A defect inspection method for inspecting a defect on a semiconductor wafer, using plural inspection methods includes: merging hot-spot coordinates as coordinates on the semiconductor wafer, designated by a user, or coordinates where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from inspection information, after information indicating the type of coordinates are added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating the respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.
|
1. A method for inspecting a semiconductor, comprising:
merging first coordinates and second coordinates of locations on the semiconductor, wherein the first coordinates and the second coordinates have respective coordinate type information, the first coordinates are hot-spot coordinates where a systematic defect can occur, and the second coordinates are defect coordinates of the semiconductor;
deciding an inspection sequence of the merged coordinates; and
inspecting the merged coordinates using a selected inspection method that is selected from a plurality of different inspection methods based on the respective coordinate type information.
11. A device for inspecting a semiconductor, comprising:
an operation unit that merges first coordinates and second coordinates of locations on the semiconductor, wherein the first coordinates and the second coordinates have respective coordinate type information, the first coordinates are hot-spot coordinates where a systematic defect can occur, and the second coordinates are defect coordinates of the semiconductor, and decides an inspection sequence of the merged coordinates; and
a control unit that inspects the merged coordinates using a selected inspection method that is selected from a plurality of different inspection methods based on the respective coordinate type information.
2. The method according to
wherein the inspection sequence is decided based on moving time of a stage located under the semiconductor.
3. The method according to
wherein the different inspection methods are a first inspection method to inspect the first coordinates and a second inspection method to inspect the second coordinates.
4. The method according to
5. The method according to
6. The method according to
7. The method according to
wherein type information of the first coordinates is systematic defect, and
wherein the second coordinates are obtained in advance by another inspection system.
8. The method according to
9. The method according to
10. The method according to
12. The device according to
wherein the inspection sequence is decided based on moving time of a stage located under the semiconductor.
13. The device according to
wherein the different inspection methods are a first inspection method to inspect the first coordinates and a second inspection method to inspect the second coordinates.
14. The device according to
15. The device according to
16. The device according to
17. The device according to
wherein type information of the first coordinates is a systematic defect, and
wherein the second coordinates are obtained in advance by another inspection system.
18. The device according to
19. The device according to
20. The device according to
|
The present invention relates to a method for observing and inspecting a defect that has occurred during the manufacture of a semiconductor product, and a defect inspection device using the same.
In order to secure earnings in the manufacture of a semiconductor wafer, it is important to quickly start up a manufacturing process thereof to thereby cause transition to a high-yield mass production system to take place at an early stage. For this purpose, various types of inspection • measurement devices are introduced into a production line. For the purpose of deciding a process condition enabling a desired circuit pattern to be formed at an early stage, a procedure has been in practice whereby a plurality of wafers or chips are prepared by intentionally varying, for example, a process condition in a process startup stage, an inspection is performed against the wafers or the chips, and a process condition is decided on the basis of a result of the inspection. Meanwhile, an inspection on a wafer in a mass production stage is performed for the purpose of process monitoring. More specifically, a sampling inspection of a wafer is performed in a stage halfway through the manufacture of the wafer to thereby examine whether or not a defect has occurred to the surface of the wafer, or whether or not abnormality is present on a circuit pattern formed on the surface of the wafer. If a defect or abnormality of the circuit pattern is detected as a result of the inspection, the cause thereof is looked into, and a necessary countermeasure is taken.
A defect observation device is a device for capturing a high-resolution image of detect coordinates of a wafer, using the output of the other inspection device, thereby outputting the image. Since progress has since been made in the miniaturization of a semiconductor manufacturing process to be accompanied by a defect size reaching to the order of several tens of nm, resolution on the order of several nm is required in order to observe a defect in detail. For this reason, an observation device (hereinafter referred to as a Review SEM) using a scanning electron microscope (SEM) has lately been in widespread use. A method for detecting a defect by comparing a captured-image of a defective site with an image of a non-defective product is described in Japanese Unexamined Patent Application Publication No. 2001-189358. Further, a method for detecting a defect from one sheet of an image that has captured a defective site, is described in Japanese Unexamined Patent Application Publication No. 2007-40910.
A method for deciding coordinates on a wafer, the coordinates being those to be reviewed between defect reviews, in an inspection device having not less than two inspection systems, is described in U.S. Pat. No. 7,904,845.
In order to produce a semiconductor wafer at a high yield, it is important to get hold of an occurrence frequency for every defect types occurring in a production process, and identify the cause of occurrence of a fatal defect to be subsequently fed back.
As a result of the progress made in the miniaturization of the semiconductor manufacturing process, a fatal defect has turned more microscopic in size. Further, a defect includes a random defect, and a systematic defect. The random defect has variation in respect of occurrence frequency, defect state, and defect magnitude, and an occurrence-location thereof is unpredictable. In the case of the systematic defect, a location susceptible to occurrence is attributable to a circuit pattern, and so forth, so that the location is often constant. However, there can be the case where the systematic defect does not occur, in which case, it is difficult to determine whether or not a pattern state is defective as compared with the case of the random defect.
Accordingly, if an optical inspection device is set so as to have sensitivity capable of detecting a microscopic defect, this will create a problem of detecting manufacturing tolerance, noise, and so forth, which do not represent a defect, on a massive scale.
Since an image in high-resolution can be acquired using the SEM, a microscopic defect can be detected in high-resolution, however, it takes time to capture the image as compared with the case of using the optical inspection device, so that it is not practical to inspect the whole surface of a wafer, so that deterioration in throughput poses a problem.
In this connection, the coordinates of the systematic defect are predicted in the method according to U.S. Pat. No. 7,904,845, however, a method for resolving the problem described as above has not been disclosed.
It is therefore an object of the invention to provide an inspection method capable of striking a balance between high throughput and capture rate of a defect in the case of executing a defect inspection including a defect review using an optical inspection device, and a fixed-point inspection using an SEM.
To that end, according to one aspect of the present invention, there is provided a method for inspecting a defect on a semiconductor wafer, using a plurality of inspection methods. The method includes merging hot-spot coordinates as coordinates on the semiconductor wafer, where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from other inspection device output information, after information indicating a type of coordinates is added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.
According to the aspect of the present invention, a highly accurate inspection can be carried out at high throughput in the case of executing the defect review, and the fixed-point inspection.
An image auto-classification device according to a first embodiment of the invention is hereinafter described. With the present embodiment, there is described the case of classifying images captured by an observation device provided with a scanning electron microscope (SEM); however, an imaging device of the invention may be a device other than the SEM, and may be an imaging device using a charged particle beam such as ion, and so forth.
A method for acquiring an image of designated coordinates is described hereinafter. First, the wafer 108 as a target for a captured-image is placed on the stage 109 by a robot arm controlled by the wafer-transport controller 201. Then, the stage 109 is moved by the stage controller 202 such that an image-capture visual field is included in a beam-irradiation range. At this point in time, measurement of a stage position is executed in order to absorb a shift-error of the stage, and the irradiation location of the electron beam is adjusted by the beam-shift controller 203 in such a way as to cancel the shift-error out. The electron beam is emanated from the electron source 110 so as to scan inside the image-capture visual field by the action of the beam-scan controller 204. The secondary electron as well as the reflection electron, emitted from the wafer, due to irradiation with the beam, are detected by the detector 111 to be turned into a digital image through the image generation unit 112. A captured-image, together with incidental information such as an image-capture condition, an image-capture date, and so forth, is stored in the image memory 205.
Reverting to
The sequence of the defect review, using a comparative inspection, is described hereinafter with reference to
The sequence of the hot-spot inspection is described hereinafter with reference to
Further, if the misregistration is insignificant, there is no need for executing the capturing of the positioning images (the step S502), and the determination on the position of the captured-image (the step S503). The parameters stored in the recipe can be substituted for these steps. Further, the captured-image of a hot-spot may be kept stored, and the detection of defects (step S505), and the classification of the defects (step S506) may be comprehensively carried out later on.
Next, setting of the captured-image coordinate information (the step S308) is described hereinafter. This processing is a processing whereby the detected defect coordinates as inputted are merged with the hot-spot coordinates, after adding respective attributes thereto. The detected defect coordinates are defect coordinates that are detected by the other inspection device. Further, the detected defect coordinates as an input may be the result of sampling executed in advance, or the detected defect coordinates that are inputted may be sampled before the merging. The hot-spot coordinates are coordinates of a hot-spot where a user wants to execute inspection, such as a location where the systematic defect is susceptible to occurrence, and so forth. In general, the hot-spot is often designated in a chip coordinate system.
Now, description reverts to the setting of the captured-image coordinate information (the step S308). After conversion of the hot-spot coordinates in the chip coordinate system into those of the wafer coordinate system by the method describe as above, the hot-spot coordinates are merged with the detected defect coordinates. In this case, the respective attributes are added thereto such that the detected defect coordinates are distinguished from the hot-spot coordinates.
In the step of the captured-image sequence setting (step S309), the captured-image sequence is rearranged such that shift-time of the stage becomes shorter with respect to the coordinates that are merged. The shift-time of the stage accrues from a shift distance of the table, and the shift-time of the stage includes the shift distance of the table. In general, a stage-shift takes time, so that the shorter the shift-time of the stage is, the higher will be a throughput-enhancement effect. However, since this problem is a combinational optimization problem, if the number of the hot-spots increases, it will become difficult to look for the optimal solution whereby the shift time is rendered the shortest within practical time. Accordingly, a quasi-optimal solution may be found using a simulated annealing method, and so forth. Further, if captured-image coordinates of plural points are present within a range where the coordinates can be shifted by a beam shift, the respective shift coordinates of the stage may be merged with each other, thereby causing a visual field to be shifted using the beam shift. Further, if the image-capture condition (for example, the probe current, the accelerating voltage, and so forth) at the time of capturing the image of the hot-spot coordinates differs from that at the time of capturing the image of the detected defect coordinates, a combination may be made such that time required for change-over is included in the shift-time from the hot-spot coordinates to the detected defect coordinates to thereby solve an optimization problem. More specifically, the shift time between coordinates identical in attribute to each other includes only time required for shifting of the stage, whereas the shift time between coordinates differing in attribute from each other includes time required for change-over of image-capture time in addition to the time required for the shifting of the stage. However, if the shifting of the stage can be executed in parallel with the change-over of the image-capture condition, longer time is regarded as the shift time. By so doing, the shift sequence can be decided after taking time for the change-over of the image-capture condition into consideration, thereby enabling the image-capture time in whole to be shortened.
Next, in connection with the extraction of the hot-spot coordinate candidates (the step S313), an overall flow for extracting the hot-spot on the wafer is first described using the present function with reference to
First, the flow for extracting the hot-spot on the wafer is described with reference to
Further, hot-spot coordinates 902 extracted from design information, and user's experience are kept stored in advance. Then, the defect review and the hot-spot inspection are executed according to the flow shown in
The contents of processing for the hot-spot coordinate candidates extraction (the step S313) are described hereinafter with reference to
A user interface according to the invention is henceforth described.
As described in the foregoing, at the time of executing the defect review, and the hot-spot inspection, the hot-spot coordinates are merged with the detected defect coordinates after adding respective attributes thereto, and the captured-image sequence is set such that the shift distance of the stage can be rendered shorter, thereby executing image-capturing, while changing over the respective sequences according to the attributes added to the coordinates, respectively, whereupon sharing of the sequence of the wafer alignments, and the sequence of the focus map estimations is enabled, and stage-shift time can be reduced, so that the defect review, and the hot-spot inspection can be efficiently executed. Furthermore, an image high in coincidence with an image acquired by the hot-spot inspection is searched from the result of the defect review to extract a hot-spot candidate, thereby enabling a user to get hold of a location susceptible to occurrence of a systematic defect. Thus, the use of the present invention enables a user to more quickly get hold of the occurrence frequency by the defect type, and the occurrence tendency in the wafer plane with a higher accuracy, so that the user can quickly obtain guidelines for deciding process-improvement guidelines.
With a second embodiment of the invention, in particular, there is described hereinafter the information indicating the type of coordinates. In the step S1801, coordinates that are empirically judged, and decided by a user may be inputted as the hot-spot coordinates. The hot-spots may be worked out on the basis of an inspection result outputted from the other inspection device to be reflected on the inspection information. Or hot-spots as predicted on the basis of design data on a semiconductor wafer may be inputted.
In order to calculate the coordinates of the reference points in the step (S1808), it need only be sufficient to calculate coordinates designed such that a circuit pattern identical to that of the defect-point is formed. As the simplest method, it need only be sufficient to calculate coordinates corresponding to a defect-point in a die adjacent to a die where a defect-point is present. In other words, it need only be sufficient to increase, or decrease the coordinates of a defect-point, in magnitude, by the magnitude corresponding to one chip size. Further, an adjacent die is unnecessary, and reference point coordinates on a wafer may be worked such that a captured image thereof can be taken in the vicinity of the inputted hot-spot coordinates, or the inputted defect-point coordinates, or the reference point coordinates as already worked out. As described later on, an attribute of “reference” is added to the reference point coordinates worked out as above, in the step S1802, and linkage information on a corresponding defect-point is stored as incidental information.
The merging between the hot-spot coordinates and the inspection information, in the step S1802, is described hereinafter with reference to
In the step S1803, a method for determining the captured-image sequence is the same as in the case of the first embodiment. Otherwise, captured-image sequence may be decided such that the inspection time can be shortened by taking not only the attribute of the inspection coordinates but also the shift-time of the stage up to the reference coordinates.
The defect inspection in the step S1804 is described with reference to
The case of the attribute being “reference” is described hereinafter. The stage is shifted up to the reference image to thereby take a captured-image of the reference image.
The sequence in the case of the attribute being “reference” and “defect” is called an observation, and the sequence in the case of the attribute being “hot-spot” is called hot-spot inspection, or simply as an inspection.
In the case of the attribute being “hot-spot”, the stage is shifted to the hot-spot coordinates referred to (addressing), and the inspection is conducted by taking a captured-image of the hot-spot coordinates.
In other words, after making a judgment on the information indicating the type of coordinates, the inspection or the observation is conducted, while changing over between the inspection sequences according to the type of the coordinates.
As described in the foregoing, at the time when the defect review, and the hot-spot inspection are executed, the hot-spot coordinates are merged with the inspection information after adding the information indicating the type of the coordinates thereto, the captured-image sequence is decided, and the inspection or the observation is carried out, while changing over between the sequences according to attributes, in particular, included in the information indicating the type of coordinates, whereupon the sharing of the sequence of the wafer alignments, and the sequence of the focus map estimations is enabled, and the stage-shift time can be reduced, so that the defect review (the observation), and the hot-spot inspection can be efficiently executed. Further, the image high in coincidence with the image acquired by the hot-spot inspection is searched on the basis of the result of the defect review to extract the hot-spot candidate, thereby enabling a user to get hold of the location susceptible to occurrence of the systematic defect. Therefore, the use of the present invention enables a user to more quickly get hold of the occurrence frequency by the defect type, and the occurrence tendency in the wafer plane with a higher accuracy, so that the user can quickly obtain the guidelines for deciding the process-improvement guidelines.
Miyamoto, Atsushi, Harada, Minoru, Hirai, Takehiro, Fukunaga, Fumihiko
Patent | Priority | Assignee | Title |
10872406, | Apr 13 2018 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hot spot defect detecting method and hot spot defect detecting system |
Patent | Priority | Assignee | Title |
7873202, | Aug 05 2005 | HITACHI HIGH-TECH CORPORATION | Method and apparatus for reviewing defects of semiconductor device |
7904845, | Dec 06 2006 | KLA-Tencor Corporation | Determining locations on a wafer to be reviewed during defect review |
20030058435, | |||
20050234672, | |||
20060238753, | |||
20060284088, | |||
20070031026, | |||
20070236689, | |||
20080163140, | |||
20080232671, | |||
20080298669, | |||
20110276935, | |||
JP2001189358, | |||
JP2005302906, | |||
JP200740910, | |||
JP2008233687, | |||
JP2008300670, | |||
JP201085145, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 06 2012 | Hitachi High-Technologies Corporation | (assignment on the face of the patent) | / | |||
Jan 15 2014 | HARADA, MINORU | Hitachi High-Technologies Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032196 | /0346 | |
Jan 15 2014 | MIYAMOTO, ATSUSHI | Hitachi High-Technologies Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032196 | /0346 | |
Jan 20 2014 | HIRAI, TAKEHIRO | Hitachi High-Technologies Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032196 | /0346 | |
Jan 20 2014 | FUKUNAGA, FUMIHIKO | Hitachi High-Technologies Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032196 | /0346 | |
Feb 12 2020 | Hitachi High-Technologies Corporation | HITACHI HIGH-TECH CORPORATION | CHANGE OF NAME AND ADDRESS | 052259 | /0227 |
Date | Maintenance Fee Events |
Apr 04 2019 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Apr 05 2023 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Date | Maintenance Schedule |
Oct 20 2018 | 4 years fee payment window open |
Apr 20 2019 | 6 months grace period start (w surcharge) |
Oct 20 2019 | patent expiry (for year 4) |
Oct 20 2021 | 2 years to revive unintentionally abandoned end. (for year 4) |
Oct 20 2022 | 8 years fee payment window open |
Apr 20 2023 | 6 months grace period start (w surcharge) |
Oct 20 2023 | patent expiry (for year 8) |
Oct 20 2025 | 2 years to revive unintentionally abandoned end. (for year 8) |
Oct 20 2026 | 12 years fee payment window open |
Apr 20 2027 | 6 months grace period start (w surcharge) |
Oct 20 2027 | patent expiry (for year 12) |
Oct 20 2029 | 2 years to revive unintentionally abandoned end. (for year 12) |