A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A thermally conductive and electrically resistive polymer substantially fills the at least one aperture and contacts the exposed portion of the semiconductor stack structure. One method for manufacturing the semiconductor device includes forming patterned apertures in the wafer handle to expose a portion of the semiconductor stack structure. The patterned apertures may or may not be aligned with sections of RF circuitry making up the semiconductor stack structure. A following step includes contacting the exposed portion of the semiconductor stack structure with a polymer and substantially filling the patterned apertures with the polymer, wherein the polymer is thermally conductive and electrically resistive.
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17. A method of manufacture for a semiconductor device comprising:
providing a semiconductor stack structure attached to a wafer handle;
forming a pattern of polygon-shaped openings that extends through the wafer handle to an exposed portion of the semiconductor stack structure, wherein the polygon-shaped openings each have N number of sides, wherein N is a positive counting number greater than 2 and less than infinity; and
contacting the exposed portion of the semiconductor stack structure with a polymer and substantially filling the polygon-shaped openings with the polymer.
1. A semiconductor device comprising:
a semiconductor stack structure;
a wafer handle attached to the semiconductor stack structure and having a pattern of polygon-shaped openings that extends through the wafer handle to an exposed portion of the semiconductor stack structure, wherein the polygon-shaped openings each have N number of sides, wherein N is a positive counting number greater than 2 and less than infinity; and
a polymer substantially filling the polygon-shaped openings and contacting the exposed portion of the semiconductor stack structure, wherein the polymer is thermally conductive and electrically resistive.
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The present application claims priority to U.S. Provisional Patent Application No. 61/815,327, filed Apr. 24, 2013, and U.S. Provisional Patent Application No. 61/816,207, filed Apr. 26, 2013.
The present application claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/852,648, filed Mar. 28, 2013, entitled “SEMICONDUCTOR DEVICE WITH A POLYMER SUBSTRATE AND METHODS OF MANUFACTURING THE SAME,” which claims priority to U.S. Provisional Patent Application No. 61/773,490, filed Mar. 6, 2013.
The present application is related to concurrently filed U.S. patent application Ser. No. 14/260,909, entitled “SILICON-ON-DUAL PLASTIC (SODP) TECHNOLOGY AND METHODS OF MANUFACTURING THE SAME,” which claims priority to U.S. Provisional Patent Application No. 61/816,207, filed Apr. 26, 2013.
All of the applications listed above are hereby incorporated herein by reference in their entireties.
This disclosure relates to semiconductor devices and methods for manufacturing the same.
Radio frequency complementary metal oxide (RFCMOS) silicon-on-insulator (SOI) RF power switches are devices that are essential for practically every mobile handset currently on the market. Existing RFCMOS SOI technologies used to manufacture these devices provide excellent performance in increasingly complex multi-throw RF switches, tunable RF capacitance arrays, and antenna RF tuners. Conventional RFCMOS SOI technologies are built on high resistivity CMOS wafer handles that have resistivities ranging from 1000 Ohm-cm to 5000 Ohm-cm. A power switch employing RFCMOS SOI technology uses a high resistivity wafer handle so that a plurality of relatively low voltage field effect transistors (FETs) can be stacked while maintaining a desired isolation between the low voltage FETs.
In an RF switch application for third generation (3G) and fourth generation (4G) wireless applications, a high degree of RF device linearity and a relatively very low level of RF intermodulation under RF power conditions are crucial. Therefore, inherent nonlinearities in RF devices such as CMOS n-type field effect transistor (NFET) devices must be mitigated. Another source of nonlinearities is attributed to a high resistivity silicon handle wafer region interfaced with a buried oxide (BOX) dielectric region. One proposed solution for mitigating these nonlinearities includes a trap rich silicon/oxide interface that degrades carrier lifetimes in the silicon/oxide interface. Other proposed solutions for mitigating the nonlinearities due to the high resistivity handle region interfaced with the BOX dielectric region include harmonic suppression process techniques that include a series of process steps and heating treatments to minimize nonlinearities attributed to the high resistivity handle region interfaced with the BOX dielectric region. However, all the aforementioned proposed solutions add significant complexity and cost to CMOS SOI technology. What is needed are CMOS SOI-based semiconductor devices and methods for manufacturing CMOS SOI devices that do not produce the nonlinearities attributed to the high resistivity silicon handle region interfaced with the BOX dielectric region.
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A polymer substantially fills the at least one aperture and contacts the exposed portion of the semiconductor stack structure. The polymer is thermally conductive and electrically resistive.
In exemplary embodiments, a pattern of apertures extending through the wafer handle to exposed portions of the semiconductor stack structure are completely filled. In other exemplary embodiments, the polymer is further disposed on an external planar surface of the wafer handle to a predetermined thickness. In an additional embodiment, a silicon nitride layer covers portions of the semiconductor stack structure previously exposed during the formation of patterned apertures.
One method for manufacturing the semiconductor device includes forming the patterned apertures in the wafer handle to expose a portion of the semiconductor stack structure. The patterned apertures may or may not be aligned with sections of RF circuitry making up the semiconductor stack structure. A following step includes contacting the exposed portion of the semiconductor stack structure with a polymer and substantially filling the patterned apertures with the polymer, wherein the polymer is thermally conductive and electrically resistive. This step may continue to further dispose the polymer onto an external planar surface of the wafer handle. Another method adds a silicon nitride layer to cover the portions of the semiconductor stack structure before filling the patterned apertures with polymer.
Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.
The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “over,” “on,” “disposed on,” “in,” or extending “onto” another element, it can be directly over, directly on, directly disposed on, directly in, or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over,” “directly on,” “directly disposed on,” “directly in,” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. Moreover, the phrase “electrically resistive” used herein means having a resistance greater than 106 Ohm-cm. Also, the phrase “thermally conductive” used herein means having a thermal conductivity greater than 2 watts per meter Kelvin (W/mK).
Traditional RFCMOS SOI technologies have reached a fundamental barrier due to limitations inherent to silicon wafer handles that prevent the relatively better insulating characteristics available in group IV, group III-V, or sapphire wafer handles. The disclosed semiconductor device replaces the silicon wafer handle with a polymer. As such, the semiconductor device of this disclosure eliminates the need for a high resistivity silicon wafer handle in a provided semiconductor stack structure.
Advanced silicon wafer handles for RF switch applications have resistivities that range from 1000 Ohm-cm to 5000 Ohm-cm and are significantly more costly than standard silicon wafer handles having much lower resistivities. Moreover, relatively complex process controls are needed to realize high resistivity in advanced silicon wafer handles. For these reasons, standard silicon wafer handles are used ubiquitously in standard SOI technologies. However, standard silicon wafer handles with their much lower resistivities are not conducive for stacking a plurality of relatively low voltage field effect transistors (FETs) while maintaining a desired isolation between the low voltage FETs. Fortunately, the polymer of the present disclosure replaces the silicon wafer handle and thus eliminates the problems associated with both high and low resistivity silicon wafer handles.
Additionally, the methods of the present disclosure allow for an immediate migration to 300 mm wafer handles for use in RF power switch applications. This is an important development since there is currently no commercially viable high volume supply of high resistivity RFSOI wafer handles in the 300 mm wafer diameter format. Fabricating the present semiconductor devices on 300 mm diameter wafer handles would provide a significant improvement in die costs. Moreover, the need for a trap rich layer and/or harmonic suppression techniques is eliminated, thereby resulting in a significantly simpler process flow and lower cost.
Further still, the polymer is expected to eliminate RF nonlinear effects resulting from the interface between the BOX layer and the silicon wafer handle used in traditional semiconductor processes to manufacture RF switch devices. The present methods realize RF switch devices that have linear characteristics relatively close to ideal linear characteristics.
Additionally, the semiconductor device of this disclosure offers a near ideal voltage stacking of NFET transistors. Traditionally, the number of NFET devices that can be stacked is limited by silicon wafer handle resistivity combined with the interface effects between the BOX layer and the silicon wafer handle. This issue essentially limits the number of practical NFET transistors that can be stacked and thus limits the highest RF operating voltage for the resulting NFET transistor stack. Replacing silicon wafer handles with the polymer of the present disclosure allows relatively many more NFET transistors to be practically ideally stacked. The resulting semiconductor device is operable at relatively much higher RF power levels and RMS voltages than is traditionally allowable on silicon handle wafer technologies.
Furthermore, the highest RF frequency of operation of RF power switches built with the disclosed polymer can be extended beyond the highest frequency of operation achievable with traditional RFCMOS SOI technologies. Typically, a silicon wafer handle resistivity is in the range of 1000-3000 Ohm-cm, which effectively imposes an operational high frequency limit. The resulting resistivity of the polymer of the semiconductor device taught in this disclosure is several orders of magnitude higher than what is achieved in high resistivity silicon. For instance, there are polymers with nearly ideal electrically insulating characteristics, with resistivity values similar to what is obtained in gallium arsenide (GaAs) and sapphire semi-insulating wafer handles.
In this exemplary case, the first surface 38 is also an exposed surface of the BOX layer 14. The chemical etch can be implemented with a reactive ion etch and/or with potassium hydroxide. An aperture mask 40 may be applied to a back-side of the silicon wafer handle 12 to prevent etching some areas of the wafer, thus allowing the silicon etch process to be selective. The aperture mask 40 is patterned using standard semiconductor lithographic techniques, and is made up of deposited layers of material such as silicon dioxide or silicon nitride, or a combination of silicon dioxide and silicon nitride. Other techniques for removal of the silicon wafer handle 12 exist and are well documented in the literature. Some of these other techniques are based on dry or wet etch processes. The process used to remove the patterned portion of the silicon wafer handle 12 is not particularly relevant to the present disclosure. However, it is desirable for the removal of the patterned portion of the silicon wafer handle 12 to be accomplished without damaging the BOX layer 14 and the remainder of the semiconductor stack structure 10 as well as the source flipchip bump 26 and the drain flipchip bump 32.
It is desirable that a polymer material usable for the polymer 42 be relatively strongly bondable to the first surface 38 of the semiconductor stack structure 10. For example, the polymer material needs a bonding strength that allows the semiconductor device 44 to be dismounted from the temporary carrier mount 36 and remain permanently bonded after additional processing steps as well as throughout the operational lifetime of the semiconductor device 44. Moreover, a desirable thickness for the polymer 42 ranges from around about 100 μm to around about 500 μm, but other desirable thicknesses for the polymer 42 can be thinner or thicker depending on the characteristics of the polymer material used to make up the polymer 42.
The polymer material making up the polymer 42 should also be a good electrical insulator. In general, the electrical resistivity of the polymer 42 should be at least 106 Ohm-cm. In at least one embodiment, the polymer has a relatively high electrical resistivity that ranges from around about 1012 Ohm-cm to around about 1016 Ohm-cm. In combination with relatively high electrical resistivity, the thermal conductivity of the polymer 42 is on the order of the thermal conductivity of typical semiconductors, which is typically greater than 2 W/mK. In one embodiment, the thermal conductivity of the polymer 42 ranges from greater than 2 W/mK to around about 10 W/mK. In yet another embodiment, the thermal conductivity of the polymer 42 ranges from around about 10 W/mK to around about 50 W/mK. As polymer science provides materials with additional thermal conductivities, these materials can be utilized in the semiconductor device of this disclosure, as there are no upper bounds for how high the polymer thermal conductivity may be with regards to this disclosure.
The semiconductor stack structure 10 is then mounted to the temporary carrier mount 36 with the source flipchip bump 26 and the drain flipchip bump 32 facing the temporary carrier mount 36 (step 102). Optionally, the silicon wafer handle 12 can be thinned to a predetermined thickness by grinding and/or etching (step 104). An exemplary thickness for the silicon wafer handle 12 after thinning is within a range of thickness from around about 50 μm to around about 150 μm. Further optionally, the aperture mask 40 can be applied to an external planar surface of the silicon wafer handle 12 (step 106). The process then continues by removing a portion of the silicon wafer handle 12 to form apertures to expose portions of the semiconductor stack structure 10 (step 108). The apertures can be formed via grinding and/or etching. The polymer 42 can then be attached to the first surface 38 of the semiconductor stack structure 10 using various polymer material disposing methods (step 110). Such methods for attaching the polymer 42 to the first surface 38 of the semiconductor stack structure 10 include, but are not limited to, injection molding, spin deposition, spray deposition, and pattern dispensing of polymer material directly onto the first surface 38 of the semiconductor stack structure 10. Once the polymer 42 is attached to the first surface 38 of the semiconductor stack structure 10, the temporary carrier mount 36 is dismounted (step 112).
The sequence of steps used in processes to manufacture the semiconductor device 44 will depend on the type of carrier and mounting processes used. There are a number of such processes available. A typical dismount step used extensively for through-substrate-via (TSV) processing includes exposing the UV adhesive tape that mounted the semiconductor stack structure 10 to a transparent quartz carrier to UV light, which alters the chemistry of the UV tape so that the semiconductor device 44 can be easily separated from the temporary carrier mount 36. The semiconductor device 44 can then be cleaned with common chemical solvents and/or plasma cleaning processes.
The semiconductor device 44 can then be singulated from an original wafer (not shown) into individual die by a number of different conventional processes. Typically, a saw operation that cuts through the semiconductor stack structure 10 and polymer 42 is the one method of die singulation. Other singulation methods such as laser sawing, laser scribing or diamond scribing can be used as alternatives.
It should be noted that the semiconductor device and methods taught in this disclosure begin with a conventionally manufactured RFSOI CMOS wafer which in this exemplary case is the semiconductor stack structure 10 disposed on the silicon wafer handle 12. However, one distinction is that there is no need for the silicon wafer handle 12 to have high resistivity, since the polymer 42 replaces substantial portions of the silicon wafer handle 12. If the semiconductor device 44 requires flipchip packaging, it should ideally already include the source flipchip bump 26 and the drain flipchip bump 32, although such a requirement may not be necessary depending on the specific characteristics of the bump or pillar packaging technology employed. In this exemplary case, it is assumed that a wafer process was completed through bumping.
The silicon nitride layer 46 may be deposited, as an example, via a plasma enhanced chemical vapor deposition (PECVD) system by the decomposition of silane and nitrogen gases, as commonly known to those skilled in the art. Such PECVD systems operate at temperatures typically between room temperature and 350° C. The silicon nitride layer 46 may also be deposited via other techniques including liquid phase chemical vapor deposition (LPCVD) and sputtered from a nitride target using RF sputtering. The silicon nitride layer 46 does not significantly impact the thermal conductivity provided by the polymer 42. In one embodiment, the thickness of the silicon nitride layer 46 ranges from around about 100 Å to around about 1000 Å. In another embodiment, the thickness of the silicon nitride layer 46 ranges from around about 1000 Å to around about 5000 Å. In yet another embodiment, the thickness of the silicon nitride layer 46 ranges from around about 5000 Å to around about 10,000 Å.
The semiconductor stack structure 10 is then mounted to the temporary carrier mount 36 with the source flipchip bump 26 and the drain flipchip bump 32 facing the temporary carrier mount 36 (step 202). Optionally, the silicon wafer handle 12 can be thinned to a predetermined thickness by grinding and/or etching (step 204). An exemplary thickness for the silicon wafer handle 12 after thinning is within a range of around about 50 μm to around about 150 μm. Further optionally, the aperture mask 40 can be applied to an external planar surface of the silicon wafer handle 12 (step 206). The process then continues by removing a portion of the silicon wafer handle 12 to form apertures to expose portions of the semiconductor stack structure 10 (step 208). The apertures can be formed via grinding and/or etching. The aperture mask 40 may optionally be removed from the external planar surface of the wafer handle 12 (step 210). Next, the at least one exposed portion of the semiconductor stack 10 is conformally coated with the silicon nitride layer 46 (step 212). The polymer 42 can then be adhered to the silicon nitride layer 46 using various polymer material disposing methods (step 214). Such methods for attaching the polymer 42 to the first surface 38 of the semiconductor stack structure 10 include, but are not limited to, injection molding, spin deposition, spray deposition, and pattern dispensing of polymer material directly onto the first surface 38 of the semiconductor stack structure 10. Once the polymer 42 is attached to the first surface 38 of the semiconductor stack structure 10, the temporary carrier mount 36 is dismounted (step 216).
Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
Costa, Julio, Carroll, Michael, Kerr, Daniel Charles, Willis, Don, Glass, Elizabeth
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