A liquid crystal display device includes a display panel, a multiplexer, an alignment circuit and a short bar circuit. The multiplexer is configured to provide a plurality of output data signals according to a plurality of switch control signals and an input data signal. During the alignment period, the alignment circuit is configured to provide a curing voltage to the display panel, and the short bar circuit is configured to couple the multiplexer to a predetermined voltage.
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8. An alignment method for use in a liquid crystal display device which includes:
a display panel having a plurality of pixels and a plurality of data lines; and
a multiplexer having an input end, a plurality of output ends coupled to the pixels, and a plurality of switches configured to control transmission paths between the input end and the plurality of output ends according to a plurality of switch control signals, respectively;
the alignment method comprising:
providing a curing voltage to the plurality of data lines and a uv light to the display panel during an alignment period;
coupling the multiplexer to a predetermined voltage for maintaining the plurality of switch control signals at a same level during the alignment period;
transmitting the curing voltage to a first side of the plurality of data lines during the alignment period; and
transmitting the curing voltage to a second side of the plurality of data lines via the multiplexer during the alignment period.
1. A liquid crystal display device, comprising:
a display panel, comprising:
a plurality of pixels;
a plurality of data lines disposed along a first direction and respectively coupled to the plurality of pixels; and
a plurality of gate lines disposed along a second direction and respectively coupled to the plurality of pixels;
a multiplexer disposed on a first side of the display panel and configured to provide a plurality of output data signals according to a plurality of first switch control signals and an input data signal, the multiplexer comprising:
an input end for receiving the input data signal;
a plurality of output ends coupled to the plurality of data lines for respectively outputting the plurality of output data signals; and
a plurality of first switches configured to control transmission paths between the input end and the plurality of output ends according to the plurality of first switch control signals;
a first alignment circuit configured to provide a curing voltage to the plurality of data lines during an alignment period;
a first short bar circuit configured to couple the multiplexer to a predetermined voltage during the alignment period; and
a second alignment circuit coupled to the plurality of data lines and configured to provide the curing voltage to the plurality of data lines during the alignment period, wherein the first alignment circuit and the second alignment circuit are disposed on opposite sides of the display panel.
12. A liquid crystal display device, comprising:
a display panel, comprising:
a plurality of pixels formed of liquid crystal molecules mixed with a uv-curable monomer;
a plurality of data lines disposed along a first direction and respectively coupled to the plurality of pixels; and
a plurality of gate lines disposed along a second direction and respectively coupled to the plurality of pixels;
a multiplexer disposed on a first side of the display panel and configured to provide a plurality of output data signals according to a plurality of first-switch control signals and an input data signal, the multiplexer comprising:
an input end for receiving the input data signal;
a plurality of output ends coupled to the plurality of data lines for respectively outputting the plurality of output data signals; and
a plurality of first switches configured to control transmission paths between the input end and the plurality of output ends according to the plurality of first-switch control signals;
a first alignment circuit configured to provide a curing voltage to the plurality of data lines during an alignment period, the first alignment circuit comprising:
a plurality of second switches each including:
a control end;
a first end for receiving the curing voltage; and
a second end coupled to a corresponding data line;
a first transmission logic gate, comprising:
an input end for receiving a common voltage;
a first control end coupled to the control ends of the pull-up switches;
an output end coupled to the first control end of the first transmission logic gate; and
a second control end for receiving a low level voltage;
a second transmission logic gate, comprising:
an input end for receiving the common voltage;
a first control end coupled to the control ends of the pull-up switches;
an output end coupled to the second control end of the first transmission logic gate; and
a second control end coupled to the second control end of the first transmission logic gate; and
a voltage buffer, comprising:
an input end coupled to the output end of the first transmission logic gate; and
an output end coupled to the control end of the second switches; and
a short bar circuit configured to couple the multiplexer to a predetermined voltage during the alignment period to turn off the multiplexer during the alignment period, wherein the alignment period is defined as a period when the uv-curable monomer is activated by a uv radiation while the first alignment circuit is providing the curing voltage to the plurality of data lines.
2. The liquid crystal display device of
3. The liquid crystal display device of
the multiplexer is disposed between the display panel and the second alignment circuit;
the curing voltage is transmitted to the plurality of data lines via the multiplexer; and
the first short bar circuit is further configured to provide the predetermined voltage for turning on the multiplexer during the alignment period.
4. The liquid crystal display device of
5. The liquid crystal display device of
a control end for receiving a second switch control signal;
a first end for receiving a high level voltage; and
a second end coupled to the gate line.
6. The liquid crystal display device of
a plurality of second switches each including:
a control end;
a first end for receiving the curing voltage; and
a second end coupled to a corresponding data line;
a first transmission logic gate, comprising:
an input end for receiving a common voltage;
a first control end coupled to the control ends of the pull-up switches;
an output end coupled to the first control end of the first transmission logic gate; and
a second control end for receiving a low level voltage;
a second transmission logic gate, comprising:
an input end for receiving the common voltage;
a first control end coupled to the control ends of the pull-up switches;
an output end coupled to the second control end of the first transmission logic gate; and
a second control end coupled to the second control end of the first transmission logic gate; and
a voltage buffer, comprising:
an input end coupled to the output end of the first transmission logic gate; and
an output end coupled to the control end of the second switches.
7. The liquid crystal display device of
a plurality of second switches each including:
a control end;
a first end for receiving the curing voltage; and
a second end coupled to a corresponding data line;
a first transmission logic gate, comprising:
an input end for receiving a common voltage;
a first control end coupled to the control ends of the pull-up switches;
an output end coupled to the first control end of the first transmission logic gate; and
a second control end for receiving a low level voltage;
a second transmission logic gate, comprising:
an input end for receiving the common voltage;
a first control end coupled to the control ends of the pull-up switches;
an output end coupled to the second control end of the first transmission logic gate; and
a second control end coupled to the second control end of the first transmission logic gate; and
a voltage buffer, comprising:
an input end coupled to the output end of the first transmission logic gate; and
an output end coupled to the control end of the second switches.
9. The alignment method of
coupling the multiplexer to the predetermined voltage for maintaining the plurality of switch control signals at the same level and for turning off the multiplexer using the predetermined voltage during the alignment period.
10. The alignment method of
11. The alignment method of
13. The liquid crystal display device of
an electrostatic discharge circuit coupled to the input end of the multiplexer and comprising:
a first diode including an anode coupled to a low level voltage and a cathode coupled to the input end of the multiplexer; and
a second diode including an anode coupled to the input end of the multiplexer and a cathode coupled to a high level voltage.
14. The liquid crystal display device of
wherein each gate line is coupled to a pull-up switch which includes:
a control end for receiving a second switch control signal;
a first end for receiving a high level voltage; and
a second end coupled to the gate line.
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1. Field of the Invention
The present invention is related to a liquid crystal display device and related alignment method, and more particularly, to a liquid crystal display device and related alignment method with ESD protection and reduced mura.
2. Description of the Prior Art
With rapid development of large-size liquid crystal display (LCD) panels, the ability to provide multi-viewing angles have become a major feature. Because of the advantages of multi-viewing angles and low response time, multi-domain vertical alignment (MVA) LCD panels have become the mainstream products of the large-size display panels.
Conventional MVA LCD panels provide multi-viewing angle function by making the liquid crystal molecules in different areas slant in different directions using protrusions (bumps). However, in addition to complicating manufacturing processes, protrusions may also block part of light, thereby lowering the aperture ratio and the brightness performance.
Therefore, polymer stabilized alignment or phase separation alignment (PSA) technology has been developed in which polymers are used to replace the protrusions in MVA LCD panels. The core of PSA technology is to forma polymer-alignment layer over a conventionally coated polyimide by mixing a UV-curable monomer into the liquid crystal molecules. The monomer is then activated by UV radiation while applying a curing voltage. The monomer reacts with the polymer layer to form a surface that fixes the pre-tilt angle of the liquid crystal molecules.
During the alignment period, the multiplexer in the prior art LCD device is floating. Unstable curing voltage or electrostatic discharge (ESD) may influence the alignment process and cause image mura which downgrades display quality.
An embodiment of the present invention provides an LCD device having a display panel, a multiplexer, an alignment circuit and a short bar circuit. The display panel includes a plurality of pixels; a plurality of data lines disposed along a first direction and respectively coupled to the plurality of pixels; and a plurality of gate lines disposed along a second direction and respectively coupled to the plurality of pixels. The multiplexer is disposed on a first side of the display panel and configured to provide a plurality of output data signals according to a plurality of switch control signals and an input data signal. The multiplexer includes an input end for receiving the input data signal; a plurality of output ends coupled to the plurality of data lines for respectively outputting the plurality of output data signals; and a plurality of switches configured to control transmission paths between the input end and the plurality of output ends according to the plurality of switch control signals. The alignment circuit is configured to provide a curing voltage to the plurality of data lines during an alignment period. The short bar circuit is configured to couple the multiplexer to a predetermined voltage during the alignment period.
An embodiment of the present invention further provides an alignment method for use in an LCD device. The alignment method includes providing the LCD device which includes a display panel having a plurality of pixels and a plurality of data lines; a multiplexer having an input end, a plurality of output ends coupled to the pixels, and a plurality of switches configured to control transmission paths between the input end and the plurality of output ends according to a plurality of switch control signals, respectively; providing a curing voltage to the plurality of data lines and a UV light to the display panel during an alignment period; and coupling the multiplexer to a predetermined voltage for maintaining the plurality of switch control signals at a same level during the alignment period.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the embodiments of the present invention, the LCD panel 10 may be manufactured using PSA technology in which a plurality of data lines DL1˜DLM (M is an integer larger than 1), a plurality of gate lines GL1˜GLN (N is an integer larger than 1), and a plurality of pixels PX are disposed on the active area. The gate driving circuit 20 is configured to provide gate driving signals for turning on each row of pixels. The source driving/testing circuit 30 and the multiplexer 40 are configured to provide data signals for charging each column of pixels.
Referring to
Referring to
Referring to
Referring to
Referring to
In the embodiment illustrated in
In the embodiments of the present invention, the gate driving circuit 20 may include pull-up switches T1˜TN and shift registers SR1˜SRN. Each pull-up switch includes a first end for receiving a bias voltage VGH, a second end coupled to a corresponding gate line, and a control end for receiving a control signal CTL. During the alignment period, the control signal CTL is set to low level for turning on the pull-up switches T1˜TN so that the bias voltage VGH may turn on the pixels PX for receiving the curing voltage VPSA. During the display period, the control signal CTL is set to high level for turning off the pull-up switches T1˜TN, thereby preventing the bias voltage VGH from reaching the gate lines GL1˜GLN. At the same time, the control signal CTL is inverted to low level by a voltage buffer 66 for turning off the switches B1˜BN, thereby preventing the pixels PX from receiving the curing voltage VPSA.
In the embodiments of the present invention, the multiplexer 40 may adopt 1-to-M scheme and may include an input end, M output ends and M switches A1˜AM. The input end of the multiplexer 40 is coupled to the source driving/testing circuit 30 for receiving an input signal DIN. The switches A1˜AM are configured to control the signal transmission paths between the input end and the output ends of the multiplexer 40 according to the control signals SW1˜SWM, respectively. Therefore, the multiplexer 40 may output data signals DOUT1˜DOUTM to the data lines DL1˜DLM, respectively.
In the embodiments of the present invention, the alignment circuits 50 and 55 may each include M switches B1˜BN, transmission logic gates 62 and 64, and a voltage buffer 66. The switches B1˜BN include first ends respectively coupled to the data lines DL1˜DLM, second ends for receiving a curing voltage VPSA, and control ends coupled to the output end of the voltage buffer 66. Each of the transmission logic gates 62 and 64 includes a first end coupled to the control ends of the pull-up switches T1˜TN, a second control end for receiving a bias voltage VGL, and an input end for receiving a bias voltage VCOM. The output end of the transmission logic gate 62 is coupled to the input end of the voltage buffer 66, and the output end of the transmission logic gate 64 is coupled to receive the bias voltage VGL. The bias voltage VGH may be a high level voltage, the bias voltage VGL may be a low level voltage, and the bias voltage VCOM may be a common voltage.
In the embodiments of the present invention, the short bar circuit 60 may include M switches C1˜CM, transmission logic gates 72 and 74, and a voltage buffer 76. The switches C1˜CM include first ends respectively coupled to the control ends of the switches A1˜AM, second ends for receiving a predetermined voltage VMUX, and control ends coupled to the output end of the voltage buffer 76. Each of the transmission logic gates 72 and 74 includes a first end coupled to the control ends of the pull-up switches T1˜TN, a second control end for receiving a bias voltage VGL, and an input end for receiving a bias voltage VCOM. The output end of the transmission logic gate 72 is coupled to the input end of the voltage buffer 76, and the output end of the transmission logic gate 74 is coupled to receive the bias voltage VGL. The bias voltage VGH may be a high level voltage, the bias voltage VGL may be a low level voltage, and the bias voltage VCOM may be a common voltage.
During the alignment period, the control signal CTL is set to turn on the switches B1˜BM so that the data lines DL1˜DLM may be coupled to the curing voltage VPSA. Meanwhile, the control signal CTL is set to turn on the switches C1˜CM so that the control ends of the switches A1˜AM may be coupled to the predetermined voltage VMUX.
In the LCD devices 100, 200, 300 and 500 according to embodiments of the present invention, the predetermined voltage VMUX may be set to the turn-off voltage of the switches A1˜AM or smaller than the turn-on voltage of the switches A1˜AM so as to turn off the multiplexer 40 during the alignment period. The turned-off multiplexer 40 may prevent the ESD generated by the source driving/testing circuit 30 from reaching the data lines DL1˜DLM, thereby improving image mura.
In the LCD device 400 according to embodiments of the present invention, the predetermined voltage VMUX may be set to the turn-on voltage of the switches A1˜AM or larger than the turn-on voltage of the switches A1˜AM so as to turn on the multiplexer 40 during the alignment period. The second alignment circuit 55 may share the ESD present at the input end of the multiplexer 40, thereby improving image mura.
During the alignment period, the multiplexer in the LCD device of the present invention is coupled to a predetermined voltage in order to prevent unstable curing voltage or ESD from influencing the curing process. The display quality can thus be improved by reducing image mura.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Patent | Priority | Assignee | Title |
| 10636377, | Nov 21 2017 | AU Optronics Corporation | Multiplexer circuit and display panel thereof |
| Patent | Priority | Assignee | Title |
| 20030001809, | |||
| 20060187170, | |||
| 20060221701, | |||
| 20070001962, | |||
| 20120133631, | |||
| 20120140157, | |||
| KR1020060092676, | |||
| TW200636664, | |||
| TW201003190, | |||
| TW297484, |
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