A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an n-type substrate and an epitaxial structure on a front-side of the n-type substrate. The epitaxial substrate includes a P-type layer adjacent to the n-type substrate and one or more additional SiC layers on the P-type layer opposite the n-type substrate. The semiconductor device also includes one or more openings through the n-type substrate that extend from a back-side of the n-type substrate to the P-type layer and a back-side contact on the back-side of the n-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the n-type substrate.
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13. A method of fabricating a semiconductor device, comprising: providing an epitaxial structure on a first side of an n-type Silicon Carbide substrate, the epitaxial structure comprising a P-type Silicon Carbide layer adjacent to the n-type Silicon Carbide substrate; forming one or more openings through the n-type Silicon Carbide substrate that extend from a second side of the n-type Silicon Carbide substrate to the P-type Silicon Carbide layer in the epitaxial structure, the one or more openings exposing greater than or equal to about 40% of the P-type Silicon Carbide layer; forming a plurality of spaced apart highly doped regions in the P-type Silicon Carbide layer through the one or more openings; and providing a contact on the second side of the n-type Silicon Carbide substrate and within the one or more openings through the n-type Silicon Carbide substrate such that the contact is in physical and electrical contact with the P-type Silicon Carbide layer.
1. A semiconductor device comprising:
an n-type Silicon Carbide substrate;
an epitaxial structure on a first side of the n-type Silicon Carbide substrate, the epitaxial structure comprising a P-type Silicon Carbide layer adjacent to the n-type Silicon Carbide substrate;
a plurality of spaced apart highly doped regions formed in the P-type Silicon Carbide layer;
one or more openings through the n-type Silicon Carbide substrate corresponding to the plurality of spaced apart highly doped regions the that extend from a second side of the n-type Silicon Carbide substrate to the P-type Silicon Carbide layer in the epitaxial structure, the second side of the n-type Silicon Carbide substrate being opposite the first side of the n-type Silicon Carbide substrate;
a first contact on the epitaxial structure opposite the n-type Silicon Carbide substrate; and
a second contact on the second side of the n-type Silicon Carbide substrate and within the one or more openings through the n-type Silicon Carbide substrate such that the second contact is in physical and electrical contact with the P-type Silicon Carbide layer;
wherein, in a forward conduction state of the semiconductor device, current flows between the first contact and the second contact through the epitaxial structure.
2. The semiconductor device of
3. The semiconductor device of
4. The semiconductor device of
5. The semiconductor device of
6. The semiconductor device of
7. The semiconductor device of
8. The semiconductor device of
9. The semiconductor device of
10. The semiconductor device of
11. The semiconductor device of
an n-type epitaxial layer between the P-type Silicon Carbide layer and the n-type Silicon Carbide substrate;
wherein the one or more openings through the n-type Silicon Carbide substrate extend from the second side of the n-type Silicon Carbide substrate through the n-type epitaxial layer to the P-type Silicon Carbide layer in the epitaxial structure.
12. The semiconductor device of
14. The method of
thinning the n-type Silicon Carbide substrate; and
after thinning the n-type Silicon Carbide substrate, etching the n-type Silicon Carbide substrate to form the one or more openings through the n-type Silicon Carbide substrate that extend from the second side of the n-type Silicon Carbide substrate to the P-type Silicon Carbide layer in the epitaxial structure.
15. The method of
16. The method of
17. The method of
18. The method of
19. The method of
20. The method of
21. The method of
22. The method of
23. The method of
24. The method of
providing an n-type Silicon Carbide layer on the n-type Silicon Carbide substrate; and
providing the P-type Silicon Carbide layer on the n-type Silicon Carbide layer opposite the n-type Silicon Carbide substrate;
wherein the one or more openings through the n-type Silicon Carbide substrate extend from the second side of the n-type Silicon Carbide substrate through the n-type Silicon Carbide layer to the P-type Silicon Carbide layer in the epitaxial structure.
25. The method of
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This invention was made with government funds under contract number W911 NF-10-2-0038 awarded by the Army. The U.S. Government may have rights in this invention.
The present disclosure relates to semiconductor devices and more particularly relates to vertical semiconductor devices formed in Silicon Carbide (SiC) having a P-type backside contact layer (e.g., an N-channel Insulated Gate Bipolar Transistor (IGBT), an N-channel Gate Turn-Off thyristor (GTO), an N-channel thyristor, a PNP Bipolar Junction Transistor (BJT), or a P-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET)).
Silicon Carbide (SiC) power devices provide superior performance over power devices formed in other material systems. In particular, SiC power devices have numerous advantages over Silicon (Si) power devices such as, for example, higher breakdown field (˜10×) and thus, for the same breakdown voltage, lower specific on-resistance and faster switching; higher thermal conductivity (˜3×) and thus higher current densities; and higher bandgap (˜3×) and thus higher temperature of operation. Power devices are typically vertical devices. As such, current flows through a vertical power device between one contact on a front-side of the power device and another contact on a back-side of the power device.
Embodiments of a Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type SiC substrate and an epitaxial structure on a front-side of the SiC substrate. The epitaxial substrate includes a P-type SiC layer adjacent to the N-type SiC substrate and one or more additional SiC layers on the P-type SiC layer opposite the N-type SiC substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type SiC layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type SiC layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type SiC substrate.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
One issue that arises for some Silicon Carbide (SiC) power devices, such as an SiC N-channel Insulated Gate Bipolar Transistor (IGBT) or an N-channel Gate Turn-Off thyristor (GTO), is that the back-side contact needs to be connected to a P-type region, where the P-type region needs to be heavily doped (i.e., doped >1018 dopants per cubic centimeter (cm3)) so that the P-type region can act as an efficient injector of holes during forward conduction while providing minimal resistance. A natural way to fabricate these SiC power devices would be to use a P-type substrate and then grow the needed epitaxial structure on top of the P-type substrate. However, high quality P-type SiC substrates are difficult, and thus costly, to produce. In addition, holes have a very low mobility in SiC, which makes P-type SiC substrates very resistive. Fabricating power devices on a P-type SiC substrate would therefore introduce a large parasitic resistance, resulting in low efficiency. As such, there is a need for SiC power devices having back-side contacts to a P-type region that avoid the need for costly and highly resistive P-type SiC substrates, and methods of fabrication thereof.
Embodiments of a Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type SiC substrate and an epitaxial structure on a front-side of the SiC substrate. The epitaxial substrate includes a P-type SiC layer adjacent to the N-type SiC substrate and one or more additional SiC layers on the P-type SiC layer opposite the N-type SiC substrate. The semiconductor device also includes one or more openings through the N-type SiC substrate that extend from a back-side of the N-type SiC substrate to the P-type SiC layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type SiC layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type SiC substrate. By using the N-type SiC substrate and the opening(s) through the N-type SiC substrate for the contact to the P-type SiC layer, the need for a P-type SiC substrate is avoided, which in turn reduces the cost and complexity of fabricating the semiconductor device.
Before discussing various embodiments of the disclosed semiconductor device and methods of fabrication thereof, a discussion of the state of the art and the problems associated therewith is beneficial. In this regard,
In this example, the IGBT 10 also includes guard rings 32 formed around a periphery of an active area of the IGBT 10. The guard rings 32 form an edge termination for the IGBT 10. In addition, a passivation and/or encapsulation material 34 is formed over the front-side of the wafer.
One natural way of fabricating the IGBT 10 of
The process of
Further, Aluminum (Al) doping in the range of 1019 to 1021 dopants per cm3 is desired for a low resistance ohmic contact to the P-type injector layer 12. Due to the limited thermal budget, in the state-of-the-art process, Al doping is performed using epitaxial growth (i.e., the P-type injector layer 12 is either Al doped or contains an Al doped sub-layer adjacent to the back-side of the wafer). However, heavy Al doping in this manner above 1019 dopants per cm3 increases a defect density during epitaxial growth. These defects propagate to the N− drift layer 14 as recombination centers. This leads to inferior carrier lifetime and degradation of the bipolar operation of the IGBT 10 when the IGBT 10 is forward biased.
Still further, in the state-of-the-art process, the collector contact 28 is formed on the back-side 30 of the P+ injector layer 12 by laser annealing in order to avoid high temperature processing after removing the N+ SiC substrate 36. The local temperature at the back-side of the wafer during laser annealing of the collector contact 28 can exceed 1300° C. This temperature is much greater than a known optimal temperature range for forming ohmic contacts to P-type SiC, which is 850-900° C.
More specifically, as illustrated in
Al doped regions 66 are formed at a back-side of the P+ injector layer 48. Notably, as compared to the IGBT 10 of
The Al doped regions 66 are aligned with the openings 42 and extend from within the P+ injector layer 48 to terminating ends 68 of the corresponding openings 42. The Al doped regions 66 are highly doped. In one preferred embodiment, a doping concentration of the Al doped regions 66 is greater than about 1019 dopants per cm3 and more preferably in a range of and including about 1019-1020 dopants per cm3, whereas a doping concentration of the P+ injector layer 48 can be less than 1019 dopants per cm3 or more preferably approximately 1018 dopants per cm3 (e.g., 5×1017 to 5×1018 dopants per cm3). Along with thermal annealing (e.g., Rapid Thermal Annealing) of the collector contact 44 in an optimal temperature range of 800-900° C., the Al doped regions 66 provide a good ohmic contact between the collector contact 44 and the P+ injector layer 48. Further, by providing the high Al doping concentration in the Al doped regions 66 via ion implantation rather than providing high Al doping via epitaxial growth as done in the IGBT 10, a low defect density in the P+ injector layer 48 is achieved. Note that while the Al doped regions 66 are doped with Al in this embodiment, other dopants may additionally or alternatively be used. Further, while the Al doped regions 66 are illustrated and described herein, as one alternative embodiment, the Al doped regions 66 may be replaced with a highly doped epitaxial layer between the N+ substrate 40 and the P+ injector layer 48.
In this example, the IGBT 38 also includes guard rings 70 formed around a periphery of an active area of the IGBT 38. The active area of the IGBT 38 is an area of the wafer in which current flows in the forward conduction state, which corresponds to the area of the wafer below the P+ wells 54. The guard rings 70 form an edge termination for the IGBT 38. In addition, a passivation and/or encapsulation material 72 is formed over the front-side of the wafer.
Next, the wafer is flipped and a mask 74 defining desired locations for the openings 42 through the N+ substrate 40 is formed on the back-side of the N+ substrate 40 as illustrated in
Next, the wafer is again flipped, and then front-side process is performed to form the P+ wells 54, the N+ emitter regions 56, the gate contacts 60 insulated by the insulating material 62, the emitter contact 64, and the passivation and/or encapsulating material 72, as illustrated in
Thus far, the discussion has focused on the IGBT 38. However, the concepts disclosed herein are applicable to other SiC semiconductor devices where a back-side contact is to be formed to a P-type layer. For instance, as discussed below, the concepts disclosed herein are applicable to other types of bipolar devices such as, for example, an N-channel GTO, an N-channel thyristor, and a PNP Bipolar Junction Transistor (BJT). In addition, the concepts disclosed herein are applicable to similar unipolar devices such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
In this regard,
More specifically, as illustrated in
Cathode contacts 98 are on, and preferably directly on, the N+ cathode regions 96 opposite the P-type base layer 94. Gate contacts 100 are on, and preferably directly on, the P-type base layer 94 between the N+ cathode regions 96. Again, the anode contact 84 is on the back-side 86 of the N+ substrate 80, which is also referred to herein as a back-side of the wafer, and within the openings 82 through the N+ substrate 80. The openings 82 extend from the back-side 86 of the N+ substrate 80 to, and potentially into, the P+ injector layer 88. As such, the anode contact 84 is in physical and electrical contact with the P+ injector layer 88 through the openings 82. The cathode contacts 98, the gate contacts 100, and the anode contact 84 are formed of any suitable metal(s) and/or metal alloy(s).
Al doped regions 102 are formed at a back-side of the P+ injector layer 88. Notably, as compared to the IGBT 10 of
The Al doped regions 102 are aligned with the openings 82 and extend from within the P+ injector layer 88 to terminating ends 104 of the corresponding openings 82. The Al doped regions 102 are highly doped. In one preferred embodiment, a doping concentration of the Al doped regions 102 is greater than about 1019 dopants per cm3 and more preferably in a range of and including about 1019-1020 dopants per cm3, whereas a doping concentration of the P+ injector layer 88 can be less than 1019 dopants per cm3 or more preferably approximately 1018 dopants per cm3 (e.g., 5×1017 to 5×1018 dopants per cm3). Along with thermal annealing (e.g., Rapid Thermal Annealing) of the anode contact 84 in an optimal temperature range of 800-900° C., the Al doped regions 102 provide a good ohmic contact between the anode contact 84 and the P+ injector layer 88. Further, by providing the high Al doping concentration in the Al doped regions 102 via ion implantation rather than providing high Al doping via epitaxial growth as done in the IGBT 10, a low defect density in the P+ injector layer 88 is achieved. Note that while the Al doped regions 102 are doped with Al in this embodiment, other dopants may additionally or alternatively be used. Further, while the Al doped regions 102 are illustrated and described herein, as one alternative embodiment, the Al doped regions 102 may be replaced with a highly doped epitaxial layer between the N+ substrate 80 and the P+ injector layer 88.
Note that, in another embodiment, the P+ injector layer 88 of the GTO 78 may be electrically transparent, and the GTO 78 may further include an additional N− epitaxial layer between the N+ substrate 80 and the P+ injector layer 88 as discussed above with respect to the embodiment of the IGBT 38 illustrated in
More specifically, as illustrated in
Emitter contacts 128 are on, and preferably directly on, the P+ emitter regions 124 opposite the N-type base layer 122. Base contacts 130 are on, and preferably directly on, the N-type base layer 122 between the P+ emitter regions 124. Again, the collector contact 112 is on the back-side 114 of the N+ substrate 108, which is also referred to herein as a back-side of the wafer, and within the openings 110 through the N+ substrate 108. The openings 110 extend from the back-side 114 of the N+ substrate 108 to, and potentially into, the P+ collector 116. As such, the collector contact 112 is in physical and electrical contact with the P+ collector 116 through the openings 110. The emitter contacts 128, the base contacts 130, and the collector contact 112 are formed of any suitable metal(s) and/or metal alloy(s).
Al doped regions 132 are formed at a back-side of the P+ collector 116. Notably, as compared to the IGBT 10 of
The Al doped regions 132 are aligned with the openings 110 and extend from within the P+ collector 116 to terminating ends 134 of the corresponding openings 110. The Al doped regions 132 are highly doped. In one preferred embodiment, a doping concentration of the Al doped regions 132 is greater than about 1019 dopants per cm3 and more preferably in a range of and including about 1019-1020 dopants per cm3, whereas a doping concentration of the P+ collector 116 can be less than 1019 dopants per cm3 or more preferably approximately 1018 dopants per cm3 (e.g., 5×1017 to 5×1018 dopants per cm3). Along with thermal annealing (e.g., Rapid Thermal Annealing) of the collector contact 112 in an optimal temperature range of 800-900° C., the Al doped regions 132 provide a good ohmic contact between the collector contact 112 and the P+ collector 116. Further, by providing the high Al doping concentration in the Al doped regions 132 via ion implantation rather than providing high Al doping via epitaxial growth as done in the IGBT 10, a low defect density in the P+ collector 116 is achieved. Note that while the Al doped regions 132 are doped with Al in this embodiment, other dopants may additionally or alternatively be used. Further, while the Al doped regions 132 are illustrated and described herein, as one alternative embodiment, the Al doped regions 132 may be replaced with a highly doped epitaxial layer between the N+ substrate 108 and the P+ collector 116.
Thus far, the semiconductor devices described have all been bipolar devices. However, the concepts disclosed herein are also applicable to unipolar devices. In this regard,
More specifically, as illustrated in
Gate contacts 162, which are insulated by insulating material 164, are on the front-side 154 of the P− drift layer 150 over regions of the P− drift layer 150 between the N-type wells 152. A source contact 166 is on, and preferably directly on, the P+, N+, and P+ regions 156, 158, and 160, which form corresponding source regions of the MOSFET 136. Again, the drain contact 142 is on the back-side 144 of the N+ substrate 138, which is also referred to herein as a back-side of the wafer, and within the openings 140 through the N+ substrate 138. The openings 140 extend from the back-side 144 of the N+ substrate 138 to, and potentially into, the P+ drain region 146. As such, the drain contact 142 is in physical and electrical contact with the P+ drain region 146 through the openings 140. The gate contacts 162, the source contact 166, and the drain contact 142 are formed of any suitable metal(s) and/or metal alloy(s).
Al doped regions 168 are formed at a back-side of the P+ drain region 146. Notably, as compared to the IGBT 10 of
The Al doped regions 168 are aligned with the openings 140 and extend from within the P+ drain region 146 to terminating ends 170 of the corresponding openings 140. The Al doped regions 168 are highly doped. In one preferred embodiment, a doping concentration of the Al doped regions 168 is greater than about 1019 dopants per cm3 and more preferably in a range of and including about 1019-1020 dopants per cm3, whereas a doping concentration of the P+ drain region 146 can be less than 1019 dopants per cm3 or more preferably approximately 1018 dopants per cm3 (e.g., 5×1017 to 5×1018 dopants per cm3). Along with thermal annealing (e.g., Rapid Thermal Annealing) of the drain contact 142 in an optimal temperature range of 800-900° C., the Al doped regions 168 provide a good ohmic contact between the drain contact 142 and the P+ drain region 146. Further, by providing the high Al doping concentration in the Al doped regions 168 via ion implantation rather than providing high Al doping via epitaxial growth as done in the IGBT 10, a low defect density in the P+ drain region 146 is achieved. Note that while the Al doped regions 168 are doped with Al in this embodiment, other dopants may additionally or alternatively be used. Further, while the Al doped regions 168 are illustrated and described herein, as one alternative embodiment, the Al doped regions 168 may be replaced with a highly doped epitaxial layer between the N+ substrate 138 and the P+ drain region 146.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
Cheng, Lin, Van Brunt, Edward Robert, Pala, Vipindas, Palmour, John Williams, Lichtenwalner, Daniel Jenner, Agarwal, Anant Kumar
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