A power converter controller includes an oscillator, a drive circuit, and a frequency modulator. The drive circuit receives a clock signal from the oscillator and generates a drive signal in response thereto to control switching of a switch of the power converter. The frequency modulator controls the frequency of the clock signal in response to an inductor voltage across an inductor of the energy transfer element to reduce a peak-to-peak ripple value in an output current of the power converter. The frequency modulator controls the frequency of the clock signal during each line half cycle to be a fixed frequency when the inductor voltage is less than or equal to a threshold voltage. When the inductor voltage is greater than the threshold voltage the frequency modulator varies the frequency to be less than the fixed frequency to adjust a shape of an input current of the power converter.
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1. A controller for use in an ac-to-dc power converter, the controller comprising:
an oscillator coupled to generate a clock signal having a frequency;
a drive circuit coupled to receive the clock signal and to generate a drive signal in response thereto, the drive signal to control switching of a switch to control a transfer of energy across an energy transfer element from an input of the power converter to an output of the power converter, wherein a switching frequency of the drive signal is based on the frequency of the clock signal and is much greater than a lower frequency of a time-varying inductor voltage across an inductor of the energy transfer element; and
a frequency modulator coupled to the oscillator to control the frequency of the clock signal during each line half cycle of the time-varying inductor voltage in response to a magnitude of the time-varying inductor voltage in order to reduce a peak-to-peak ripple value in an output current of the power converter that is due to the lower frequency time variations in the inductor voltage, wherein the frequency modulator controls the frequency of the clock signal during each line half cycle to be a fixed frequency when the magnitude of the inductor voltage is less than or equal to a threshold voltage, and wherein the frequency modulator varies the frequency of the clock signal during each line half cycle to be less than the fixed frequency to adjust a shape of an input current of the power converter when the magnitude of the inductor voltage is greater than the threshold voltage.
18. An ac-to-dc power converter, comprising:
an energy transfer element to be coupled between an input and an output of the power converter;
a switch coupled to an inductor of the energy transfer element; and
a controller coupled to the switch to control switching of the switch, wherein the controller includes:
an oscillator coupled to generate a clock signal having a frequency;
a drive circuit coupled to receive the clock signal and to generate a drive signal in response thereto, the drive signal to control switching of the switch to control a transfer of energy across the energy transfer element from the input of the power converter to the output of the power converter, wherein a switching frequency of the drive signal is based on the frequency of the clock signal and is much greater than a lower frequency of a time-varying inductor voltage across the inductor; and
a frequency modulator coupled to the oscillator to control the frequency of the clock signal during each line half cycle of the time-varying inductor voltage in response to a magnitude of the time-varying inductor voltage in order to reduce a peak-to-peak ripple value in an output current of the power converter that is due to the lower frequency time variations in the inductor voltage, wherein the frequency modulator controls the frequency of the clock signal during each line half cycle to be a fixed frequency when the magnitude of the inductor voltage is less than or equal to a threshold voltage, and wherein the frequency modulator varies the frequency of the clock signal during each line half cycle to be less than the fixed frequency to adjust a shape of an input current of the power converter when the magnitude of the inductor voltage is greater than the threshold voltage.
26. A device, comprising:
a light emitting diode (led) load; and
an ac-to-dc power converter having an output coupled to the led load, the power converter comprising:
an energy transfer element to be coupled between an input and the output of the power converter;
a switch coupled to an inductor of the energy transfer element; and
a controller coupled to the switch to control switching of the switch, wherein the controller includes:
an oscillator coupled to generate a clock signal having a frequency;
a drive circuit coupled to receive the clock signal and to generate a drive signal in response thereto, the drive signal to control switching of the switch to control a transfer of energy across the energy transfer element from the input of the power converter to the output of the power converter, wherein a switching frequency of the drive signal is based on the frequency of the clock signal and is much greater than a lower frequency of a time-varying inductor voltage across the inductor; and
a frequency modulator coupled to the oscillator to control the frequency of the clock signal in response to a magnitude of the time-varying inductor voltage in order to reduce a peak-to-peak ripple value in an output current of the power converter that is due to the lower frequency time variations in the inductor voltage, wherein, wherein the frequency modulator controls the frequency of the clock signal during each line half cycle to be a fixed frequency when the magnitude of the inductor voltage is less than or equal to a threshold voltage, and wherein the frequency modulator varies the frequency of the clock signal during each line half cycle to be less than the fixed frequency to adjust a shape of an input current of the power converter when the magnitude of the inductor voltage is greater than the threshold voltage.
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1. Field of the Disclosure
This disclosure relates to power supplies and, more particularly, to control circuits for power supplies.
2. Background
LED lighting has become popular in the industry due to the many advantages that this technology provides. For example, LED lamps typically have a longer lifespan, pose fewer hazards, and provide increased visual appeal when compared to other lighting technologies, such as compact fluorescent lamp (CFL) or incandescent lighting technologies. The advantages provided by LED lighting have resulted in LEDs being incorporated into a variety of lighting technologies, televisions, monitors, and other applications.
It is often desirable to implement LED lamps with a dimming functionality to provide variable light output. One known technology that has been used for analog LED dimming is the phase angle dimming either by leading edge or trailing edge control. In a known example, a Triac circuit can be used that operates by delaying the beginning of each half-cycle of alternating current (ac) power, which is known as “phase control.” By delaying the beginning of each half-cycle, the amount of power delivered to the load (e.g., the lamp) is reduced, producing a dimming effect in the light output by the lamp. In most applications, the delay in the beginning of each half-cycle is not noticeable to the human eye because the variations in the phase controlled line voltage and the variations in power delivered to the lamp occur so quickly. For example, Triac dimming circuits work especially well when used to dim incandescent light bulbs since the variations in phase angle with altered ac line voltages are immaterial to these types of bulbs. However, flicker may be noticed when Triac circuits are used for dimming LED lamps.
Flickering in LED lamps can occur because these devices are typically driven by LED drivers having regulated power supplies that provide regulated current and voltage to the LED lamps from ac power lines. Unless the regulated power supplies that drive the LED lamps are designed to recognize and respond to the voltage signals from Triac dimming circuits in a desirable way, the Triac dimming circuits are likely to produce non-ideal results, such as limited dimming range, flickering, shimmering, blinking, and/or color shifting in the LED lamps.
Some causes of these non-ideal results in using Triac dimming circuits with LED lamps are in part due to the characteristic of the Triac itself. For example, a Triac is a semiconductor component that behaves as a controlled ac switch. Thus, the Triac behaves as an open switch to an ac voltage until it receives a trigger signal at a control terminal, causing the switch to close. However, many Triac dimming circuits include an inherent imbalance in phase angle and conduction angles from cycle to cycle. These variances in phase angle and conduction angles in consecutive cycles can result in voltage amplitude variations at the input and also as output current variations (i.e., ripple) at the output of the power converter. The output current ripple may appear as light fluctuations and shimmering in an LED load.
Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals may refer to like parts throughout the various figures.
Corresponding reference characters may indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. Common but well-understood elements that are useful or necessary in commercially feasible embodiments are often not depicted in order to facilitate understanding of the various embodiments.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.
Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality.
The rectified phase controlled voltage 112, through the input circuitry block 120, provides a rectified input voltage Vin 130 at an input terminal of the switching regulator 140. The input circuitry block 120 in one example may include circuits and components/blocks such as input sense, inductive and capacitive filter, bleeder, damper and other required or optional interface circuits/components depending on the application. Power converter 100 may be an isolated or non-isolated converter with the same or shifted input/output reference grounds (e.g., reference grounds 101 and 191 may be either directly coupled or shifted relative to each other). Non-limiting examples of isolated converters include Flyback and forward converters, and non-limiting examples of non-isolated converters include Buck, Buck-boost and Tapped Buck converters. The high frequency switching of the switch element 141 of the switching regulator 140 is controlled by the controller 150 that, based on teaching of present application, includes a line ripple compensation block.
The rectified voltage 112, unaffected or substantially unaffected by the input circuitry 120, is applied to the input terminal 130 of the switching regulator 140 and also may be provided to the controller 150. In one example, controller 150 may be referenced to the input ground 101 (primary control). The regulated output of switching regulator 140, after passing through some output circuit block 160, may be applied across the bulk capacitor 168, which is then applied as an output voltage Vo 170 and an output current Io 171 to load 175 which in one example may be an array of LED lamps 178.
As shown in
Diagram 220 in
The phase-controlled rectified input voltage Vin 330 (e.g., waveform 315) is received from the bridge rectifier and input circuitry (e.g., 110 and 120 in
The switching regulator 340 includes an energy transfer element having inductors L1 342 and 343 (auxiliary winding), a diode 345, a switch 341 and a controller 350. Whenever switch 341 is closed energy (through passing current) will be transferred to the load which will charge the magnetic field of the inductor 342. When switch 341 opens the charged energy in the magnetic field of the inductor 342 resumes circulating the current through the load and diode 345.
Switch 341 is controlled by the drive signal from pin 351 of the controller 350 that includes the output ripple compensation feature to control the transfer of energy from input to output of the converter. Switch 341 and controller 350 in one embodiment could be included in a monolithic or hybrid integrated circuit (IC) structure 349 and in one example switch 341 is a MOSFET with drain terminal D, source terminal S and gate terminal G.
The switching regulator 340 in embodiment of
Controller 350 generates the drive signal on terminal 351 by processing the input signals on terminals: FB 353, BS 354, DS 355 and Vin 357 (from feedback circuit, bleeder circuit, damper circuit and from the input line sense).
The inductor L1 342 that is inserted on the low line of the switching regulator (on the path of return current from LED load) is the main energy transfer element. Auxiliary winding 343 may provide a rectified DC voltage 392 through rectifier diode 346, resistor 347 and capacitance 344 that is referenced to the input ground 301 and may provide supply voltage for the controller at BP pin 352 of the controller. As shown in
It is appreciated that in the example of
The output of the switching regulator 340 is coupled through a bulk output capacitor Co 368 to the LED load 378 to provide output voltage Vout 370 and regulated output current Io 371 to the LED array 378.
In CCM (Continuous Conduction Mode) operation of the switching regulator to force the input line current i(t) to follow the variation of the input sinusoidal voltage v(t) during each line cycle, one method is to control the duty cycle of the drive signal provided to the power switch (eg; a MOSFET). To control the duty cycle either on-time (ton) and/or switching frequency_of the drive signal could be changed.
In many applications, the DCM (Discontinuous Conduction mode) or critical mode operation of the switching regulator is more popular because of the low cost and simplicity of PFC control. In DCM operation the switching current pulses through the inductor fall to zero and all the magnetic energy in the inductor is discharged before the next switching cycle starts. In DCM operation of the PFC switching regulator the input line current Iin(t) is the average of current pulses through the inductor that is defined by the voltage across the inductor and thus the line current follows the line voltage.
The line ripple compensation block 420 may be used for LED drivers with DCM or critical mode PFC operation. In LED drivers with DCM or critical mode PFC operation the low frequency current ripple, specifically during phase controlled dimming, may modulate on the output current causing light shimmer. Without activation of the line ripple compensation block 420 the PFC switching regulator operates in DCM/Critical mode with fixed/constant on-time ton and fixed/constant switching frequency, Fsw(=1/Tsw) during the line sinusoidal variations of input line cycle.
When switch 450 is closed the current pulse through the inductor Lind ramps linearly from zero and during on-time of the switch (ton) rises to a peak value Ipulse(t) in response and proportional to the voltage across inductor Vind(t) at time t of the line sinusoidal variations: Vind(t)=Lind*Ipulse(t) ton. Voltage across the inductor Vind(t) depends on the topology of the switching regulators. For example, in a Buck switching regulator the inductor voltage definition is Vind(t)=Vin(t)−Vo, while in a Buck-boost or Flyback switching regulator the inductor voltage is defined as Vind(t)=Vin(t). In the above relations Vin(t) presents the input voltage sinusoidal variations and Vo is the output voltage.
Embodiments of the present disclosure include reducing the effect of low frequency output ripple and the light shimmering by substantially flattening the top portion of the input line rectified sinusoidal current above a reference level. This can be achieved by either controlling on-time ton or switching frequency Fsw as discussed in further detail below.
The average of inductor DCM current pulses defines the input current Iin(t) which is proportional to the inductor voltage Vind(t)
Ipulse(t)=Vind(t)*ton/Lind [EQ. 1]
Iin(t)=Ipulse(t)*ton/Tsw=Vind(t)*ton2*Fsw/Lind [EQ. 2]
Inductor value, Lind, has a predefined value and switch on-time ton in DCM operation may be kept constant during each line cycle. Considering that in any of Buck, Buckboost or Flyback topologies the inductor voltage during electro-magnetic charging may represent the input voltage (either Vind(t)=Vin(t) or Vind(t)=Vin(t)˜Vo) and considering the input current as average of DCM current pulses, it would be concluded that input current is proportionate to multiplication of inductor voltage and switching frequency Fsw (inverse of switching period Fsw=1/Tsw):
Iin(t)˜Vind(t)*Fsw(t) [EQ. 3]
As mentioned above, in an LED driver with PFC and phase control dimming when dimming level goes beyond a threshold (e.g., phase angle control of 130 or 150 degree) the line ripple current appearing at output may generate light shimmering effect. To reduce the low frequency current ripple effect at the output it is desired that in each half-line cycle of sinusoidal voltage variation above a predefined voltage level (i.e., a voltage threshold) the input line current to be kept constant (flattened). This predefined voltage level is referred as reference voltage or voltage threshold (in one example above 100V), wherein the switching frequency at or below reference voltage Vref is a fixed frequency referred as a reference frequency Fref
As observed in relation above, in an example where the on-time ton is kept constant, in each half-line cycle above the reference voltage Vref, the line current waveform Iin(t) can be kept constant/flattened by considering: Vind(t)*Fsw(t)=Vref*Fref; which means above the reference level the switching frequency Fsw(t) may be controlled as an inverse function of the line voltage sinusoidal variation, Fsw(t)=Fref*Vref/Vind(t) or Fsw(t)˜1/Vind(t).
The above relation with some mathematical manipulation can be rewritten as: Fsw(t)=Fref−Fref {[Vind(t)−Vref]/Vind(t)}; wherein the second term indicates a modifier term that, in response to increase of inductor voltage above the reference voltage, modifies and reduces the switching frequency to keep Iin(t) flat.
The line ripple compensation employed by line ripple compensation block 420 offers a compromise between the shimmer reduction and LED driver improved performance at deep dimming at one side and the PFC performance and harmonic distortion requirements at input of the switching regulator at the other side. The LED drivers utilizing the ripple compensation block introduced by block 420 may comply with the regulatory standards for power factor PF and total harmonic distortion THD. The line ripple compensation block 420 may be activated at a predefined low level of dimming where the PFC and THD performance is not of a main concern while the shimmer reduction and extending the dimming range is the main issue of the design. Even when the line ripple compensation block 420 is activated, transforming the input current to a flattened wave shape, the input current waveform still remains in-phase with the input sinusoidal voltage and power factor would not show a noticeable change (even though THD may have slightly changed). As will be discussed below, by selecting different options of the maximum/target value of the ripple compensation factor (RCF), either at 1 (flat input current waveform) or at a value above/below 1 (concave/convex input current waveform) any desired compromise between the input current PFC requirement and the output current ripple reduction (shimmer reduce and dimming range increase) may be achieved.
In one embodiment, all the signals required for the ripple compensation processing such as input line voltage Vin(t), reference voltage Vref, output voltage Vo, reference frequency Fref and switching frequency Fsw could be transferred to the current signals as presented for the internal control blocks of the
The controller IC 402 may include an external terminal Vin sense terminal 412 to be coupled through a resistor module 411 to the input voltage Vin 410 from input circuitry (Vin 130 in
The output sense signal through a resistor module 424 (equivalent to 366 in
The Vin Sense signal on terminal 412 is received through a first current mirror set of transistors 421 and 422 which transforms the voltage signal to a current signal 423 I[Vin] for processing in the controller. A second set of current mirror transistors 425 and 426 is coupled to terminal 414 Vo that provides a current signal I[Vo] 428 representative of the output voltage to block 430.
Block 430 receives the current signals 423 I[Vin] and 428 I[Vo] and outputs a current signal I[Vind] 431 representing the inductor voltage based on switching regulator topology: Buck switching regulator: I[Vind]=I[Vin]−I[Vo]; and Buck-boost or Flyback switching regulator: I[Vind]=I[Vin].
The first current mirror set of transistors (421 and 422) and the second current mirror set of transistors (425 and 426) are both referenced to the ground node 427 of the controller coupled to 450S terminal of the controller and coupled to the switching regulator ground 401.
The Frequency Modulation block 440 receives signal 431 representing inductor voltage, to be processed based on the voltage and frequency at reference level of the line sinusoidal variation, I[Vref] and I[Fref] respectively. To avoid any hard transient at enabling/disabling of the ripple compensation feature of the LED controller that may cause instability and misbehavior of LED driver, a weighting Ripple Compensation Factor (RCF) is defined that varies between 0 and a maximum target value RCFmax in gradual digital steps. In one example, the ripple compensation factor RCF changes between 0 and 1 in digital steps of 1/256. The RCF as a weighting factor multiplies in a frequency modification term that is applied in the Frequency Modulator block 440 as illustrated in
The weighting factor RCF increments or decrements digitally between 0 and a maximum/target value (eg; 1, >1 or <1) and smoothly transforms the sinusoidal input current waveform to a flat (or concave/convex) shape over multiple line cycles to compensate the ripple current at output.
The feedback sense signal on FB pin 419 couples to input 446 of the drive signal control loop block 445. The ripple compensation factor generator block 435 based on regulation status of the output received by signal 446 and through drive signal control loop block 445 defines signal 438 for incrementing/decrementing steps of RCF.
It is appreciated that enabling/disabling (i.e., activation/deactivation) signal 436 for RCF (ripple compensation factor) generator block 435 is based on the utilized circuitry in the LED driver. Signal 436 could be generated at any predetermined level of dimming (eg; 130 or 150 degree of phase angle control or even as soon as leading/trailing dimming edge is detected) and it is activated so that the compensation weighting factor RCF may change towards its maximum/target value RCFmax that could be 1 or some value below or above 1 based on desired application. Activation of RCF generator block 435 may be by different means/events such as but not limited to: A.) The FB (feedback) error voltage reference changing at a specific level of dimming. In one example when the error voltage reference level changes from 300 mV to 150 mV; B.) Edge detection at leading or trailing edge of phase angle control dimmer; or C.) Detection of the dimmer phase angle value going above/below some predetermined limit. In other examples any other event indicating the dimming level beyond a predetermined level may enable the ripple compensation feature.
The Frequency Modulation block 440 by receiving signal 431 representing inductor voltage I[Vind(t)] and signals I[Vref] and I[Fref] representing reference voltage Vref and reference frequency Fref, respectively (as current signals) and also by receiving signal RCF on terminal 434 calculates a modulated frequency to compensate the current variation. The modulated frequency calculation is based on the functions and logic shown in
The signal 441 I(Fsw) at output of the frequency modulation block 440 through the oscillator 442 may control the frequency of clock signal 444 and thus the switching frequency of the power switch 450 through the drive signal control loop block 445. The drive signal 448 through gate drive 449 applies to control terminal (in one example Gate 450G) of the power switch SW 450.
In each line cycle below the reference voltage Vref the frequency of the clock signal 444 and thus the switching frequency remain constant. Above the reference voltage Vref level for each switching cycle the frequency of the clock signal is calculated and controlled in response to reference voltage Vref, reference frequency Fref, the inductor voltage variation Vind(t) (that follows input voltage Vin(t) sinusoidal variations) and the RCF weighting factor as illustrated in relation of
I[Fsw]=I[Fref]−RCF*I[Fref]*(I[Vind(t)]−I[Vref])I[Vind(t)] [EQ. 4]
The RCF weighting factor in equation 4 guaranties that when ripple compensation feature is fully active (RCF=1) the switching frequency is modulated as below to keep the input current at a constant level (fully flattened):
I[Fsw]={I[Fref]*I[Vref]/I[Vind(t)]}[EQ. 5]
When ripple compensation feature is not activated (RCF=0) the switching frequency remains fixed on the same value of the reference frequency Fref: I[Fsw]=I[Fref]. Equation 4 and the effect of RCF provides an efficient control of switching frequency (Fsw) when the ripple compensation block 420 is activated to keep the line current constant (flat) above the reference voltage Vref level. As a second fold advantage RCF guaranties a smooth transition with no hard transient misbehavior during activation/deactivation of the ripple compensation block.
As long as the enabling signal 436 (
Accordingly,
It is appreciated that in each half-line cycle below the reference voltage level as mentioned above the inductor voltage signal is clamped on reference voltage Vref and the upper limit of the switching frequency would consequently be clamped on the reference frequency Fref. On the other hand the lower limit of switching frequency would be defined and clamped through the clamp block 485 on the minimum frequency of the oscillator block 442. This may happen during rising slope of line voltage sinusoidal variations when inductor voltage is also ramping up, switching frequency reduces and may hit the minimum frequency limit of the oscillator.
In the condition block 520 the main controller error is compared against a FB error threshold value. As long as the FB error is not below the threshold (option NO 522), which means regulation is not achieved, the loop goes back to point S 518, waiting and checking the condition until regulation is completed and FB error goes below (less than) the FB threshold. In condition block 520, when the drive signal control loop FB error has dropped below the threshold, then the loop continues to option Yes 525 and to the next conditional block 530 to confirm detection and activation of the line ripple compensation block feature (i.e., On/Off or Enable/Disable). The conditional block 530 detects if the Ripple Compensation block is already activated (option ON 532) or deactivated (option OFF 531). Activation of line ripple compensation feature could be by different means as explained in
If the line ripple compensation block is detected to be active/enabled (option ON 532), control loop continues to the conditional block 534 that compares the current (last updated) RCF to the maximum allowed RCF value (could be 1 or above/below 1) and checks if the current (last updated) RCF has not exceeded its maximum. If the RCF has hit the maximum allowed value (option NO 536) loop returns to loop start point S 518. However, as long as the RCF remains below the maximum RCF value (option “Yes” 538), the RCF would be one step incremented in block 540 before returning to the loop start point S 518.
On the other hand from conditional block 530 if the line ripple compensation block is not detected (or it is detected at OFF position disabled/deactivated, option OFF 531), then the conditional block 533 verifies if the RCF is reduced to (and is hitting) zero. If RCF is still higher enough than zero (RCF above zero, option Yes, 537), Then RCF is Decremented in block 545 before the RCF loop closes back for the next line cycle that starts over from loop start point S 518. However, if after RCF conditional block 533, it is detected that RCF has declined towards/below zero (RCF is hitting the zero, option NO 535) the process starts over from loop start point S 518. In one embodiment, the process of
It is appreciated that I[Vind(t)] follows the applied clamp for input sinusoidal voltage variations below the reference voltage level I[Vref]. The inductor voltage signal I[Vind(t)] 568 resulted from block 565 as well as the other updated signals I[Vo], I[Vref], I[Fref] and RCF are used in calculation block 570 based on the ripple compensation functions discussed above in
The upper limit of I[Fsw(t)] 572 is defined and clamped by I[Fref] and the lower limit of I[Fsw(t)] 572 would be defined and clamped by the predefined minimum switching frequency (oscillator minimum frequency Fsw(min)) as shown in conditional block 574. The conditional block 574 compares the calculated signal I[Fsw(t)] 572, from the algorithm in block 565 and clamped at upper limit in block 570, to the predefined minimum switching frequency I[Fsw(min)] of the oscillator block 442. If in some conditions (e.g., at high line voltage and low dimming) the switching frequency I[Fsw(t)] tends to go below the I[Fsw(min)] (option “Yes” 575), it would be clamped (block 577) at the predefined minimum oscillator frequency, I[Fsw(t)]=I[Fsw(min)]. Otherwise (option “No” 576), when in block 580, I[Fref]>I[Fsw(t)]>I[Fsw(min)] the controlled/modulated switching frequency is in desired range, signal I[Fsw(t)] commands the switching frequency Fsw(t) through block 585 to run the power switch (through gate drive block 449 in
Graph 620 in
Graph 640 in
The reduced peak to peak value of the output ripple current waveform 666 with the line ripple compensation control block activation in comparison to the output ripple current waveform 664 without the line ripple compensation control block activation shows the peak to peak ripple reduction that reduces the effect of output light shimmer (may eliminate the visible effect of light shimmering for human eyes).
The above description of illustrated examples of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to be limiting to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present disclosure.
Vaughan, Peter, Pregitzer, Ricardo Luis Janezic, Mao, Mingming, Pastore, Tiziano, Zhang, Michael Yue
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