Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.
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9. An apparatus, comprising:
a dynamic random access memory (dram) module with at least one selectably adjustable reference voltage generator using a digital-to-analog converter (DAC), wherein the at least one selectably adjustable reference voltage generator includes the DAC to generate a selected voltage reference level from an input command word, and wherein the at least one selectably adjustable reference voltage generator is to dynamically adjust the dynamically adjustable reference voltage in view of a timing budget to control a buffer power level.
1. A computing system, comprising:
a processor; and
a dynamic random access memory (dram) coupled to the processor, the dram to determine logic state of received digital data based on a dynamically adjustable reference voltage, wherein a controller is operable to set, via software, the dynamically adjustable reference voltage to one of a plurality of different reference voltage options, wherein the controller is a hardware,
wherein the controller is to dynamically adjust the dynamically adjustable reference voltage in view of a timing budget to control a buffer power level.
12. Machine readable media having instructions stored thereon, that when executed, cause one or more machines to perform an operation, the operation comprising:
testing two or more different reference voltage levels for a dynamic random access memory (dram);
evaluating one or more parameters associated with the dram for the tested two or more different reference voltage levels; and
selecting one of the tested two or more different reference voltage levels based on the evaluated one or more parameters, wherein the two or more different reference voltage levels are generated by a circuit inside the dram.
2. The computing system of
3. The computing system of
5. The computing system of
6. The computing system of
7. The computing system of
8. The computing system of
11. The apparatus of
13. The machine readable media of
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The present application is a Continuation of, and claims priority to and incorporates by reference, the corresponding U.S. patent application Ser. No. 12/638,887 filed Dec. 15, 2009, and entitled “METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM,” and issued as U.S. Pat. No. 8,582,374 on Nov. 12, 2013.
Embodiments of the invention relate generally to the field of voltage reference control for input/output (I/O) circuits and more particularly to methods and apparatus for dynamically controlling voltage reference for a Dual In-line Memory Module (DIMM) of a Dynamic Random Access Memory (DRAM).
As input/output (I/O) buffers become more complicated in design, optimizing and/or debugging the I/O systems for high volume manufacturing (HVM) becomes challenging. One possible reason for such challenge is that processors having modern I/O buffers are optimized to perform at a specific power consumption envelope for a fixed I/O voltage reference level. The voltage reference for the I/O system is used in the sense amplifiers of the receivers of the I/O buffers to determine the value of the incoming data. Generally, such voltage reference is set to a level which is a fraction of the I/O power supply, for example, ½ VCC or ⅔ VCC. Optimization of the I/O systems is then performed at those fixed I/O voltage reference levels. Optimization means setting the properties of the I/O buffers so that the I/O buffers operate in a particular power envelope, drive the I/O signals at a specific speed, maintain a certain timing margin for the I/O signals, operate within certain noise levels (crosstalk, overshoot, undershoot, ground bounce, ring back), etc.
However, improved and accurate optimization of an I/O buffer depends on the system in which the I/O buffer operates. This means that for every different type of I/O system, a different voltage reference level may be selected as its fixed voltage reference to achieve the optimized performance metrics of the I/O system. Such a customized fixed voltage reference increases the cost of HVM because it is expensive to change the fixed voltage reference to a new level for every different I/O system. Furthermore, the presence of the voltage reference generator off die on the motherboard requires special external cards to interface with the motherboard to override the fixed voltage reference level to a new level for I/O system optimization. Such external cards also increase the cost of HVM.
For example, a double data rate (DDR) interface of a Dynamic Random Access Memory (DRAM) operates with a fixed reference voltage for the DDR's Dual In-Line Memory Module (DIMM). Generally, the fixed reference voltage is set to ½ VCC level. Such fixed reference voltage is used by the DRAM to decide if the received data in its memory is a logical one or zero. Statically setting this voltage reference limits the ability to achieve the optimal DRAM operation point for a given I/O system. Such a fixed voltage reference also limits the ability to test DRAMs at HVM because external interface cards on the motherboards are needed to override fixed voltage reference levels for the DRAM sense amplifiers and to determine I/O system margins for various voltage reference levels.
Embodiments of the invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.
Embodiments of the invention discuss a method and apparatus of dynamic voltage reference control for a Dual In-Line Memory Module (DIMM) in double data rate (DDR) interface system. Such a dynamic voltage reference generator allows for improved optimization of the DDR system during boot time for power consumption, timing margins, voltage margins, I/O parameters such as I/O driver drive strength, termination impedance, etc.
Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic “may,” “might,” or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
In one embodiment, the voltage reference (Vref) generator 101 of the dynamic reference generator 100a is implemented as a digital to analog converter (DAC) having a resistor ladder stack configured for selecting a specific value of the Vref via the select signal. The output of the Vref generator 101 is buffered via an analog buffer 102 and sent to input/output (I/O) buffers. In one embodiment, the analog buffer 102 comprises a voltage follower implemented as a unit gain operational amplifier (OPAMP). In one embodiment, the output impedance of the DAC 101 is higher than the embodiment in which the OPAMP 102 is removed. The high output impedance of the DAC 101 allows for a smaller DAC size die area and thus lower power dissipation as compared to the DAC 101 with low output impedance in the embodiment without the OPAMP 102.
In one embodiment, the select signal to the DAC 101 of
The initial function of the BIOS is to identify, test, and initialize system devices such as the video display card, hard disk, memory, and other hardware such as Dynamic Random Access Memory (DRAM). In one embodiment, the Vref level in the DIMM of the DRAM is dynamically adjusted via the memory reference code (MRC) in the BIOS. In one embodiment, the selection of the Vref via the select signal occurs at boot time of the I/O system. In other embodiments, Vref is selected during normal operation of the I/O system (e.g., outside the boot time of the I/O system). The term dynamic means that the Vref level is adjustable at any time (as opposed to static Vref level) via off-chip or on-chip hardware and/or software.
At block 202, a worst case voltage level of Vref is determined. In one embodiment, the worst case voltage reference level of Vref is the level at which the I/O begins to see errors. In one embodiment, the worst case voltage reference level of Vref occurs when a single type of I/O failing condition occurs. Examples of a single type of I/O failing condition include incorrect sampling by a receiver of an I/O of transmitted data by an I/O, exceeding a predetermined allowable bit error rate (errors per second), etc. In one embodiment, the worst case voltage reference level of Vref occurs when multiple types of I/O failing conditions occur. Examples of a multiple types of I/O failing conditions include exceeding a predetermined allowable bit error rate (errors per second), exceeding a predetermined power consumption envelope, etc.
At block 203, the voltage level of the Vref is adjusted by the dynamic voltage reference control unit based on the worst case voltage level of Vref. At block 204, the dynamically adjusted Vref is then used to compute the center of an asymmetrical eye of the I/O system. In one embodiment, the computed center is then used for adjusting the position of a strobe signal (sampling signal) to maximize performance metrics such as timing margin, I/O driver strengths, etc.
In one embodiment, to compute the center of the eye (which is not necessarily the middle of the eye), maximum height of the eye and the width of the eye is measured at the dynamically adjusted Vref (based on the worst case Vref level). The eye of an I/O system is generally asymmetrical in form. Asymmetrical form means that the eye is not exactly oval in shape, but some form of polygon.
As a result of the eye's asymmetrical form, the center of the eye which traditionally results in maximum timing margin in the middle of the eye at nominal Vref settings (e.g., the initially set Vref leval at VCC/2) is no longer the ideal center of the eye for maximizing timing margin as a function of Vref levels. In other words, the dynamically adjustable Vref level when used to determine the center of the asymmetrical eye for maximizing timing margin of the I/O system may be significantly different from the center of the asymmetrical eye for maximizing timing margin when Vref level is fixed at its initially set value (e.g., VCC/2).
The position of the strobe signal (sampling signal) is adjusted using multi-dimensional view of the asymmetrical eye which has height and width components. In one embodiment, the height of the eye represents a performance metric (e.g., a timing margin) of the I/O system for minimum and maximum levels of Vref while the width of the eye represents various minimum and maximum levels of the performance metric at a given Vref level. In one embodiment, the center of the asymmetrical eye is computed as the sum of the maximum height and width of the eye and then by dividing that sum by two.
In one embodiment, the left edge 405a of the asymmetrical eye represents the minimum timing margin associated with one or more Vref levels. In one embodiment, the right edge 405b of the asymmetrical eye represents the minimum timing margin associated with one or more Vref levels. In one embodiment, the center of the asymmetrical eye is computed as the sum of timing margins corresponding to the left and the right edges and then dividing the sum by 2.
At block 301, the dynamic voltage reference control unit (e.g., 100 of
At block 302, the process of equalization takes place. The process involves raising a level of the voltage reference via the dynamic reference control unit to determine a failing point of the I/O system. A failing point is identified once the I/O system stops operating correctly and begins to receive incorrect data. At the failing point, the Vref level is recorded. The performance metric is also determined at the failing point. In one embodiment, the performance metric is a timing margin of the I/O system.
The voltage reference Vref is then lowered, via the dynamic reference control unit, from the initial value of Vref till the I/O system fails again. In one embodiment, Vref level is adjusted by the BIOS. In another embodiment, the Vref level is adjusted by a compensation circuit having a feedback loop configured to adjust the Vref level in responses to an event. Examples of an event include change in operational temperature, change in system noise level, or any other internal/external event having an impact on the performance of the I/O system.
The voltage reference Vref is recorded at the failing point described above. The performance metric is also recorded at this new failing point. Based on the raised Vref level and the lowered Vref level, which generated failing points of the I/O system, a new Vref level is computed. In one embodiment, the new Vref level is an average of the raised and lowered Vref levels at the failing points. In other embodiments, a skewed average of the raised and lowered Vref levels at the failing points is used to compute a new Vref level. In yet other embodiments, other formulae are used to compute the new Vref level.
At block 303, the new Vref level determined via the equalization process is used to compute a center of an asymmetrical eye. This center is used to re-adjust the position of the sampling strobe signal to achieve the optimized level of I/O system performance based on the performance metric.
As mentioned in the background section, I/O systems are optimized at a fixed Vref level, which is generally set at ½ VCC. The eye diagram of such an I/O system is a single dimensional (1D) eye diagram based on that fixed voltage reference Vref level. Indicators 404a and 404b correspond to a performance metric of the I/O system. In this example, indicators 404a and 404b represent timing margins of +/−15 ps at a fixed Vref level of “+00” (e.g., ½ VCC). Each tick on the x-axis, for the above example, represents 1/64 of a unit interval (UI). A UI is defined as how fast data is sent out on an I/O bus of an I/O system, for example for a 1333 MT (mega-transfer) I/O data frequency, the UI is 750 ps. Based on this example, a tick on the x-axis is 750/64=12 ps. Therefore, the timing margin of +/−15 ps at a fixed Vref level of “+00” is 12×15=180 ps for a 1333 MT I/O system.
In one embodiment, the 2D eye diagram, as the one shown in
In one embodiment, to achieve a certain power dissipation level of the I/O system, Vref is adjusted dynamically via the BIOS in view of the timing margin budget (as seen in the 2D eye diagram of
If a system administrator, for example, wants to lower the power dissipation of the I/O system at the cost of timing margin for the I/O system, the administrator can dynamically adjust the Vref level to achieve a new timing margin and re-center the strobe signal for proper I/O operation. As mentioned above, strobe signal is a sampling signal to sample data. Generally, the strobe signal is set at the center of a data signal to maximize the timing margins associated with the data signal. The position of the strobe signal can be re-adjusted in view of a dynamically adjusted Vref signal to optimize the I/O system.
One reason for dynamically adjusting the voltage reference Vref level to optimize an I/O system, as opposed to other parameters, is because many I/O system performance parameters, such as crosstalk, inter-symbol interference (ISI), etc., are more easily comprehended in voltage domain than any other domain. Without knowing the operational boundaries of the system in view of how high or low Vref level may be set and still have an operational I/O system, further optimization of the I/O system becomes difficult. Optimizing the I/O system on the basis of timing margin alone (at a fixed Vref level) results in incorrect information regarding the true operational boundaries of the I/O system.
For example, if a vendor of a DDR4 experiences a failing DRAM 504 because it does not store or read data correctly, Vref level in the DIMM 501 can be dynamically adjusted via the BIOS 503a to vary the timing margin or other parameters of an I/O buffer and so place the system in operational condition. In one embodiment, the sampling signal (the strobe signal) is re-calibrated to a new center in view of the new dynamically adjusted Vref level.
In one embodiment, the dynamic voltage reference control unit (of
In one embodiment, the dynamic voltage reference control unit is located on die. In another embodiment, the dynamic voltage reference control unit is located off-chip on the motherboard.
In one embodiment, by dynamically adjusting Vref (thus the eye height) optimum drive strength is achieved at point 604. The optimum drive strength point 604 suggests that a weaker (thus smaller) I/O driver (buffer) is needed to achieve the desirable drive strength in the I/O system—weaker compared to the drive strength at the default point 603. A weaker driver will consume less power than a stronger driver. Therefore, the new optimized drive strength point also achieves better power performance of the I/O system. Such optimum drive strength is not easily identifiable with a fixed static voltage reference Vref. Such fixed Vref level would have resulted in non-optimum drive strength setting at 603. Therefore, dynamically adjusting the Vref level via a 2D eye diagram of the I/O allows for optimizing the I/O system in a faster manner which is visibly easier to comprehend.
Elements of embodiments are also provided as a machine-readable medium for storing the computer-executable instructions (e.g., BIOS for controlling the voltage reference level Vref). The machine-readable medium may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or other type of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the invention may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
In one embodiment, the BIOS sweeps Vref levels by accessing the dynamic voltage reference control unit and executing test patterns on the I/O system for each Vref level and determining an optimized Vref level for the I/O system. Such embodiment allows for dynamically adjusting DIMM Vref levels at boot time and determining an optimized Vref level for the DRAM. As mentioned above, optimization means determining a Vref level that provides targeted power dissipation level for a given I/O system frequency goals.
While the invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations will be apparent to those of ordinary skill in the art in light of the foregoing description.
For example, the resistor ladder in
The methods of optimizing timing margin by re-centering the strobe signal (as illustrated by
Embodiments of the invention are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.
Moore, Kevin B., Lovelace, John V., Mozak, Christopher P., Spry, Bryan L., Schoenborn, Theodore Z., Yunker, Christopher E.
| Patent | Priority | Assignee | Title |
| 10027338, | Jun 10 2016 | Analog Devices International Unlimited Company | Buffer, and digital to analog converter in combination with a buffer |
| 10347319, | Dec 15 2009 | TAHOE RESEARCH, LTD | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system |
| 10431262, | Nov 13 2017 | SILICON MOTION INC. | Method for controlling operations of memory device, associated memory device and controller thereof, and associated electronic device |
| 10510379, | Nov 13 2017 | Silicon Motion, Inc. | Method for controlling operations of memory device, associated memory device and controller thereof, and associated electronic device |
| 10998012, | Apr 19 2019 | Samsung Electronics Co., Ltd. | Semiconductor memory modules including power management integrated circuits |
| 11983410, | Feb 25 2021 | Samsung Electronics Co., Ltd. | Method optimizing DQ calibration pattern for memory device and computing system performing same |
| 9948315, | Jun 10 2016 | Analog Devices International Unlimited Company | Digital to analog converter including logical assistance |
| Patent | Priority | Assignee | Title |
| 5243625, | Jul 16 1990 | U.S. Philips Corporation | Receiver for multivalued digital signals |
| 5864225, | Jun 04 1997 | Fairchild Semiconductor Corporation | Dual adjustable voltage regulators |
| 5982161, | Oct 14 1998 | Intel Corporation | Voltage regulator having variable frequency-based control |
| 6052307, | Aug 11 1998 | Texas Instruments Incorporated | Leakage tolerant sense amplifier |
| 6069471, | May 14 1998 | Intel Corporation | Dynamic set point switching regulator |
| 6094734, | Aug 22 1997 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Test arrangement for memory devices using a dynamic row for creating test data |
| 6104651, | Nov 04 1997 | Round Rock Research, LLC | Testing parameters of an electronic device |
| 6140860, | Dec 31 1997 | Intel Corporation | Thermal sensing circuit |
| 6353403, | Apr 06 2000 | Unwired Planet, LLC | Fast ramping of control voltage with enhanced resolution |
| 6425086, | Apr 30 1999 | Intel Corp | Method and apparatus for dynamic power control of a low power processor |
| 6489912, | Apr 10 2001 | International Business Machines Corporation | Analog-to-digital converter for monitoring VDDQ and dynamically updating programmable Vref when using high-frequency receiver and driver circuits for commercial memory |
| 6499131, | Jul 15 1999 | Texas Instruments Incorporated | Method for verification of crosstalk noise in a CMOS design |
| 6510503, | Jul 27 1998 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | High bandwidth memory interface |
| 6515917, | Apr 10 2001 | International Business Machines Corporation | DIGITAL-TO-ANALOG CONVERTER (DAC) FOR DYNAMIC ADJUSTMENT OF OFF-CHIP DRIVER PULL-UP AND PULL DOWN IMPEDANCE BY PROVIDING A VARIABLE REFERENCE VOLTAGE TO HIGH FREQUENCY RECEIVER AND DRIVER CIRCUITS FOR COMMERCIAL MEMORY |
| 6614674, | Aug 27 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Regulator circuit for independent adjustment of pumps in multiple modes of operation |
| 6667769, | Dec 10 2001 | Google Technology Holdings LLC | Time integrating pixel sensor |
| 6680642, | May 23 2002 | Innersea Technology | Analog bipolar current source |
| 6728133, | Jul 09 2001 | Renesas Electronics Corporation | Nonvolatile semiconductor memory device |
| 6906531, | Oct 11 2002 | Dell Products L.P.; Dell Products L P | Adaptive reference voltage method and system |
| 6940303, | Nov 29 2002 | SIGMATEL, LLC | System and method to establish an adjustable on-chip impedance |
| 6947348, | Jul 15 2003 | International Business Machines Corporation | Gain cell memory having read cycle interlock |
| 6969976, | Nov 07 2003 | National Semiconductor Corporation | Dynamic current limit adjustments |
| 7036053, | Dec 19 2002 | Intel Corporation | Two dimensional data eye centering for source synchronous data transfers |
| 7057397, | Mar 03 2005 | Lattice Semiconductor Corporation | Output impedance measurement techniques |
| 7068206, | Jul 31 2002 | Quantum Semiconductor LLC | Asynchronous serial analog-to-digital converter methodology having dynamic adjustment of the bandwidth |
| 7162376, | Dec 23 2004 | Rambus Inc. | Circuits, systems and methods for dynamic reference voltage calibration |
| 7170707, | Nov 09 2004 | Western Digital Technologies, INC | Systems and methods for reducing power dissipation in a disk drive including an adjustable output voltage regulator |
| 7194559, | Aug 29 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Slave I/O driver calibration using error-nulling master reference |
| 7200027, | Dec 29 2004 | Texas Instruments Incorporated | Ferroelectric memory reference generator systems using staging capacitors |
| 7214910, | Jul 06 2004 | International Business Machines Corporation | On-chip power supply regulator and temperature control system |
| 7230449, | Feb 11 2005 | International Business Machines Corporation | Data receiver with a programmable reference voltage to optimize timing jitter |
| 7248640, | Aug 17 2001 | Synopsys, Inc | System and method for providing slicer level adaption |
| 7299380, | Jan 27 2004 | Hewlett Packard Enterprise Development LP | Testing a receiver connected to a reference voltage signal |
| 7362622, | Apr 13 2004 | Polaris Innovations Limited | System for determining a reference level and evaluating a signal on the basis of the reference level |
| 7386410, | Sep 27 2005 | ATI Technologies ULC | Closed loop controlled reference voltage calibration circuit and method |
| 7417459, | Apr 06 2005 | Intel Corporation | On-die offset reference circuit block |
| 7489121, | Nov 16 2005 | INTERSIL AMERICAS LLC | Compensation offset adjustment scheme for fast reference voltage transitioning |
| 7499308, | Mar 21 2007 | CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD | Programmable heavy-ion sensing device for accelerated DRAM soft error detection |
| 7541795, | Feb 09 2006 | National Semiconductor Corporation | Apparatus and method for start-up and over-current protection for a regulator |
| 7561465, | Dec 28 2006 | GLOBALFOUNDRIES U S INC | Methods and systems for recovering data in a nonvolatile memory array |
| 7613045, | Nov 26 2007 | Western Digital Israel Ltd | Operation sequence and commands for measuring threshold voltage distribution in memory |
| 7720141, | Sep 05 2006 | Advanced Micro Devices, INC | Decision feedback restore of DC signals in a receiver |
| 7729168, | Jun 28 2007 | TAHOE RESEARCH, LTD | Reduced signal level support for memory devices |
| 7759958, | Sep 21 2007 | LENOVO INTERNATIONAL LIMITED | Apparatus, system, and method for integrated component testing |
| 7791966, | Nov 26 2007 | NEC Corporation | Apparatus, memory device and method of improving redundancy |
| 7817714, | Jan 23 2006 | Postech Foundation and Postech Academy Industry Foundation | Integrating receiver having adaptive feedback equalizer function to simultaneously remove inter-symbol interference and high frequency noises and system having the same |
| 7826279, | Apr 10 2008 | Advanced Micro Devices, Inc. | Programmable bias circuit architecture for a digital data/clock receiver |
| 7853842, | Jun 08 2007 | Hynix Semiconductor Inc. | Semiconductor memory device with ZQ calibration |
| 7859938, | May 22 2006 | LONGITUDE SEMICONDUCTOR S A R L | Semiconductor memory device and test method thereof |
| 7872494, | Jun 12 2009 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Memory controller calibration |
| 7924628, | Nov 14 2007 | MORGAN STANLEY SENIOR FUNDING | Operation of a non-volatile memory array |
| 7974141, | Jan 29 2009 | International Business Machines Corporation | Setting memory device VREF in a memory controller and memory device interface in a communication bus |
| 7990768, | Jan 29 2009 | International Business Machines Corporation | Setting memory controller driver to memory device termination value in a communication bus |
| 7991098, | Oct 31 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for training the reference voltage level and data sample timing in a receiver |
| 8068357, | Sep 05 2007 | Rambus Inc. | Memory controller with multi-modal reference pad |
| 8073648, | May 14 2007 | Western Digital Israel Ltd | Measuring threshold voltage distribution in memory using an aggregate characteristic |
| 8089813, | Jul 18 2008 | International Business Machines Corporation | Controllable voltage reference driver for a memory system |
| 8253396, | Jun 10 2008 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Voltage regulator system |
| 8289784, | Jun 15 2010 | International Business Machines Corporation | Setting a reference voltage in a memory controller trained to a memory device |
| 8314515, | Apr 24 2009 | SHANGHAI DARESOAR DYNAMICS TECHNOLOGY CO , LTD | System corrected programmable integrated circuit |
| 8331176, | Nov 30 2009 | Intel Corporation | Method and system for evaluating effects of signal phase difference on a memory system |
| 8370719, | May 21 2010 | SK HYNIX NAND PRODUCT SOLUTIONS CORP | Persistent moving read reference |
| 8456928, | May 24 2010 | LENOVO INTERNATIONAL LIMITED | Dynamic adjustment of reference voltage in a computer memory system |
| 8582374, | Dec 15 2009 | TAHOE RESEARCH, LTD | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system |
| 8630317, | Oct 19 1999 | Rambus Inc. | Memory system with calibrated data communication |
| 8654573, | Jul 27 1998 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | High bandwidth memory interface |
| 8878592, | Apr 27 2012 | Rambus Inc. | Simultaneous switching noise cancellation by adjusting reference voltage and sampling clock phase |
| 8946610, | Jun 02 2005 | SONY GROUP CORPORATION | Semiconductor image sensor module and method of manufacturing the same |
| 8949520, | Jan 22 2009 | Rambus Inc. | Maintenance operations in a DRAM |
| 20020078615, | |||
| 20040123207, | |||
| 20050259774, | |||
| 20060142977, | |||
| 20080022288, | |||
| 20090080266, | |||
| 20090228739, | |||
| 20090292971, | |||
| 20100001703, |
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