Methods, systems, and computer readable media for providing bios data and non-bios data on the same non-volatile memory. According to one aspect, a system for providing bios data and non-bios data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including bios data and non-bios data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before bios is accessed.
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1. A system for providing basic input/output system (bios) data and non-bios data on the same non-volatile memory, the system comprising:
a controller for controlling access by a host to a non-volatile memory for storing data, the data including bios data and non-bios data, the controller comprising:
a first bus interface for communicating data to and from the host via a first bus of a first bus protocol;
a second bus interface for communicating data to and from the host via a second bus of a second bus protocol; and
a third interface for communicating data to and from the non-volatile memory,
wherein the first bus comprises a bus that is operable after power-on reset and before bios is accessed.
24. A system for providing basic input/output system (bios) data and non-bios data on the same non-volatile memory, the system comprising:
a non-volatile memory for storing data, the data including bios data and non-bios data; and
a controller for controlling access by a host to the non-volatile memory, wherein the controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory, wherein the first bus comprises a bus that is operable after power-on reset and before bios is accessed.
30. A method for providing basic input/output system (bios) data and non-bios data on the same non-volatile memory, the method comprising:
at a controller for controlling access by a host to a non-volatile memory for storing data, the data including bios data and non-bios data, the controller having a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory:
performing a power-on reset;
providing access to bios data via the first bus interface;
using at least some of the bios data to render operable the second bus interface; and
providing access to non-bios data via the second bus interface.
32. A non-transitory computer readable medium having stored thereon executable instructions that when executed by a processor of a computer control the computer to perform steps comprising:
at a controller for controlling access by a host to a non-volatile memory for storing data, the data including bios data and non-bios data, the controller having a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory:
performing a power-on reset;
providing access to bios data via the first bus interface;
using at least some of the bios data to render operable the second bus interface; and
providing access to non-bios data via the second bus interface.
31. A method for providing a capability to reset a bus interface that lacks a dedicated reset signal, the method comprising:
at a bus controller having a first bus interface for communicating data to and from a host via a first bus of a first bus protocol, the first bus interface having a reset signal input for receiving a reset request for resetting the first interface without resetting the controller, and a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, the second bus interface lacking a reset signal input for receiving a reset request for resetting the second interface without resetting the controller:
detecting a reset request on the reset signal input of the first bus interface; and
in response to detecting the reset request, resetting at least one of the first bus interface and the second bus interface without resetting portions of the controller other than the at least one of the first bus interface and the second bus interface.
14. A system for providing a capability to reset a bus interface that lacks a dedicated reset signal, the system comprising:
a bus controller comprising:
a first bus interface for communicating data to and from a host via a first bus of a first bus protocol, the first bus interface having a reset signal input for receiving a reset request for resetting the first interface without resetting the controller; and
a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, the second bus interface lacking a reset signal input for receiving a reset request for resetting the second interface without resetting the controller,
wherein the controller is configured to detect a reset request on the reset signal input of the first bus interface, and, in response to detecting the reset request, reset at least one of the first bus interface and the second bus interface without resetting portions of the controller other than the at least one of the first bus interface and the second bus interface.
33. A non-transitory computer readable medium having stored thereon executable instructions that when executed by a processor of a computer control the computer to perform steps comprising:
at a bus controller having a first bus interface for communicating data to and from a host via a first bus of a first bus protocol, the first bus interface having a reset signal input for receiving a reset request for resetting the first interface without resetting the controller, and a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, the second bus interface lacking a reset signal input for receiving a reset request for resetting the second interface without resetting the controller:
detecting a reset request on the reset signal input of the first bus interface; and
in response to detecting the reset request, resetting at least one of the first bus interface and the second bus interface without resetting portions of the controller other than the at least one of the first bus interface and the second bus interface.
28. A system for providing basic input/output system (bios) data and non-bios data on the same non-volatile memory, the system comprising:
a non-volatile memory for storing data, the data including bios data and non-bios data; and
a bus controller for controlling access by a host to the non-volatile memory, wherein the controller includes:
a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, the first bus interface having a reset signal input for receiving a reset request for resetting the first interface without resetting the controller;
a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, the second bus interface lacking a reset signal input for receiving a reset request for resetting the second interface without resetting the controller; and
a third interface for communicating data to and from the non-volatile memory,
wherein the controller is configured to detect a reset request on the reset signal input of the first bus interface, and, in response to detecting the reset request, reset at least one of the first bus interface and the second bus interface without resetting portions of the controller other than the at least one of the first bus interface and the second bus interface.
2. The system of
3. The system of
4. The system of
5. The system of
6. The system of
a low pin count (LPC) bus interface; and
a serial peripheral interface (SPI) bus interface.
7. The system of
a serial advanced technology attachment (SATA) bus interface;
a peripheral component interconnect (PCI) bus interface;
a peripheral component interconnect express (PCIe) bus interface;
a peripheral component interconnect extended (PCI-X) bus interface; and
an integrated drive electronics (IDE) bus interface.
9. The system of
10. The system of
11. The system of
12. The system of
15. The system of
16. The system of
a low pin count (LPC) bus interface;
a peripheral component interconnect (PCI) bus interface;
a peripheral component interconnect extended (PCI-X) bus interface; and
an integrated drive electronics (IDE) bus interface.
17. The system of
a serial advanced technology attachment (SATA) bus interface; and
a peripheral component interconnect express (PCIe) bus interface.
18. The system of
19. The system of
21. The system of
27. The system of
29. The system of
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The subject matter described herein relates to methods and systems for reducing the chip count in computer systems and devices. More particularly, the subject matter described herein relates to methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory.
Conventional computer system architectures include three types of memory: random access memory (RAM), which is used as a work area for the operating system and applications and which is typically volatile memory; read only memory (ROM), which is used to store code that does not or should not change, such as the BIOS; and some form of non-volatile mass storage memory, such as a hard disk drive (HDD), which is used to store files, applications, etc. With the advent of FLASH memory and improvements in the reliability and lifetimes of FLASH memories, there is a trend to replace HDDs with SSDs, which have no moving parts and typically consume less power and space than their HDD counterparts. The use of SSDs allows the development of smaller and smaller computers and consumer devices, such as smart phones, handheld computers, and the like. Recent computer system architectures, however, continue to adhere to the legacy convention of maintaining a separate ROM for storing the BIOS. As used herein, the term “BIOS” refers to program code executed by a processor to perform BIOS functions, along with any data structures that may be used to store initial parameters or other information needed by the program code to perform the BIOS functions.
There are disadvantages associated with the conventional architectures described above, however. The systems illustrated in
There are other disadvantages associated with the conventional architectures shown in
Accordingly, in light of these disadvantages associated with conventional architectures, there exists a need for methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory.
According to one aspect, the subject matter described herein includes a system for providing BIOS data and non-BIOS data on the same non-volatile memory. The system includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.
According to another aspect, the subject matter described herein includes a system for providing a capability to reset a bus interface that lacks a dedicated reset signal. The system includes a bus controller having a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, the first bus interface having a reset signal input for receiving a reset request for resetting the first interface without resetting the controller, and a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, the second bus interface lacking a reset signal input for receiving a reset request for resetting the second interface without resetting the controller. The controller is configured to detect a reset request on the reset signal input of the first bus interface, and, in response to detecting the reset request, reset at least one of the first bus interface and the second bus interface without resetting portions of the controller other than the at least one of the first bus interface and the second bus interface.
According to yet another aspect, the subject matter described herein includes a system for providing BIOS data and non-BIOS data on the same non-volatile memory. The system includes a non-volatile memory for storing data, the data including BIOS data and non-BIOS data, and a controller for controlling access by a host to the non-volatile memory. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.
According to yet another aspect, the subject matter described herein includes a system for providing BIOS data and non-BIOS data on the same non-volatile memory. The system includes a non-volatile memory for storing data, the data including BIOS data and non-BIOS data, and a bus controller for controlling access by a host to the non-volatile memory. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, the first bus interface having a reset signal input for receiving a reset request for resetting the first interface without resetting the controller, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, the second bus interface lacking a reset signal input for receiving a reset request for resetting the second interface without resetting the controller, and a third interface for communicating data to and from the non-volatile memory. The controller is configured to detect a reset request on the reset signal input of the first bus interface, and, in response to detecting the reset request, reset at least one of the first bus interface and the second bus interface without resetting portions of the controller other than the at least one of the first bus interface and the second bus interface.
According to yet another aspect, the subject matter described herein includes a method for providing BIOS data and non-BIOS data on the same non-volatile memory. The method includes, at a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data, the controller having a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory: performing a power-on reset; providing access to BIOS data via the first bus interface; using at least some of the BIOS data to render operable the second bus interface; and providing access to non-BIOS data via the second bus interface.
According to yet another embodiment, the subject matter described herein includes a method for providing a capability to reset a bus interface that lacks a dedicated reset signal. The method includes, at a bus controller having a first bus interface for communicating data to and from a host via a first bus of a first bus protocol, the first bus interface having a reset signal input for receiving a reset request for resetting the first interface without resetting the controller, and a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, the second bus interface lacking a reset signal input for receiving a reset request for resetting the second interface without resetting the controller: detecting a reset request on the reset signal input of the first bus interface, and, in response to detecting the reset request, resetting at least one of the first bus interface and the second bus interface without resetting portions of the controller other than the at least one of the first bus interface and the second bus interface.
The subject matter described herein can be implemented in software in combination with hardware and/or firmware. For example, the subject matter described herein can be implemented in software executed by a processor. In one exemplary implementation, the subject matter described herein can be implemented using a non-transitory computer readable medium having stored thereon computer executable instructions that when executed by the processor of a computer control the computer to perform steps. Exemplary computer readable media suitable for implementing the subject matter described herein include non-transitory computer-readable media, such as disk memory devices, chip memory devices, programmable logic devices, and application specific integrated circuits. In addition, a computer readable medium that implements the subject matter described herein may be located on a single device or computing platform or may be distributed across multiple devices or computing platforms.
Preferred embodiments of the subject matter described herein will now be explained with reference to the accompanying drawings, wherein like reference numerals represent like parts, of which:
In accordance with the subject matter disclosed herein, systems, methods, and computer readable media are provided for providing BIOS data and non-BIOS data on the same non-volatile memory. Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
One obstacle to providing both BIOS and non-BIOS data on the same non-volatile memory, such as FLASH or a solid state drive, that uses a SATA interface is that although the SATA interface is suitable for mass transfer of non-BIOS data to and from the FLASH memory, the SATA interface is not immediately operable after reset, but requires firmware to be first loaded, making a SATA-only controller unable to perform the initial BIOS accesses. This obstacle is overcome by controller 200, since first bus interface 206 is operational immediately after reset without requiring firmware. In the embodiment illustrated in
After reset, host 202 may use LPC bus 208 to access the BIOS stored within non-volatile memory 204. In the embodiment illustrated in
In one embodiment, second bus interfaces 210 and/or 220 may require BIOS or firmware to be accessed before they are operational. In that scenario, host 202 may retrieve firmware, such as a SATA device driver, from non-volatile memory 204 using LPC bus 208. Once the device driver is installed and operational, host 202 may then activate its SATA interface 220 and use SATA bus 212 for bulk transfers of mass storage to and from non-volatile memory 204. In the embodiment illustrated in
In this manner, a system that uses controller 200 can store both BIOS data and non-BIOS data in the same non-volatile memory 204. In one embodiment, host 202 may use first bus 208 to perform byte-by-byte data transfers and use second bus 212 to perform multi-byte or bulk data transfers. In one embodiment, controller 200 and non-volatile memory 204 may be combined into one device 222, such as a solid state drive.
In one embodiment, one or both of the first and second bus protocols is a bus protocol that allows controller 200 rather than host 202 to operate as a bus master. For example, with the addition of optional pins, LPC bus interface 206 supports bus mastering by controller 200. This give controller 200 the ability to perform initialization routines on behalf of host 202 (or while host 202 is finishing its internal initialization routines) such as downloading BIOS or firmware from non-volatile memory 204 to other peripherals that share LPC bus 208.
Controller 300 also includes a second bus interface 308 for communicating data to and from host 302 via a second bus 310 of a second bus protocol, second bus interface 308 lacking a reset signal input for receiving a reset request for resetting the second interface without resetting the controller. Examples of bus interfaces that lack a reset signal input include a SATA interface and a PCIe interface.
Controller 300 is configured to detect a reset request on reset signal input RST of first bus interface 304. In response to detecting the reset request, in one embodiment controller 300 resets both first bus interface 304 and second bus interface 306.
In one embodiment, controller 300 resets both bus interfaces without resetting any other portions of the controller. This is useful when second bus interface 308, which does not have a reset input signal, locks up or otherwise becomes inoperative. In that event, host 302 may detect that bus 310 is not working and use the reset signal of bus 306 to reset second bus interface 308 in an attempt to restore bus 310 to working condition without resorting to the drastic measure of resetting controller 300 completely.
Alternatively, controller 300 may respond to a reset request on reset signal input RST of bus interface 304 by performing a full reset of controller 300. This arrangement is useful where controller 300 is remote from host 302, e.g., where host 302 does not have access to or control of a master reset pin on controller 300 or where controller 300 does not have master reset pin.
In the embodiment illustrated in
In one embodiment, reset control circuit 314 may be configured to detect a non-standard signal voltage or sequence on reset signal input RST of first bus interface 304 and respond by resetting second bus interface 308 without resetting first bus interface 304.
It will be understood that features of the system illustrated in
Controllers 200 and 300 may implement their respective bus interfaces using dedicated logic or circuitry. Alternatively, they may emulate the function of a bus interface and/or the function of an internal bus using software executing within the controller, which is colloquially referred to as “bit-banging.”
An additional advantage to the embodiments illustrated in
It will be understood that various details of the subject matter described herein may be changed without departing from the scope of the subject matter described herein. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation.
Asfur, Mahmud, Tzafrir, Yonatan
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Nov 27 2011 | ASFAR, MAHMUD | SanDisk Technologies Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 027724 | /0722 | |
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May 20 2012 | ASFUR, MAHMUD | SanDisk Technologies Inc | CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF ASSIGNOR S, MAHMUD ASFUR, LAST NAME PREVIOUSLY RECORDED ON REEL 027724 FRAME 0722 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT | 028452 | /0842 | |
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