Methods for fabricating dense arrays of electrically conductive nanocrystals that are self-aligned in depressions at target locations on a substrate, and semiconductor devices configured with nanocrystals situated within a gate stack as a charge storage area for a nonvolatile memory (NVM) device, are provided.
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1. A method of forming nanocrystals on a substrate, comprising:
forming a plurality of depressions in a surface of the substrate, the depressions having a depth and sidewalls;
forming a first insulating layer over the substrate;
forming a semiconductor layer over the first insulating layer;
annealing the semiconductor layer to form a plurality of spaced apart nanocrystals on the first insulating layer;
forming a second insulating layer over the nanocrystals and the first insulating layer; and
forming a semiconductor layer over the second insulating layer;
wherein density of the nanocrystals within the depressions is higher than density of the nanocrystals on the surface of the first insulating layer outside the depressions.
14. A method of forming a nonvolatile memory device, comprising:
providing a semiconductor substrate having a source region, a drain region and a channel region therebetween;
patterning and etching a plurality of depressions in a surface of the semiconductor substrate opposite the channel region, the depressions having a depth and sidewalls;
forming a first insulating layer over the semiconductor substrate including on the depressions;
forming a semiconductor layer over the first insulating layer;
annealing the semiconductor layer to form a plurality of nanocrystals on the insulating layer;
forming a second insulating layer over the nanocrystals;
forming a semiconductor layer over the second insulating layer; and
patterning the semiconductor layer and the second insulating layer to form a gate stack;
wherein the plurality of nanocrystals on the depressions are capable of storing an electrical charge.
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The disclosure relates generally to semiconductor processes and devices, and more particularly to methods for forming semiconductor devices having nanocrystals, and to nanocrystal storage devices.
Nonvolatile data storage is commonly used in integrated circuits. Conventional nonvolatile transistor memory cells commonly include a polysilicon floating gate formed over a tunnel dielectric over a semiconductor substrate as a charge storage region. Some types of semiconductive devices for nonvolatile data storage use isolated nanocrystals (also referred to as nanoparticles) to replace the floating gate as a charge storage area. Charge is transferred through the tunnel dielectric (also referred to as tunnel oxide) to the nanocrystal layer. The electrostatic properties of the nanocrystal layer are modified, which influences a subsurface channel region between source and drain in a MOS transistor to represent various logical values. The charge capturing capability of the nanocrystals is affected by the density, size and distribution of the nanocrystals. The nanocrystals are distributed over the channel region and should be capable of holding a sufficient charge. Too few nanocrystals may not be able to control the channel.
In order to have a significant memory effect, it is necessary to have a high density of nanocrystals forming the charge storage regions. Current methods form nanocrystals using, for example, a chemical vapor deposition (CVD) technique to deposit a semiconductor material over a substrate. The material is then annealed to form the nanocrystals.
As the size of semiconductor devices scale down to 40 nm and beyond, the number of nanocrystals per bit cell dwindles. Consequently, with ever shrinking devices, nanocrystal distribution in a charge storage area increasingly impacts bit cell performance and reliability. To extend current nanocrystal technology to the next node as a storage source, formation of a required density of nanocrystals within a bit cell, particularly in conjunction with the channel region of a control gate or memory gate, is desired.
Embodiments of the present invention are illustrated by way of example and are not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Embodiments of the invention generally include methods for forming a high density of self-aligned nanocrystals over a substrate or over tunnel oxide, and semiconductor devices such as nonvolatile memory (NVM) devices configured with a plurality of nanocrystals that function as a charge storage area.
Embodiments disclosed herein provide nanocrystals in a highly dense array within trenches or other controlled depressions or indentations that are patterned on the surface of an insulating layer (e.g., tunnel oxide). By providing intentional, structured sites (e.g., trenches) which are preferred for nanocrystal nucleation and formation, a dense distribution of nanocrystals can be provided at desired locations or the substrate, rather than nanocrystals having a random distribution over the substrate. With methods of embodiments of the invention, nanocrystals are readily grown and self-align on the depressions formed in the insulating layer. The pattern of depressions provides nucleation sites at desired locations on the surface of the insulating layer to seed the growth of nanocrystals from deposited material. The concentration of nanocrystals in specific areas provides a highly dense charge storage area. A charge storage area formed by the nanocrystals on the depressions can readily scale with reduced dimensions (length, width) of a control or memory gate. Nanocrystal charge storage area formed according to embodiments of the invention have improved reliability and program/erase performance for next node split gate nonvolatile memory (NVM) devices (e.g., N+1, N+2).
The depressions 18 can be formed in a variety of shapes and dimensions according to the application and device node. In some embodiments, the length and width of the depressions can be in a range of about 20-160 nm, and the depth (d) of the depressions 18 can be in a range of about 3-80 nm, or about 20-50 nm. For example, in embodiments in which the nanocrystals form a charge storage area of a nonvolatile memory device, the length and width dimensions of the depressions are less than the length and width dimensions of the overlying gate. The depth of the depressions is generally determined by device node and nanocrystal size and density.
The depressions 18 can be formed, for example, as trenches, grooves, channels, divots, pits, indentations, cavities, and concavities, among other shapes and configurations. In some embodiments, the depressions 18 can be concave or angled, with sidewalls that are angled at greater than zero. As depicted in
The depressions 18 provide nucleation sites having a lower surface energy, and thus a lower nucleation barrier, which promote and facilitate nucleation of the semiconductive material. The depressions 18 reduce the contact angle (e.g., wetting angle) of the depositing semiconductor material 24 (e.g., amorphous silicon) with the surface 26 of the insulating layer 22. This in turn reduces the nucleation barrier resulting in enhanced and faster nucleation and growth rates on the depressions 18.
Annealing the semiconductor layer 24 results in the formation of a plurality of individual, discrete nanocrystals 30 (also called nanoparticles) which are dispersed over the surface 26 of the insulating layer 22 with a higher density of nanocrystals on the depressions 18. The anneal causes the semiconductor (e.g., amorphous silicon) layer 24 to dewet from the insulating layer and form the nanocrystal structures. The nanocrystals 30 are physically separated from each other. In embodiments, for example, the nanocrystals 30 can have an average diameter of about 3-20 nm.
The depressions 18 create a difference in surface adhesion on the surface 26 of the insulating layer 22. This difference in surface tension or energy makes the depressions 18 preferred sites for nucleation and crystal formation of the semiconductor layer 24 (e.g., amorphous silicon) such that the nanocrystals self-align on the insulating layer within the depressions 18.
The nanocrystals 30 are generally uniformly distributed over the surface 26 of the insulating layer 22 outside the depressions 18, for example, at a density of about 1E11 to 3E11 nanocrystals per cm2. In some embodiments, the number of nanocrystals 30 on the depressions 18 is about 1.5 times more than the number of nanocrystals on the insulating layer 22 outside the depressions.
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The terms “top,” “bottom,” “over,” “under,” “overlying,” “underlying,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
The terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one,” “at least two,” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to devices, etc., containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same applies to the use of definite articles.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required or essential feature or element of any or all of the claims.
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