A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal, a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase, wherein a transition error detection circuit comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals.
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1. A sequential circuit with transition error detector, comprising:
a sequential element with an input signal that is asserted to an output during a second clock phase of a two phase clock signal; and
a transition error detector coupled to the sequential element input signal, the transition error detector configured to assert an error signal if a transition occurs at the sequential element input signal during the second clock phase and configured to not assert the error signal during a first clock phase, wherein the transition error detector further comprises a current mode logic circuit as a transition error detection circuit configured to detect at least one transition timing error from signals derived from at least one of the sequential element two phase clock signal or input signal.
2. The sequential circuit of
3. The sequential circuit of
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5. The sequential circuit of
6. The sequential circuit of
7. The sequential circuit of
8. The sequential circuit of
9. The sequential circuit of
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1. Field of the Disclosure
The invention relates to combinatory logic timing error detection and especially to improvements to subthreshold CMOS devices by a use of a type of new timing error detection circuit.
2. Description of Related Art
In conventional digital design flow, combinational logic delay constraints are static in the sense that the resulting circuit from synthesis must meet the worst case operation condition delays in order to guarantee the circuit operation. If the run-time delay is longer than analyzed during the design time, correct circuit operation cannot be secured. In a conventional design, meeting timing requirements introduces overdesign leading to both area and power—dynamic and static—consumption increase in the system. On the other hand, a timing error detection (TED) system equipped with Error-Detection Sequential (EDS) latches (Bowman, K. A.; et. al. “Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance” IEEE Journal of Solid-State Circuits, Volume: 44, Issue: 1, Page(s): 49-63, 2009) can tolerate late arriving signals from combinational logic. The EDS latch detects late arriving data and reacts to recover from the error. EDS operation is conceptually shown in
The minimum energy point for static CMOS logic is in the subthreshold region, where the operating voltage is below the threshold voltage of the CMOS transistors. Although minimum energy operation is achieved, the effect of the variations in modern deep submicron CMOS processes is greatly increased. Subthreshold current is due to diffusion charge transport mechanism and it can be observed that the drain current is exponentially related to the gate-source voltage, drain-source voltage, and thermal voltage. From this exponential relationship it can be seen that, when compared to nominal operating conditions (strong inversion), effects of process variation, supply voltage, and temperature are greatly amplified in the subthreshold operating region.
Combining subthreshold design with TED mitigates the subthreshold design hindrances. Although adding TED circuitry introduces extra energy consumption, the timing error information provided by the TED circuitry can be used to control the circuit operation for better energy efficiency. With TED, circuits can be designed with relaxed timing margin overhead, and dynamic voltage (DVS) or frequency (DFS) scaling can be used alongside error recovery. This works not only from process variance and operating conditions point of view, but a TED system also takes into account data related delay variance issues. However, if the circuits designed for the nominal voltage range are used in the subthreshold range, the size, and thus the energy consumption, of the circuits grows unfeasibly large (Turnquist, M. J.; et. al. “Adaptive Sub-Threshold Test Circuit” NASA/ESA Conference on Adaptive Hardware and Systems, 2009. Page(s): 197-203, 2009).
Subthreshold source-coupled logic (STSCL) can be used to provide both robustness to process, supply voltage and temperature (PVT) variations and reduced power consumption in subthreshold. STSCL has been shown to consume less power than static CMOS for low operation frequencies. Since the delay of an STSCL gate is independent of the threshold voltage (VT), STSCL is more robust to PVT than static CMOS. In addition, STSCL allows for accurate control of gate current consumption and operation frequency. These advantages are all beneficial for TED systems operating in subthreshold where less power overhead, robustness, and ease in adaptability are considered key parameters. As shown in
Error detection principle and error discovery is described in US 2010/079,184 (A1) now U.S. Pat. No. 8,301,970, and in WO2004084072. The general ideas of timing error detection and recovery are not described here in detail. Current mode logic circuits are described in US2009/219,054 (A1)now abandoned.
One object of the invention is to minimize the effects of sensitivity to PVT variations of the device and timing error detection. The invention allows use of for example subthreshold CMOS circuits, and it allows also larger voltage and temperature tolerances.
Modern digital design flow CAD tools do not support STSCL, which forces STSCL to be designed by hand. Accordingly, a new approach is required. This approach should integrate the robustness of STSCL but can be placed within the conventional digital design flow. The purpose of our invention is also to overcome the aforementioned problems.
The object is achieved by a circuit according to the claim 1.
An embodiment of our invention, a Sequential Circuit with Current Mode Error Detection (SCCMED), is shown in
The block diagram of the Current Mode Sequential Circuit with Error Detection is shown in
Although the latch 405 of the figure is a positive edge triggered latch, it should be appreciated that any type of latch (for example negative edge triggered) can be used without any loss of generality. The latch input is connected to the critical path of the logic (D) of which the timing errors are to be detected. The error detection according to invention may be used with any sequential element with suitable timing requirements for the TED-device.
The delay line (404) consists of three delay stages, which can be, but are not limited to, conventional static CMOS inverters or SCSTL inverters. The function of the delay line is to pass on the critical path signal D to the transition detector in three delayed stages. The delay line may be made of alike gates as the element 404, resulting to alike delays temperature and voltage dependencies as in the element 404. The delays may also controllable, for example by controlling the current.
The transition detector includes a timing error reset switch (401), consisting of transistors M3 and M6, a pulldown network switch (402) (transistors M1, M2, M4, M5), and a latching switch (403) (transistors M7, M8, M9, M10, M11, M12). The function of the combination of the load line 406 and transition detector 401, 402, 403 is to recognize a transition of D during the time CLK is high. A transition of D during CLK high generates a differential timing error (i.e. ERR goes high and ERRn low). This is the result of (402) pulling ERRn low and 403 being OFF. After a transition of D is complete, 403 is ON and keeps ERR high and ERRn low until a negative CLK edge. The functionality of Error Detection can be further explained with the help of
The term “transistor” here encompasses both N-type and P-type metal oxide field effect (MOS) transistors. Further encompassed are MOS transistors, where different parameters such as VT, material type, gate size and configuration, insulator thickness, etc. are varied. The term “transistor” can also include other FET-type and bipolar-junction transistors and other types of transistors known to those skilled in the art related to the present disclosure.
Aspects of the present invention also provide for a method detecting a transition error in a sequential circuit. As shown in
Mäkipää, Jani, Koskinen, Lauri, Turnquist, Matthew, Laulainen, Erkka
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