Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.
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1. A method of manufacturing, comprising:
coupling a plurality of substrates to form a stack, wherein at least one of the plurality of substrates is a semiconductor chip;
forming a plurality of conductive vias in a first of the plurality of substrates using a first material deposition;
forming a plurality of via extensions that are in ohmic contact with the plurality of conductive vias in the first of the plurality of substrates, wherein the plurality of via extensions are formed using a subsequent material deposition; and
positioning the plurality of via extensions to a plurality of solder structures on a circuit board, wherein each of the solder structures includes a portion projecting beyond a solder mask on the circuit board.
7. A method of manufacturing, comprising:
providing a circuit board and a solder mask on the circuit board, the solder mask including a plurality of openings;
forming a solder structure in each of the plurality of solder mask openings, each of the solder structures including a portion projecting beyond the solder mask; and
coupling the solder structures to corresponding via extensions of a stack of substrates, wherein at least one of the substrates is a semiconductor chip and the via extensions are in ohmic contact with corresponding conductive vias in the at least one of the substrates, and wherein the conductive vias are formed using a first material deposition and the via extensions are formed using a subsequent material deposition.
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This application is a continuation of U.S. patent application Ser. No. 13/017,946, filed Jan. 31, 2011, which is incorporated herein by reference in its entirety for all purposes.
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for stacking multiple semiconductor devices and packaging the same.
2. Description of the Related Art
Some time ago semiconductor chip designers began stacking multiple semiconductor dice (aka “dies”) vertically in order to obtain more functionality without an attendant increase in required package substrate or circuit board area. A variety of techniques have been used to electrically connect adjacent dice in such stacked arrangements. One technique has involved the use of wire bonds leading from contact pads on one die to corresponding contact pads on an adjacent die. Another technique that has been introduced more recently involves the use of so-called thru-silicon-vias (TSV). A typical TSV is a conductive via that extends nearly or perhaps entirely through a semiconductor chip, depending on the presence or absence of any intervening conductor pads at one or the other of the principal surfaces of the chip.
Most semiconductor chips are eventually mounted to some form of circuit board or enclosure. Typical examples include semiconductor chip package substrates, circuit cards, motherboards and other types of packaging closures. A technical challenge associated with most mounting schemes is the establishment of electrical interfaces between the semiconductor die or dice and the receiving circuit board. The fabrication of these electrical interfaces may be particularly challenging in a stacked dice arrangement. This follows from the fact that the multiple semiconductor chips may, by definition, include a significantly higher number of input outputs than a single semiconductor device.
One conventional technique for establishing electrical interconnects between a stacked dice arrangement and a circuit board involves the use of wire bond interconnects. Plural wire bonds are connected to conductor pads on one or more of the dice in the stacked dice arrangement and also to corresponding conductor pads on the circuit board or some other device on the circuit board. Another conventional arrangement for connecting a stacked dice arrangement to a circuit board involves the use of some form of control collapse bump arrangement wherein the plural solder joints are established between a lowermost of the stacked dice and the circuit board. This typically entails the formation of a solder bump on the lowermost die and a corresponding solder bump on the circuit board followed by a solder reflow process.
A more recent innovation involves the use of copper pillars that project outwardly from the lowermost die of a stacked dice arrangement and interconnect electrically with a circuit board. This conventional arrangement utilizes a low profile solder paste placed in plural low-profile openings in a solder mask on the circuit board. The lower ends of each of the copper pillars is fitted with a small solder cap. To establish the requisite connections, the die is positioned so that the solder caps of the copper pillars are in proximity or in contact with the low profile solder paste portions and a reflow process is performed. Expenses in the form of material and labor costs are associated with the conventional copper pillar process.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.
In accordance with another aspect of the present invention, a method of manufacturing is provided that includes providing a circuit board that includes an outermost surface and plural conductor pads. A solder structure is formed on each of the plural conductor pads. Each of the solder structures includes a portion projecting beyond the outermost surface. The solder structures are coupled to corresponding conductive vias of a stack of substrates. At least one of the substrates is a semiconductor chip.
In accordance with another aspect of the present invention, an apparatus is provided that has a stack including plural substrates. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are coupled to a principal surface of a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting away from the principal surface of the first substrate.
The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
Various embodiments of a semiconductor chip device that includes two or more stacked substrates are described herein. One example includes multiple substrates that may be semiconductor chips stacked and mounted on a circuit board. The lowermost of the substrates includes conductive vias that project beyond the chip and metallurgically bond with vertically projecting solder structures, such as solder pillars. The combination of the projecting vias and projecting solder structures provides sufficient solder volume to wet during reflow without the requirement to separately plate the vias with solder. Additional details will now be described.
In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to
The circuit board 35 may be a semiconductor chip package substrate, a circuit card, or virtually any other type of printed circuit board. A monolithic structure could be used for the circuit board 35, although a more typical configuration will utilize a build-up design. In this regard, the circuit board 35 may consist of a central core upon which one or more build-up layers are formed and below which an additional one or more build-up layers are formed. The core itself may consist of a stack of one or more layers. If implemented as a semiconductor chip package substrate, the number of layers in the circuit board 35 can vary from four to sixteen or more, although less than four may be used. So-called “coreless” designs may be used as well. The layers of the circuit board 35 may consist of an insulating material, such as various well-known epoxies, interspersed with metal interconnects. A multi-layer configuration other than buildup could be used. Optionally, the circuit board 35 may be composed of well-known ceramics or other materials suitable for package substrates or other printed circuit boards. The circuit board 35 is provided with a number of conductor traces and vias and other structures (not visible) in order to provide power, ground and signals transfers between the semiconductor chip 110 and another device, such as another circuit board for example. The circuit board 35 may be electrically connected to another device (not shown) by way of an input/output array such as the ball grid array 50 provided on the under surface 55 of the circuit board 35.
Electrical pathways between the substrates 15, 20, 25 and 30 and the circuit board 35 as well as between any of the substrates 15, 20, 25 and 30 are provided by plural interconnect structures that are not visible in
An underfill material layer 45 is dispensed between the substrate 15 and the circuit board 35 to alleviate issues of differential coefficient of thermal expansion. The underfill 45 may be formed from well-known polymeric materials, such as epoxies or others, with or without some form of filler, such as fiberglass or others. Only a portion of the underfill 45 is visible around the periphery of the substrate 15.
Attention is now turned to
The conductor structures in the various substrates 15, 20, 25 and 30 may be fabricated using well-known lithography and material deposition and/or removal techniques. Any or all of the vias, such as the vias 60, may be formed by fabricating plural holes or trenches in the substrate 30 and thereafter depositing or by plating, chemical vapor deposition, physical deposition, e-beam deposition or other techniques. A variety of conductor materials may be used, such as copper, gold, platinum, palladium, aluminum, titanium, refractory metals, refractory metal compounds, alloys of these or the like. Hole or trench formation may be by chemical etching, laser drilling or other material removal techniques. Higher aspect ratio openings will generally require more anisotropic techniques, such as laser drilling or plasma etching. The various pads, such as the pad 65 or 75 may be fabricated using the same techniques or alternatively by way of build up processes in which conductor material layer is plated and subsequently patterned by etch definition or other material removal techniques into the desired shapes for the pads 65, 75, etc.
The substrates 15, 20, 25 and 30 may be joined to one another to form the stack 13 in a variety of ways. Exemplary techniques include copper-to-copper direct bonding, silicon dioxide-to-silicon diffusion bonding, the application of an adhesive or other techniques. The copper-to-copper and silicon dioxide-to-silicon diffusion bonding involve pressing two substrates together so that corresponding conductor structures are touching or nearly, such as the vias 90 and the pads 85, and heating the combination to initiate the bonding. If an adhesive is contemplated, materials such as benzocylobutene or the like may be applied to one or both of the facing substrates and a thermal cure performed. The stacking may be performed on so-called die-to-die, die-to-wafer or even wafer-to-wafer bases. If die-to-wafer or wafer-to-wafer is used, singulation will follow the joining operation. Wafer-to-wafer joining may be more attractive where the dice to be joined are roughly the same size. Ohmic contact between the conductor structures of a given substrate, such as the substrate 20 and the next adjoining substrate chip 15, could also be established with solder.
Still referring to
To establish metallurgical bonds between the vias 90 and the solder structures 100, the stack 13 is put into the orientation depicted in
The solder structures 100 are advantageously fabricated to project beyond a principal or outermost surface of the circuit board 35, which in this case is an outermost surface 147 of the solder mask 115. This arrangement gives the solder structures sufficient volume to readily wet to the vias 90 without the necessity of fitting the vias 90 with solder caps. A variety of techniques may be used to form the solder structures 100 with the desired height projection. In this regard, attention is now turned to
Optionally, and as depicted in
An exemplary process flow for fabricating the vias 90 depicted in
Next and as depicted in
An alternate exemplary process for fabricating the vias now numbered 90′, may be understood by referring now to
An exemplary process for fabricating the solder structures as solder bumps such as those depicted in
An alternate exemplary process flow for establishing the solder structures as pillars, like the pillars 100 depicted in
It may be useful at this point to contrast an exemplary conventional multiple chip stack-to-circuit board joining process and structure. Attention is now turned to
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Fu, Lei, Su, Michael Zhuoying, Kuechenmeister, Frank Gottfried
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
6053397, | Nov 12 1996 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Method for the manufacture of micro solder bumps on copper pads |
6451626, | Jul 27 2001 | Three-dimensional stacked semiconductor package | |
6525413, | Jul 12 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Die to die connection method and assemblies and packages including dice so connected |
6661086, | Nov 15 1999 | Infineon Technologies AG | Three-dimensionally embodied circuit with electrically connected semiconductor chips |
6683374, | Aug 30 2001 | Infineon Technologies AG | Electronic component and process for producing the electronic component |
6794741, | Jul 27 2001 | Bridge Semiconductor Corporation | Three-dimensional stacked semiconductor package with pillars in pillar cavities |
6847105, | Sep 21 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Bumping technology in stacked die configurations |
6984889, | May 25 2001 | Renesas Electronics Corporation | Semiconductor device |
7132736, | Oct 31 2001 | Georgia Tech Research Corporation | Devices having compliant wafer-level packages with pillars and methods of fabrication |
7183648, | Jul 02 2003 | Intel Corporation | Method and apparatus for low temperature copper to copper bonding |
7205646, | May 19 2000 | Qualcomm Incorporated | Electronic device and chip package |
7217999, | Oct 05 1999 | Renesas Electronics Corporation | Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semiconductor chip on the interconnection board |
7453150, | Apr 01 2004 | Rensselaer Polytechnic Institute | Three-dimensional face-to-face integration assembly |
7462930, | Jan 26 2006 | Samsung Electronics Co., Ltd. | Stack chip and stack chip package having the same |
7468558, | May 03 2002 | Georgia Tech Research Corporation | Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof |
7498668, | Oct 27 2005 | Panasonic Corporation | Stacked semiconductor device and lower module of stacked semiconductor device |
7518230, | Dec 14 2005 | Taiwan Semiconductor Manufacturing Company, Ltd | Semiconductor chip and semiconductor device |
7545028, | Feb 08 2005 | XILINX, Inc. | Solder ball assembly for a semiconductor device and method of fabricating same |
20060201997, | |||
20090041981, | |||
20100015762, | |||
20110042798, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jan 12 2011 | FU, LEI | Advanced Micro Devices, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036224 | 0128 | |
Jan 12 2011 | KUECHENMEISTER, FRANK GOTTFRIED | Advanced Micro Devices, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036224 | 0128 | |
Jan 12 2011 | SU, MICHAEL ZHUOYING | Advanced Micro Devices, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036224 | 0128 | |
Jun 12 2015 | Advanced Micro Devices, Inc. | (assignment on the face of the patent) |
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