One embodiment of the instant disclosure provides a transistor device that comprises: a semiconductor substrate; a buffer layer formed in a fin structure over the semiconductor substrate; a nanowire formed over the buffer layer, having at least a middle portion suspended over the buffer layer by an undercutting, the nanowire including a source and a drain region respectively defined at distal portions thereof and a channel region defined in the suspended portion of the nanowire and connecting the source and drain regions; and a gate structure surrounding at least a portion of the suspended portion of the nanowire.
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17. A transistor device comprising:
a semiconductor substrate;
a buffer layer formed over the semiconductor substrate;
a nanowire formed over the buffer layer, and including a channel region, and a source region and a drain region connected by the channel region;
a gate region surrounding the nanowire; and
a remnant of a sacrificial layer between the buffer layer and the nanowire, wherein the gate region and the remnant of the sacrificial layer define a distance l therebetween and the distance l is such that a potential barrier between the source region or the drain region and the buffer layer is higher than an operation voltage of the transistor device.
1. A transistor device, comprising:
a semiconductor substrate;
a buffer layer formed over the semiconductor substrate;
a nanowire formed over the buffer layer and having a pair of distal portions, the nanowire including
source and drain regions respectively defined at the distal portions of the nanowire and
a channel region connecting the source and drain regions of the nanowire;
a gate structure surrounding the nanowire; and
a remnant of a sacrificial layer between the buffer layer and the nanowire, wherein the gate structure and the remnant of the sacrificial layer define a distance l therebetween and the distance l determines a degree to which areas of the source region or the drain region are electrically isolated from the buffer layer.
18. A transistor device comprising:
a semiconductor substrate;
a buffer layer formed over the semiconductor substrate;
a nanowire formed over the buffer layer, and including a channel region, and a source region and a drain region connected by the channel region; and
a gate surrounding the nanowire and including a high-k dielectric layer, wherein a ratio of the thickness of the high-k dielectric layer to the width of the channel region is such that a potential barrier between the source region or the drain region and the buffer layer is higher than an operation voltage of the transistor device;
a remnant of a non-silicon semiconductor layer between the buffer layer and the nanowire, wherein the gate structure and the remnant of the non-silicon semiconductor layer define a distance l therebetween and the distance l determines a degree to which areas of the source region or the drain region are electrically isolated from the buffer layer.
2. The device of
a gate dielectric layer surrounding the channel region of the nanowire,
a gate metal layer disposed over the gate dielectric layer, and
a gate spacer disposed over the the nanowire.
3. The device of
5. The device of
6. The device of
7. The device of
8. The device of
9. The device of
10. The device of
12. The device of
13. The device of
14. The device of
15. The device of
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This application is a divisional application of U.S. patent application Ser. No. 14/101,715, now U.S. Pat. No. 9,136,332, entitled “METHOD FOR FORMING A NANOWIRE FIELD EFFECT TRANSISTOR DEVICE HAVING A REPLACEMENT GATE,” filed Dec. 10, 2013, which is incorporated herein by reference in its entirety.
The technology described in this disclosure relates generally to nanowire-based devices and more particularly to nanowire-based field effect transistors (FETs) and techniques for the fabrication thereof.
Gate all around (GAA) nanowire channel field effect transistors (FETs) may enable feature scaling beyond current planar complementary-metal-oxide semiconductor (CMOS) technology. Nanowire channel FETs may also be of interest due to their electrostatics, which may be superior to those of conventional FET devices. The fabrication of nanowire channel FETs may include generating a collection of nanowires and placing them where desired (e.g., a bottom-up approach) or may include various lithographic patterning procedures (e.g., a top-down approach).
The channel layer 102 may comprise a non-silicon nanowire that is used to provide a channel region of the lateral nanowire FET. For example,
At 140 of
At 160 of
In the end-product device structure depicted at 160 of
As noted above, the channel layer 102 may be a non-silicon semiconductor material that is provided via an epitaxial growth process. The non-silicon semiconductor material used for the channel layer 102 may include, for example, compound group III-V semiconductors, group IV semiconductors, or other materials. Such compound group III-V semiconductors or group IV semiconductors may comprise high mobility channel materials and may be used to replace silicon nanowires used in conventional nanowire FET devices. The replacement of the silicon nanowires with the high mobility semiconductor materials may be complicated by various issues, however. For example, the high mobility channel materials having a different lattice parameter to silicon may be highly defective at the epitaxially formed interface with silicon. Further, implant doping to create an isolation well may not be a simple matter in the group III-V and IV semiconductors, and bulk-like or buffer layers of high mobility semiconductors may be conductive, thus leading to unwanted source-drain leakage currents.
The lateral nanowire field effect transistor (FET) described above with reference to
A thickness of the channel layer 206 (i.e., “tchannel”) may be within a range of approximately 5 nm to 30 nm. A thickness of the etch layer 208 (i.e., “tetch”) may be within a range of approximately 1 nm to 15 nm. A thickness of the buffer layer 210 (i.e., “tbuffer”) may be within a range of approximately 20 nm to 300 nm. Such thicknesses are exemplary only, and the layers 206, 208, 210 may be fabricated to various other thicknesses. In an example, the thickness tetch may be one to fifteen times smaller than the thickness tchannel, which may cause the etch layer 208 to comprise a strained layer. The use of a strained layer for the etch layer 208 may increase a number of potential material systems that may be used in fabricating the etch layer 208. Because the etch layer 208 is a sacrificial layer that is removed via an etch process, the increased number of potential material systems may allow a greater etch selectivity to be engineered.
In the extension cross-section, the extension 214 may be formed substantially over the channel layer 206 and the etch layer 208, such that the extension 214 surrounds three sides of the channel layer 206 and two sides of the etch layer 208. The extension 214 may comprise a spacer material, and the spacer material may be, for example, a nitride spacer, an oxide spacer, or another type of spacer material. The spacer material may be used to maintain integrity of the gate region or other portions of the semiconductor structure throughout the fabrication process (e.g., to reduce interaction with aggressive chemicals that may be used in further processing). Following the formation of the dummy gate 212 and the extension 214, source and drain regions of the FET may be formed. In the interest of clarity, the source and drain regions may not be depicted in
Similar to
As illustrated in
The etching of the etch layer 208 may be understood as including multiple aspects. In a first aspect of the etching, a first portion of the etch layer 208 may be etched, where the first portion may comprise the portion of the etch layer 208 that is directly exposed to the etchant via the opening 218. In a second aspect of the etching, a second portion of the etch layer 208 may be etched, where the second portion may comprise a portion of the etch layer 208 that is removed via etch undercutting. The portion of the etch layer 208 that may be removed via the etch undercutting may be characterized by a distance L, as depicted in
As illustrated in
In
Group IV semiconductor material system options for the buffer layer may include Si, SixGe1-x (0.0≦x≦1.0), or Ge. Group IV semiconductor material system options for the etch layer may include Ge (e.g., Ge strained on Si). Further, an AlAsyP1-y (0.0≦y≦1.0, optionally lattice matched to the buffer) etch layer that is grown between group IV layers may be used. Group IV semiconductor material system options for the channel layer may include Si, SixGe1-x (0.0≦x≦0.5), or SixGe1-x (0.0≦x≦1.0).
As illustrated in
Accordingly, one aspect of the instant disclosure provides a transistor device, which comprises: a semiconductor substrate; a buffer layer formed in a fin structure over the semiconductor substrate; a nanowire formed over the buffer layer, having at least a middle portion suspended over the buffer layer by an undercutting, the nanowire including a source and a drain region respectively defined at distal portions thereof and a channel region defined in the suspended portion of the nanowire and connecting the source and drain regions; and a gate structure surrounding at least a portion of the suspended portion of the nanowire.
Accordingly, another aspect of the instant disclosure provides a transistor device that comprises: a semiconductor substrate; a device layer including a source region and a drain region, the source region and the drain region being connected by a channel region that comprises at least a portion of a nanowire, wherein the channel region is formed over a buffer layer; a gate region that surrounds at least the portion of the nanowire; and a distance L beneath the source region or the drain region, wherein 0≦L≦LS/D, such that a potential barrier between the source region or the drain region and the buffer layer is higher than an operation voltage of the transistor device.
Accordingly, yet another aspect of the instant disclosure provides a transistor device that comprises: a semiconductor substrate; a device layer including a source region and a drain region, the source region and the drain region being connected by a channel region that comprises at least a portion of a nanowire with a determined diameter, wherein the channel region is formed over a buffer layer; and a gate that surrounds at least the portion of the nanowire, wherein the gate comprises a high-k dielectric layer deposited in a conformal manner over all sides of the portion, wherein a ratio of the thickness of the high-k dielectric layer to the thickness of the diameter of the nanowire determined by the channel region is between about ⅓ and 1, such that a potential barrier between the source region or the drain region and the buffer layer is higher than an operation voltage of the transistor device.
This written description uses examples to disclose the disclosure, including the best mode, and also to enable a person skilled in the art to make and use the disclosure. The patentable scope of the disclosure may include other examples. It should be understood that as used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. Further, as used in the description herein and throughout the claims that follow, the meaning of “each” does not require “each and every” unless the context clearly dictates otherwise. Finally, as used in the description herein and throughout the claims that follow, the meanings of “and” and “or” include both the conjunctive and disjunctive and may be used interchangeably unless the context expressly dictates otherwise; the phrase “exclusive of” may be used to indicate situations where only the disjunctive meaning may apply.
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