Embodiments herein describe dummy gates disposed over a portion of a fin in finfets. That is, instead of separating the dummy gates from the finfet structure, the fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor. In one embodiment, the dummy gate overlaps a portion of the fin that is held at a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than rail coupled to the fin. For example, if the fin is coupled to VHIGH then the dummy gate is coupled to VLOW, or vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., VHIGH and VLOW).
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10. An integrated circuit, comprising:
a fin extending in a first direction on a substrate;
a gate extending in a second direction on the substrate substantially perpendicular to the first direction, wherein the gate is disposed over a first portion of the fin in order to selectively activate a conductive channel in the first portion of the fin in response to a time-varying gate signal; and
a dummy fin structure extending in the second direction on the substrate and overlapping a second portion of the fin, wherein the dummy fin structure is coupled to a first voltage rail; and
a conductive contact coupled with a third portion of the fin located between the first and second portions, the contact electrically coupling the third portion of the fin to a second voltage rail different from the first voltage rail,
wherein the dummy fin structure surrounds the second portion of the fin on at least three sides, and wherein the fin does not extend through the dummy fin structure.
13. A method of operating a finfet, comprising:
driving a time-varying gate signal onto a gate extending in a first direction on a substrate, wherein the gate is disposed over a first portion of a fin extending in a second direction on the substrate substantially perpendicular to the first direction, and wherein the time-varying signal selectively activates a conductive channel in the first portion of the fin;
while driving the time-varying gate signal, driving a first dc voltage on a dummy fin structure extending in the second direction on the substrate, the dummy fin structure overlapping a second portion of the fin;
while driving the time-varying gate signal, driving a second dc voltage different from the first dc voltage on a conductive contact contacting a third portion of the fin that is located between the first and second portions;
receiving the first dc voltage from a first dc power supply; and
receiving the second dc voltage rail from a second dc power supply.
1. A fin field effect transistor (FET) comprising:
a fin extending in a first direction on a substrate;
a gate extending in a second direction on the substrate substantially perpendicular to the first direction, wherein the gate is disposed over a first portion of the fin in order to selectively activate a conductive channel in the first portion of the fin in response to a time-varying gate signal;
a dummy fin structure extending in the second direction on the substrate and overlapping a second portion of the fin, wherein the dummy fin structure is coupled to a first voltage rail;
a conductive contact contacting a third portion of the fin located between the first and second portions, the contact electrically coupling the third portion of the fin to a second voltage rail different from the first voltage rail; and
a dielectric material disposed between the dummy fin structure and the second portion of the fin, whereby the dielectric material and second portion of the fin form a decoupling capacitance between the first and second voltage rails.
2. The finfet of
3. The finfet of
5. The finfet of
a second fin extending in the first direction on the substrate, wherein the gates is disposed over a first portion of the second fin in order to selectively activate a conductive channel in the first portion of the second fin in response to the time-varying gate signal, and wherein the dummy fin structure overlaps a second portion of the second fin, and
wherein the conductive contact couples with a third portion of the second fin that is located between the first and second portions of the second fin.
6. The finfet of
a second dummy fin structure extending in the second direction on the substrate and overlapping a fourth portion of the fin, wherein the second dummy fin structure is coupled to a second voltage rail; and
a second conductive contact coupled with a fifth portion of the fin located between the first and fourth portions of the fin, the contact electrically coupling the fifth portion of the fin to a fourth voltage rail different from the third voltage rail.
7. The finfet of
a dielectric material disposed between the second dummy fin structure and the fourth portion of the fin, whereby the dielectric material and fourth portion of the fin form a decoupling capacitance between the third and fourth voltage rails.
8. The finfet of
9. The finfet of
a second gate extending in the second direction on the substrate substantially perpendicular to the first direction, wherein the second gate is disposed over a sixth portion of the fin in order to selectively activate a second conductive channel in the sixth portion of the fin in response to a second time-varying gate signal.
11. The integrated circuit of
a dielectric material disposed between the dummy fin structure and the second portion of the fin, whereby the dielectric material and second portion of the fin form a decoupling capacitance between the first and second voltage rails.
12. The integrated circuit of
a second fin extending in the first direction on the substrate, wherein the gates is disposed over a first portion of the second fin in order to selectively activate a conductive channel in the first portion of the second fin in response to the time-varying gate signal, and wherein the dummy fin structure overlaps a second portion of the second fin, and
wherein the conductive contact couples with a third portion of the second fin that is located between the first and second portions of the second fin.
14. The method of
15. The method of
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The present invention relates to incorporating decoupling capacitance into a fin field effect transistor (FET) structure, and more specifically, to the interaction between a fin in the finFET and a dummy gate.
FinFET semiconductor technology provides improved transistor performance versus historic planar FET technologies. However, finFETs have much larger gate capacitances when compared to similar sized planar FETs. This increased gate capacitance can have negative effects on the power supplies used to provide the rail voltages to the finFETs which may cause the rail voltages to droop as the gates are switched. This droop can decrease the switching speed of the finFETs and negatively affect the overall timing of the semiconductor chip.
According to one embodiment of the present invention is a finFET that includes a fin extending in a first direction on a substrate and a gate extending in a second direction on the substrate substantially perpendicular to the first direction, where the gate is disposed over a first portion of the fin in order to selectively activate a conductive channel in the first portion of the fin in response to a time-varying gate signal. Moreover, the finFET includes a dummy fin structure extending in the second direction on the substrate and overlapping a second portion of the fin, where the dummy gate is coupled to a first voltage rail. The finFET also includes a conductive contact contacting a third portion of the fin located between the first and second portions, the contact electrically coupling the third portion of the fin to a second voltage rail different from the first voltage rail.
Another embodiment of the present invention is an integrated circuit that includes a fin extending in a first direction on a substrate and a gate extending in a second direction on the substrate substantially perpendicular to the first direction, where the gate is disposed over a first portion of the fin in order to selectively activate a conductive channel in the first portion of the fin in response to a time-varying gate signal. Moreover, the integrated circuit includes a dummy fin structure extending in the second direction on the substrate and overlapping a second portion of the fin, where the dummy gate is coupled to a first voltage rail. The integrated circuit also includes a conductive contact contacting a third portion of the fin located between the first and second portions, the contact electrically coupling the third portion of the fin to a second voltage rail different from the first voltage rail.
Another embodiment of the present invention is of operating a finFET. The method includes driving a time-varying gate signal onto a gate extending in a first direction on a substrate, where the gate is disposed over a first portion of a fin extending in a second direction on the substrate substantially perpendicular to the first direction, and where the time-varying signal selectively activates a conductive channel in the first portion of the fin. While driving the time-varying gate signal, the method includes driving a first DC voltage on a dummy fin structure extending in the second direction on the substrate where the dummy fin structure overlaps a second portion of the fin. While driving the time-varying gate signal, the method also includes driving a second DC voltage different from the first DC voltage on a conductive contact contacting a third portion of the fin that is located between the first and second portions.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
The increased gate capacitance of finFETs relative to planar FET technologies may cause the rail voltages coupled to the finFETs to droop as the gate voltages change. As mentioned above, this droop can have a negative impact on the timing of the semiconductor circuit—e.g., force the finFETs to operate at slower frequencies that would otherwise be possible. To counter the effects of the gate capacitance, dummy fin structures (referred to herein as “dummy gates”) can be placed over a portion of a fin in the finFETs. Instead of separating the dummy gates from the finFET structure, one or more fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor.
In one embodiment, the dummy gate overlaps a portion of the fin that is driven to a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than the rail coupled to the fin. For example, the fin may be coupled to VHIGH (e.g., VDD), while the dummy gate is coupled to VLOW (e.g., VSS), or vice versa. In this manner, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., VHIGH and VLOW). This decoupling capacitance mitigates the negative effects of the large gate capacitance in the finFETs and may reduce or prevent the voltage rails from drooping, thereby permitting the finFETs to operate at faster frequencies.
The power path resistances 115 and 120 represent the electrical resistance between the power supplies and the FETs 105 and 110. Because the power supplies may be located at a different location on a semiconductor chip (or off the chip) than the FETs 105 and 110, the electrical path between these elements is represented by the resistances 115 and 120. The resistances 115, 120 represent the inherent resistance of the electrical path between the finFETs 105, 110 and the power supplies. For example, the electrical path between the FETs 105, 110 and the power supplies may include different metal layers, electrical vias, traces, and the like which each add some resistance. Because of the power path resistances 115 and 120, the voltage at FET 105 may be less than VHIGH, while the voltage at FET 110 may be greater than VLOW.
In one embodiment, the finFETS 105 and 110 have respective gate capacitances (i.e., the capacitance between the gate and the fin) which may cause the voltage rails VHIGH and VLOW to droop as the gate voltages switch. To mitigate this droop, the decoupling capacitor 125 is coupled between the voltages rails VHIGH and VLOW. Because the capacitor 125 is located at (or near) the same location as the FETs 105, 110 in the chip, the capacitor 125 is not affected by the resistances 115 and 120—i.e., the electrical resistance between the capacitor 125 and the finFETs 105, 110 is small relative to the resistances 115, 120.
The capacitor 125 provides a decoupling capacitance that “decouples” the voltage rails from the noise (i.e., droop) caused by the large gate capacitances of the FETs 105 and 110. To do so, in one embodiment, the capacitor 125 uses its stored charge to maintain the voltage rails close to their desired value by mitigating or preventing the droop caused when the FETs 105 and 110 switch. For example, when the switching FETs 105 and 110 cause the voltage rail to dip, this change in voltage is countered by charge flowing from the capacitor 125. Put differently, the capacitor 125 serves as a secondary (local) power source which can be used to inject or sink current in order to maintain the voltage rails close to VHIGH and VLOW.
The gate 205 may be made from silicide, polysilicon, metal, or any conductive material. The contacts 210 may be silicide, metal, or any conductive material. The fins 215 may be a crystalline semiconductor such as crystalline silicon. Moreover, the different portions of the fins 215 may be doped differently—i.e., either n-type or p-type. For example, the portions of the fins 215 to the left and right of the gate 205 may have higher dopant concentrations than the portions of the fins 215 underneath the gate 205.
In operation, a gate signal 220 drives a voltage onto the gate 205. Depending on whether the finFET 200 is a pFET or nFET, driving a first voltage on the gate 205 causes the charge carries (e.g., holes or electrons) in the fins 215 underneath the gate 205 to form a conductive channel between the left and right portions of the fins 215. When voltage driven by the gate signal 220 forms the conductive channel (i.e., the finFET 200 is activated), the left and right portions of the fins 115 are electrically connected and the out signal 230 is driven to voltage rail 225. As used herein, the “voltage rails” are constant DC voltages generated by power supplies. In one embodiment, the voltage rails are not intended to vary (although there may be some unintended droops in the voltage as discussed above) in contrast to control signals such as the gate signal 220 which change voltages to activate and deactivate the finFETs. During other time periods, the gate signal 220 drives a second voltage onto the gate 205 which ensures that no conductive channel is formed in the fins 215 (i.e., the finFET 200 is deactivated), thereby preventing current from flowing between the left and right portions. In this scenario, the out signal 230 is electrically floating.
For example, the capacitor formed by the right most ends of the fins 215 and the dummy gate 235A may be represented by the decoupling capacitor 125 shown in
In one embodiment, the dummy gate 235A overlaps only portions of the fins 215 that are directly driven by a voltage rail, which in
The dummy gate 235B, however, does not overlap the fins 115 and is not used as a decoupling capacitor. For example, the dummy gate 235B may be used to satisfy the predetermined gate density or alter a timing characteristic (e.g., coupling capacitance) but is not used to mitigate the droop caused by switching the states of the finFET 200. The dummy gate 235B may be electrically floating or tied to a voltage rail. If the dummy gate 235B was shifted to the right such that it covered a portion of the fins 215, because this portion of the fins 215 do not have a direct electrical connection to the voltage rail 225, doing so may increase the gate capacitance and exasperate the drooping issue described above. Thus, not every dummy gate 235 in the finFET 200 needs to overlap the fins 215. Indeed, it may be advantageous for the dummy gates 235 near portions of the fins 215 that are not directly coupled to a voltage rail to be spaced away from the finFET 200 to reduce any capacitive coupling between the dummy gate 235B and the FET 200.
Unlike the gate 205, the conductive contact 210B directly connects both physically and electrically to the fin 215C. As such, the voltage driven onto the contact 210B (i.e., voltage rail 225) is also driven onto the fin 215C. Referring to
However, in one embodiment, the finFET may be formed so that the fins 215A, B, and C extend through the dummy gate 235A. For example, aligning the dummy gate 235A and the fins 215 such that the fins 215 extend only partially into the dummy gate 235A may be too difficult (or expensive). In this case, it may be preferred to extend the fins 215 through the dummy gate 235A similar to how the fins 215 extend through the gate 205. Regardless of the particular structure used to generate the decoupling capacitance, the dummy gate 235A is driven to a first voltage rail while the portion of the fin 215 closest to the dummy gate 235A (i.e., the portion of the fin 215 on the same side of the gate 205 as the dummy gate 235A) is driven to a second, different voltage rail. For example, if fin 215A is driven to VHIGH, then dummy gate 235A is driven to VLOW, or vice versa.
The inverter 700 also includes dummy gates 735A, 735B that at least partially overlap the fins 715. As shown, dummy gate 735A overlaps the leftmost portions of the fins 715, while dummy gate 735B overlaps the rightmost portions of the fins 715. The dummy gate 735A is driven to voltage rail 740A which is different than the voltage rail 725A driven onto contact 710A, while dummy gate 735B is driven to voltage rail 740B which is different than the voltage rail 725B driven onto contact 710C. In one embodiment, the voltage rail 740A may be the same voltage as voltage rail 725B, while voltage rail 740B is the same voltage as voltage rail 725A. For example, voltage rails 740A and 725B may both be coupled to VHIGH, while voltage rails 740B and 725A are both coupled to VLOW. In this scenario, the capacitances formed by dummy gates 735A, 735B and fins 715 are in parallel, and thus, add together to increase the overall decoupling capacitance between the voltage rails (e.g., VHIGH and VLOW).
The contact 710A is in direct contact both physically and electrically with the fin 715A. Doing so drives the value of the voltage rail 725A onto the portion of the fin 715A proximate to the contact 710A. For example, the portion of the fin 715A to the left of the gate 705 may be heavily doped either n-type or p-type to provide a low resistance electrical conductor.
The dummy gate 735A overlaps an end of the fin 715A, which, as discussed above, generates a decoupling capacitor. Moreover, the dummy gate 735A is driven to a first voltage rail (e.g., VHIGH) while contact 710A and fin 715A are driven to a second, different voltage rail (e.g., VLOW). In this example, the fin 715A does not extend all the way through the dummy gate 735A which may increase the decoupling capacitance relative to a finFET where the fin 715A extends all the way through. However, in other embodiments, the fins 715 may extend through the dummy gates 735.
The spacers 805 lining the sides of the dummy gate 735A may have the same thickness or a different thickness than the spacers 805 lining the sides of the gate 705A.
At block 910, the integrated circuit drives a first DC voltage onto the dummy gate 235A disposed over the fin while driving the time-varying gate signal 220. In one embodiment, the first DC voltage is driven on the voltage rail 240 which is directly coupled to conductive material of the dummy gate 235A.
At block 915, the integrated circuit drives a second DC voltage different from the first DC voltage onto the conductive contact 210B contacting the fin while driving the time-varying gate signal. In
The increased gate capacitance of finFETs relative to planar FET technologies may cause the rail voltages coupled to the finFETs to droop as the gate voltages change. This droop can have a negative impact on the timing of the semiconductor circuit—e.g., cause the finFETs to operate at slower frequencies. To counter the effects of the gate capacitance, dummy gates can be placed over a portion of a fin in the finFETs. That is, instead of separating the dummy gates from the finFET structure, the fins may be extended and covered, at least partially, by the dummy gates. A dielectric material is disposed between the dummy gate and the fin in order to form a decoupling capacitor.
In one embodiment, the dummy gate overlaps a portion of the fin that is held at a rail voltage. Moreover, the dummy gate may be coupled to a different (e.g., opposite) rail voltage. For example, if the fin is coupled to VHIGH (e.g., VDD) then the dummy gate is coupled to VLOW (e.g., VSS), and vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., VHIGH and VLOW). This decoupling capacitance mitigates the negative effects of the large gate capacitance in the finFETs and may reduce or prevent the voltage rails from drooping, thereby permitting the finFETs to operate at faster frequencies.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
In the following, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Christensen, Todd A., Sheets, II, John E.
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