A package structure includes an integrated circuit die, a redistribution structure, an anti-fuse, and external connectors. The integrated circuit die is embedded in an encapsulant. The redistribution structure is on the encapsulant and is electrically coupled to the integrated circuit die. The anti-fuse is external to the integrated circuit die and the redistribution structure. The anti-fuse is mechanically and electrically coupled to the redistribution structure. The external connectors are on the redistribution structure, and the redistribution structure is disposed between the external connectors and the encapsulant.
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15. A method comprising:
forming a first redistribution structure, the first redistribution structure comprising first pads;
mechanically attaching an integrated circuit die to the first redistribution structure;
directly mechanically attaching a first anti-fuse to the first pads;
after directly mechanically attaching the first anti-fuse to the first pads, encapsulating the integrated circuit die in an encapsulant;
forming a second redistribution structure adjoining the encapsulant, the second redistribution structure comprising second pads, the second redistribution structure being directly mechanically attached to connectors of the integrated circuit die;
directly mechanically attaching a second anti-fuse to the second pads; and
mounting external connectors on the second redistribution structure, the second redistribution structure being disposed between the external connectors and the encapsulant, the external connectors and the second anti-fuse being disposed on a same side of the second redistribution structure.
1. A package structure comprising:
an integrated circuit die embedded in an encapsulant;
a first redistribution structure on a first side of the encapsulant and electrically coupled to the integrated circuit die;
a first anti-fuse external to the integrated circuit die and the first redistribution structure, the first anti-fuse being mechanically and electrically coupled to the first redistribution structure;
first external connectors on the first redistribution structure, the first redistribution structure being disposed between the first external connectors and the encapsulant, the first external connectors and the first anti-fuse being disposed on a same side of the first redistribution structure;
a second redistribution structure on a second side of the encapsulant and electrically coupled to the integrated circuit die, the second side of the encapsulant being opposite of the first side of the encapsulant;
a second anti-fuse external to the integrated circuit die and the second redistribution structure, the second anti-fuse being directly mechanically and electrically coupled to the second redistribution structure, the second anti-fuse being interposed between the first redistribution structure and the second redistribution structure; and
second external connectors on the second redistribution structure, the second redistribution structure being disposed between the second external connectors and the encapsulant, the second external connectors and the second anti-fuse being disposed on opposite sides of the second redistribution structure.
8. A package structure comprising:
a die comprising an integrated circuit, die connectors being on an active side of the die and electrically coupled to the integrated circuit;
an encapsulant at least laterally encapsulating the die;
a first redistribution structure on and adjoining the encapsulant, at least a portion of the first redistribution structure being directly coupled to the die connectors;
a first anti-fuse external to the first redistribution structure, the first anti-fuse being directly mechanically and electrically coupled to pads on an exterior side of the first redistribution structure;
a second redistribution structure on and adjoining the encapsulant, the second redistribution structure being disposed on an opposite side of the encapsulant from the first redistribution structure, through vias in the encapsulant electrically coupling at least a portion of the first redistribution structure with at least a portion of the second redistribution structure;
a second anti-fuse external to the second redistribution structure, the second anti-fuse being directly mechanically and electrically coupled to pads on an exterior side of the second redistribution structure, the die being interposed between the first anti-fuse and the second anti-fuse; and
a third anti-fuse directly mechanically and electrically coupled to the second redistribution structure, the third anti-fuse being directly mechanically and electrically coupled to pads of the second redistribution structure disposed on an interior side of the second redistribution structure, the third anti-fuse being embedded in the encapsulant.
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Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging, for example.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components such as integrated circuit dies may also require smaller packages that utilize less area than packages of the past, in some applications.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Similarly, terms such as “front side” and “back side” may be used herein to more easily identify various components, and may identify that those components are, for example, on opposing sides of another component. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Embodiments discussed herein may be discussed in a specific context, namely anti-fuses used in a fan-out or fan-in wafer-level package. Other embodiments contemplate other applications, such as different package types or different configurations that would be readily apparent to a person of ordinary skill in the art upon reading this disclosure. It should be noted that embodiments discussed herein may not necessarily illustrate every component or feature that may be present in a structure. For example, multiples of a component may be omitted from a figure, such as when discussion of one of the component may be sufficient to convey aspects of the embodiment. Further, method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.
Die connectors 44, such as conductive pillars (for example, comprising a metal such as copper), are exterior to the integrated circuit dies 42 and are mechanically and electrically coupled to the respective integrated circuit dies 42 on what may be referred to as respective active sides of the integrated circuit dies 42. The die connectors 44 electrically couple the respective integrated circuits of the integrate circuit dies 42.
A dielectric material 46 is on the active sides of the integrated circuit dies 42. The dielectric material 46 laterally encapsulates the die connectors 44, which have upper surfaces that are co-planar with upper surfaces of the dielectric material 46, and the dielectric material 46 is laterally co-terminus with the respective integrated circuit dies 42. The dielectric material 46 may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or the like; the like, or a combination thereof.
Adhesive 48 is on back sides of the integrated circuit dies 42 and adheres the integrated circuit dies to a front side redistribution structure 50. The adhesive 48 may be any suitable adhesive, epoxy, or the like.
The front side redistribution structure 50 comprises one or more metallization pattern 52 in one or more dielectric layer 54. The one or metallization pattern 52 can comprise any of lines, vias, pads, the like, or a combination thereof, and may comprise a conductive material, such as a metal, like copper, titanium, tungsten, aluminum, or the like. The one or more dielectric layer 54 may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like; or a combination thereof.
An encapsulant 56 at least laterally encapsulates the integrated circuit dies 42. The encapsulant 56 has a first surface that adjoins the redistribution structure 50 and has a second surface that is co-planar with upper surfaces of the dielectric material 46 and the die connectors 44. The encapsulant 56 may be a molding compound, epoxy, or the like.
Through vias 58 extend through the encapsulant 56, for example, from the first surface of the encapsulant 56 to the second surface of the encapsulant 56. The through vias 58 electrically couple the front side redistribution structure 50, for example, at least a portion of the one or more metallization patterns 52, with a back side redistribution structure 60, for example, at least a portion of one or more metallization patterns 62. The through vias 58 may comprise a conductive material, such as a metal, like copper, titanium, tungsten, aluminum, or the like.
The back side redistribution structure 60 comprises one or more metallization pattern 62 in one or more dielectric layer 64. At least a portion of the one or more metallization pattern 62 is electrically coupled to the respective integrated circuits on the integrated circuit dies 42 through the respective die connectors 44. The one or metallization pattern 62 can comprise any of lines, vias, pads, the like, or a combination thereof, and may comprise a conductive material, such as a metal, like copper, titanium, tungsten, aluminum, or the like. The one or more dielectric layer 64 may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like; or a combination thereof.
The one or more metallization pattern 62 comprises pads 66, 68, 70, and 72 exposed on the back side redistribution structure 60. The pads 66, 68, 70, and 72 may be locations for forming an anti-fuse. For example, a SMD 74, such as a resistor or any acceptable jumper, is bonded to the pads 66 and 68 to form an electrical connection between pads 66 and 68. In this example, no SMD is bonded between pads 70 and 72 such that no closed-loop circuit is formed between the pads 70 and 72. Thus, the SMD 74 may be an anti-fuse to create a closed-loop circuit to electrically couple, for example, portions of integrated circuits on integrated circuit dies 42 and/or various metallization patterns 52 and/or 62 in the redistribution structures 50 and 60. In some embodiments, the SMD 74 is a low resistance resistor, such as having a resistance less than about 0.1 ohms, and more specifically, less than about 0.05 ohms. In other embodiments, such as discussed below, other components, such as a wire bond or other acceptable jumper, may be used as an anti-fuse.
The one or more metallization pattern 62 further comprises an under-metal 76 exposed on the back side redistribution structure 60. An external connector 78, such as a solder ball like a ball grid array (BGA) ball, is on the under-metal 76. In some embodiments, the external connector 78 comprises solder, such as a Sn—Ag alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free or lead-containing.
Pads of the one or more metallization pattern 52 of the front side redistribution structure 50 are also exposed. External connectors 82, such as solder bumps, metal pillars, the like, or a combination such as metal pillars with solder thereon, are on the pads of the one or more metallization pattern 52. In some embodiments, the external connectors 82 comprise solder, such as a Sn—Ag alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free or lead-containing. A solder resist layer 80 is also on the front side redistribution structure 50.
The one or more metallization pattern 52 comprises pads 102, 104, 106, 108, 110, and 112. The pads 102, 104, 106, 108, 110, and 112 may be locations for forming an anti-fuse. For example, a SMD 114, such as a resistor or any acceptable jumper, is bonded to the pads 102 and 104 to form an electrical connection between pads 102 and 104. The SMD 114 is on an exterior surface of the package 100. Further in this example, a SMD 116, such as a resistor or any acceptable jumper, is bonded to the pads 110 and 112 to form an electrical connection between pads 110 and 112. The SMD 116 is embedded in the encapsulant 56. Hence, the SMD 116 is disposed on an opposite side of the front side redistribution structure 50 from the SMD 114. In this example, no SMD is bonded between pads 106 and 108 such that no closed-loop circuit is formed between the pads 106 and 108. Thus, the SMDs 114 and 116 may be an anti-fuse to create a closed-loop circuit to electrically couple, for example, portions of an integrated circuit on the integrated circuit die 42 and/or various metallization patterns 52 and/or 62 in the redistribution structures 50 and 60. In some embodiments, the SMDs 114 and 116 are low resistance resistors, such as having a resistance less than about 0.1 ohms, and more specifically, less than about 0.05 ohms. In other embodiments, such as discussed below, other components, such as a wire bond or other acceptable jumper, may be used as an anti-fuse. This illustrated embodiment shows multiple locations where an anti-fuse may be placed in the package 100.
Wire bonds 122, 124, and 126 are used in the place of SMDs 74, 114, and 116, respectively, as anti-fuses in
The exterior surfaces comprise pads 140, 142, 144, 146, and 148. The pads 140 may be for electrically and mechanically coupling external electrical connectors, such as connectors 78 and/or 82 discussed above. For example, the pads 140 may be for BGA balls. The pads 140, in these embodiments, encircle an anti-fuse area in which pads 142, 144, 146, and 148 are disposed. Pads 142, 144, 146, and 148 are used to connect or not connect a jumper, such as a SMD 150 or wire bond 152, to program the integrated circuit(s) on an integrated circuit die(s). In
The layouts in
A dielectric layer 204 is formed on the release layer 202. The bottom surface of the dielectric layer 204 may be in contact with the top surface of the release layer 202. In some embodiments, the dielectric layer 204 is formed of a polymer, such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric layer 204 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; or the like. The dielectric layer 204 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof.
Referring to
A photo resist 208 is formed and patterned on the seed layer 206. The photo resist 208 may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist 208 corresponds to a metallization pattern. The patterning forms openings through the photo resist 208 to expose the seed layer 206.
A conductive material 210 is formed in the openings of the photo resist 208 and on the exposed portions of the seed layer 206. The conductive material 210 may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material 210 may comprise a conductive material, such as a metal, like copper, titanium, tungsten, aluminum, or the like.
In
In
Referring to
A photo resist 218 is formed and patterned on the seed layer 216. The photo resist 218 may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist 218 corresponds to through vias. The patterning forms openings through the photo resist 218 to expose the seed layer 216.
A conductive material 220 is formed in the openings of the photo resist 218 and on the exposed portions of the seed layer 216. The conductive material 220 may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material 220 may comprise a conductive material, such as a metal, like copper, titanium, tungsten, aluminum, or the like.
In
In
SMDs 226 are connected between exposed portions, e.g., pads, of the metallization pattern 212. The SMDs 226 may be connected to the exposed portions of the metallization pattern 212 using, for example, a pick-and-place tool, and bonding the SMDs 226 to the exposed portions by metal-to-metal bonding, solder reflowing, or the like. In some embodiments, the SMDs 226 are low resistance resistors, such as having a resistance less than about 0.1 ohms, and more specifically, less than about 0.05 ohms. In other embodiments, other components, such as a wire bond or other acceptable jumper, may be used as an anti-fuse between the exposed portions, e.g., pads, of the metallization pattern 212. When a wire bond is used, any acceptable wire bonding technique may be used to form the wire bond on the exposed portions of the metallization pattern. One of ordinary skill in the art will readily understand other appropriate techniques for forming other jumpers.
In
In
In
A photo resist 240 is formed and patterned on the seed layer 238. The photo resist 240 may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist 240 corresponds to a metallization pattern. The patterning forms openings through the photo resist 240 to expose the seed layer 238.
A conductive material 242 is formed in the openings of the photo resist 240 and on the exposed portions of the seed layer 238. The conductive material 242 may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material 242 may comprise a conductive material, such as a metal, like copper, titanium, tungsten, aluminum, or the like.
In
In
In
External connectors 262, such as solder balls like ball grid array (BGA) balls, are formed on the under-metal 254, such as by using an appropriate ball drop process. In some embodiments, the external connectors 262 comprise solder, such as a Sn—Ag alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free or lead-containing.
In
In
In
External connectors 284, such as solder bumps, metal pillars, the like, or a combination such as metal pillars with solder thereon, are formed on the pads 278 and 280 of the metallization pattern 212, such as by using an appropriate bumping process, plating process, the like, or a combination thereof. In some embodiments, the external connectors 284 comprise solder, such as a Sn—Ag alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free or lead-containing.
The foregoing process illustrated in
Embodiments may have advantages. Programming a circuit may be simplified and more reliable using an anti-fuse external to an integrated circuit die. In some previous applications, a fuse may have been in an integrated circuit die and may have been programmed using electrical burn out or laser cutting. In those applications, a thickness of a fuse portion of a fuse may be large causing electrical burn out or laser cutting to be difficult and causing the fuse to not be blown after such an electrical burn out or laser cutting. In some embodiments, an anti-fuse is placed in a package, external to an integrated circuit die, to program the circuit. This obviates any need to blow a fuse. Further, there may be increased flexibility in placement of an anti-fuse(s) in some embodiments.
An embodiment is a package structure. The package structure includes an integrated circuit die, a redistribution structure, an anti-fuse, and external connectors. The integrated circuit die is embedded in an encapsulant. The redistribution structure is on the encapsulant and is electrically coupled to the integrated circuit die. The anti-fuse is external to the integrated circuit die and the redistribution structure. The anti-fuse is mechanically and electrically coupled to the redistribution structure. The external connectors are on the redistribution structure, and the redistribution structure is disposed between the external connectors and the encapsulant.
Another embodiment is a package structure. The package structure includes a die, an encapsulant, a redistribution structure, and an anti-fuse. The die comprises an integrated circuit, and die connectors are on an active side of the die and are electrically coupled to the integrated circuit. The encapsulant at least laterally encapsulates the die. The redistribution structure is on and adjoins the encapsulant. At least a portion of the redistribution structure is directly coupled to the die connectors. The anti-fuse is mechanically and electrically coupled to pads on an exterior side of the redistribution structure.
Another embodiment is a method. The method includes encapsulating an integrated circuit die in an encapsulant; forming a redistribution structure adjoining the encapsulant, the redistribution structure comprising pads; and mechanically attaching an anti-fuse to the pads.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Patent | Priority | Assignee | Title |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 14 2014 | SU, AN-JHIH | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 033556 | /0756 | |
Jul 14 2014 | CHEN, HSIEN-WEI | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 033556 | /0756 | |
Jul 17 2014 | Taiwan Semiconductor Manufacturing Company, Ltd. | (assignment on the face of the patent) | / |
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