A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.
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1. An integrated circuit, comprising:
an insulating layer having a planar top surface;
a first metal structure within the insulating layer;
wherein the insulating layer comprises a plurality of sub-layers;
wherein the first metal structure comprises a corresponding plurality of first sub-structures, each first sub-structure formed in one of the sub-layers and having a thickness equal to a thickness of the sub-layer within which it is formed, each first sub-structure having a width dimension and a length dimension;
wherein one of the width dimension or length dimension for the first sub-structures in the first metal structure is the same for all the first sub-structures; and
wherein the other of the width dimension or length dimension for the first sub-structures in the first metal structure is different for all the first sub-structures.
14. An integrated circuit, comprising:
a semiconductor substrate;
a first doped region within the semiconductor substrate;
a premetallization dielectric layer over the semiconductor substrate having a top surface;
a first metallization layer on the top surface of the premetallization dielectric layer;
a first metal contact extending from the first metallization layer to the first doped region;
wherein the premetallization dielectric layer comprises a plurality of sub-layers;
wherein the first metal contact comprises a corresponding plurality of first sub-contacts, each first sub-contact formed in one of the sub-layers, each first sub-contact having a width and a length, wherein widths of the first sub-contacts forming the first metal contact are all the same and wherein the lengths of the first sub-contacts forming the first metal contact are all different from each other.
34. An integrated circuit, comprising:
a semiconductor substrate;
a first doped region within the semiconductor substrate;
a second doped region within the semiconductor substrate;
a premetallization dielectric layer over the semiconductor substrate having a top surface;
a first metallization layer on the top surface of the premetallization dielectric layer;
a first metal contact extending from the first metallization layer to the first doped region;
a second metal contact extending from the first metallization layer to the second doped region;
wherein the premetallization dielectric layer comprises a plurality of sub-layers;
wherein the first metal contact comprises a corresponding plurality of first sub-contacts, each first sub-contact formed in one of the sub-layers, each first sub-contact having a width and a length, wherein widths of the first sub-contacts forming the first metal contact are all the same and wherein the lengths of the first sub-contacts forming the first metal contact are all different from each other and increase in length the further the first sub-contact is away from the first doped region; and
wherein the second metal contact comprises a corresponding plurality of second sub-contacts, each second sub-contact formed in one of the sub-layers, each second sub-contact having a width and a length, wherein widths of the second sub-contacts forming the first metal contact are all the same and wherein the lengths of the second sub-contacts forming the second metal contact are all different from each other and decrease in length the further the second sub-contact is away from the second doped region.
2. The integrated circuit of
3. The integrated circuit of
4. The integrated circuit of
5. The integrated circuit of
6. The integrated circuit of
a second metal structure within the same insulating layer;
wherein the second metal structure comprises a corresponding plurality of second sub-structures in direct contact with each other, each second sub-structure formed in one of the sub-layers and having a thickness equal to a thickness of the sub-layer within which it is formed, each second sub-structure having a width dimension and a length dimension;
wherein one of the width dimension or length dimension for the second sub-structures in the second metal structure is the same for all the second sub-structures; and
wherein the other of the width dimension or length dimension for the second sub-structures in the second metal structure is different for all the sub-structures.
7. The integrated circuit of
8. The integrated circuit of
wherein the other of the width dimension or length dimension for the first sub-structures in the first metal structure that is different progressively increases in size the further the first substructure is located from the planar top surface; and
wherein the other of the width dimension or length dimension for the second substructures in the second metal structure that is different progressively decreases in size the further the second sub-structure is located from the planar top surface.
9. The integrated circuit of
10. The integrated circuit of
11. The integrated circuit of
12. The integrated circuit of
13. The integrated circuit of
15. The integrated circuit of
16. The integrated circuit of
17. The integrated circuit of
18. The integrated circuit of
19. The integrated circuit of
20. The integrated circuit of
21. The integrated circuit of
22. The integrated circuit of
a second doped region within the semiconductor substrate;
a second metal contact extending from the first metallization layer to the second doped region;
wherein the second metal contact comprises a corresponding plurality of second sub-contacts, each second sub-contact formed in one of the sub-layers, each second sub-contact having a width and a length, wherein the lengths of the second sub-contacts forming the second metal contact are all different from each other.
23. The integrated circuit of
24. The integrated circuit of
a second doped region within the semiconductor substrate adjacent the first doped region;
an electrode formed above the second doped region;
a second metal contact extending from the first metallization layer to the electrode;
wherein the second metal contact comprises a corresponding plurality of second sub-contacts, each second sub-contact formed in one of the sub-layers, each second sub-contact having a width and a length, wherein the lengths of the second sub-contacts forming the second metal contact are all different from each other.
25. The integrated circuit of
26. The integrated circuit of
27. The integrated circuit of
29. The integrated circuit of
30. The integrated circuit of
31. The integrated circuit of
33. The integrated circuit of
35. The integrated circuit of
36. The integrated circuit of
37. The integrated circuit of
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The present invention relates to integrated circuits and, in particular, to the formation of metal-filled vias, trenches or contact openings in the metallization (M), premetallization dielectric (PMD) or interlevel dielectric (ILD) layers of an integrated circuit.
Reference is now made to
As feature sizes in integrated circuit devices continue to shrink and operational speed increases, there is a need to make a thicker ILD/PMD layer 46 so as to reduce capacitance between the first metallization layer M1 and the active region 20 as well as between the first metallization layer M1 and the gate electrode 40. The thicker ILD/PMD layer 46 and reduced feature size accordingly necessitates the use of high aspect ratio metal contacts 50 (i.e., contacts made in openings with a height/width ratio >>1, for example, ≧4). It is a challenge to provide such high aspect ratio contacts without incurring problems associated with open yield and increased contact resistance. There is accordingly a need in the art for an improved contact configuration for interconnecting the first metallization layer M1 to both the active region 20 and the gate electrode 40.
In addition, improved structures for the metal lines and metal vias in the metallization layers of integrated circuits are needed to ensure device reliability and improve signal performance through resistance adjustment.
In an embodiment, an integrated circuit comprises: an insulating layer having a planar top surface; a first metal structure within the insulating layer; wherein the insulating layer comprises a plurality of sub-layers; wherein the first metal structure comprises a corresponding plurality of first sub-structures, each first sub-structure formed in one of the sub-layers and having a thickness equal to a thickness of the sub-layer within which it is formed, each first sub-structure having a width dimension and a length dimension; wherein one of the width dimension or length dimension for the first sub-structures in the first metal structure is the same for all the first sub-structures; and wherein the other of the width dimension or length dimension for the first sub-structures in the first metal structure is different for all the first sub-structures.
In an embodiment, an integrated circuit comprises: a semiconductor substrate; a first doped region within the semiconductor substrate; a premetallization dielectric layer over the semiconductor substrate having a top surface; a first metallization layer on the top surface of the premetallization dielectric layer; a first metal contact extending from the first metallization layer to the first doped region; wherein the premetallization dielectric layer comprises a plurality of sub-layers; wherein the first metal contact comprises a corresponding plurality of first sub-contacts, each first sub-contact formed in one of the sub-layers, each first sub-contact having a width and a length, wherein the lengths of the first sub-contacts forming the first metal contact are all different from each other.
In an embodiment, an integrated circuit comprises: a semiconductor substrate; a first doped region within the semiconductor substrate; a second doped region within the semiconductor substrate; a premetallization dielectric layer over the semiconductor substrate having a top surface; a first metallization layer on the top surface of the premetallization dielectric layer; a first metal contact extending from the first metallization layer to the first doped region; a second metal contact extending from the first metallization layer to the second doped region; wherein the premetallization dielectric layer comprises a plurality of sub-layers; wherein the first metal contact comprises a corresponding plurality of first sub-contacts, each first sub-contact formed in one of the sub-layers, each first sub-contact having a width and a length, wherein the lengths of the first sub-contacts forming the first metal contact are all different from each other and increase in length the further the first sub-contact is away from the first doped region; and wherein the second metal contact comprises a corresponding plurality of second sub-contacts, each second sub-contact formed in one of the sub-layers, each second sub-contact having a width and a length, wherein the lengths of the second sub-contacts forming the second metal contact are all different from each other and decrease in length the further the second sub-contact is away from the second doped region.
For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
The illustrations provided are not necessarily drawn to scale.
Reference is now made to
A substrate 112 supports the MOSFET device 110. In this example, the substrate is of the silicon-on-insulator substrate 112 type which includes a substrate layer 114, a buried oxide (BOX) layer 116 and a semiconductor layer 118 (although it will be understood that the features disclosed herein are equally applicable to integrated circuits fabrication with a bulk or other semiconductor substrate as support). An active region 120 for the transistor device is delimited by a peripherally surrounding shallow trench isolation 122 that penetrates through the layer 118. Within the active region 120, the layer 118 is divided into a channel region 130 which has been doped with a first conductivity type dopant, a source region 132 (adjacent the channel region 130 on one side) which has been doped with a second conductivity type dopant, and a drain region 134 (adjacent the channel region 130 on an opposite side from the source region 132) which has also been doped with the second conductivity type dopant. Where the MOSFET 110 device is of the p-channel type, the first conductivity type dopant is p-type and the second conductivity type is n-type. Conversely, where the MOSFET device is of the n-channel type, the first conductivity type dopant is n-type and the second conductivity type is p-type. A gate stack 136 is provided above the channel region 130. This gate stack 136 typically comprises a gate dielectric 138, a polysilicon material gate electrode 140 and sidewall spacers 142 made of an insulating material such as silicon nitride (SiN) deposited on the sides of the gate dielectric 138 and polysilicon material gate electrode 140. An interlevel dielectric (ILD) or pre-metallization dielectric (PMD) layer 146 is provided above the substrate and the gate stack. A top surface 148 of the layer 146 is processed with a chemical-mechanical polishing (CMP) process to define a planar surface.
The ILD/PMD layer 146 comprises a plurality of sub-layers including: a first sub-layer 146(1), a second sub-layer 146(2) and a third sub-layer 146(3). Although three sub-layers are shown, it will be understood that layer 146 may comprise more sub-layers than three if demanded by the application and the geometry of the device. The first sub-layer 146(1) has a thickness which is generally the same as a thickness of the gate stack 136. This is not a requirement, but in many instances the sub-layer 146(1) is deposited and chemically-mechanically polished (CMP) stopping at the top of the gate stack 136. This operation may be performed in connection with implementation of replacement gate processes as known in the art. The second and third sub-layers 146(2) and 146(3) may have thicknesses as desired, which may be thicker, thinner or generally equal to the thickness of the first sub-layer 146(1). These additional sub-layers beyond sub-layer 146(1) are provided to increase the thickness of the layer 146 to a desired thickness separating the substrate from back-end-of-line (BEOL) structures such as metallization layers.
A set of metal contacts 150, typically formed of tungsten, extend from the top surface 148 through the ILD/PMD layer 146 to make electrical contact with each of the source region 132 and drain region 134. A metal contact 152, typically formed of tungsten, extends from the top surface 148 through the ILD/PMD layer 146 to make electrical contact with the gate electrode 140.
With respect to the contacts 150 for the source region 132 and drain region 134, a first sub-contact 150(1) is provided in the first sub-layer 146(1). The first sub-contact 150(1) has a thickness equal to the thickness of the first sub-layer 146(1). The first sub-contact 150(1) has a first width as shown in
Additionally, a second sub-contact 150(2) is provided in the second sub-layer 146(2). The second sub-contact 150(2) has a thickness equal to the thickness of the second sub-layer 146(2). The second sub-contact 150(2) has a second width as shown in
Additionally, a third sub-contact 150(3) is provided in the third sub-layer 146(3). The third sub-contact 150(3) has a thickness equal to the thickness of the third sub-layer 146(3). The third sub-contact 150(3) has a third width as shown in
The first, second and third sub-contacts 150(1)-150(3) are in series electrical connection with each other to define the contact 150 which extends from the top surface 148 through the ILD/PMD layer 146 to make physical and electrical contact with the source region 132 or drain region 134. It will be noted that the lengths of the sub-contacts 150 progressively decrease in size the further the sub-contact is from the planar surface 148.
With respect to the contact 152 for the gate electrode 140, a first sub-contact 152(1) is provided in the second sub-layer 146(2). The first sub-contact 152(1) has a thickness equal to the thickness of the second sub-layer 146(2). The first sub-contact 152(1) has a first width as shown in
Additionally, a second sub-contact 152(2) is provided in the third sub-layer 146(3). The second sub-contact 152(2) has a thickness equal to the thickness of the third sub-layer 146(3). The second sub-contact 152(2) has a second width as shown in
The first and second sub-contacts 152(1)-152(2) are in series electrical connection with each other to define the contact 150 which extends from the top surface 148 through the ILD/PMD layer 146 to make physical and electrical contact with the gate electrode 140. It will be noted that the lengths of the sub-contacts 152 progressively increase in size the further the sub-contact is from the planar surface 148.
In an embodiment, a volume of conductive material for the contact 150 (to either the source region or drain region) is substantially equal to a volume of conductive material for the contact 152 (to the gate region). In this context, the volumes of conductive material are considered to be substantially equal if they are within 5% of each other. To accomplish this design goal, the layout designer selects the widths and lengths of the sub-contacts for each of the sub-layers.
A first metallization layer M1 is then provided at the top surface 148 of the ILD/PMD layer 146, with the first metallization layer M1 comprising metal lines 154 in contact with the contacts 150 and 152 and surrounded by a planarized dielectric material layer 156. Additional metallization layers (not shown) may be provided above the first metallization layer M1 in a manner well known in the art. The metallization layers may, for example, be formed using well known damascene processes. The metal lines 154 of the metallization layer M1 are configured to make physical and electrical contact to a plurality of contacts such as, for example, shown in
In an embodiment utilizing a replacement metal gate technology, the gate electrode 140 may instead comprise a metal fill material 140′ as shown in
In this configuration, with respect to the contacts 152 for the gate electrode, a first sub-contact 152(1) comprising the replacement metal gate 140′ is provided in the first sub-layer 146(1). The first sub-contact 150(1) has a thickness generally equal to the thickness of the first sub-layer 146(1) (taking into account other structures of the gate stack such as the gate dielectric and work function metal, for example). The first sub-contact 150(1) has a first width as shown in
Additionally, a second sub-contact 152(2) is provided in the second sub-layer 146(2). The second sub-contact 152(2) has a thickness equal to the thickness of the second sub-layer 146(2). The second sub-contact 152(2) has a second width as shown in
Additionally, a third sub-contact 152(3) is provided in the third sub-layer 146(3). The third sub-contact 152(3) has a thickness equal to the thickness of the third sub-layer 146(3). The third sub-contact 152(3) has a third width as shown in
Although the contacts 150 and 152 are shown in
While rectangular prism structures are shown in
It will be noted that a volume of conductive material in the first and second contacts of the implementations shown in
In an embodiment, the first sub-contact 150(1) and the first sub-contact 152(1) in any of the disclosed implementations may be made of a first metal material such as, for example, tungsten. The remaining sub-contacts, such as the second and third sub-contacts 150(2)-150(3) and second and third sub-contacts 152(2) and 152(3) may be made of the same first material or, in an alternative implementation, made of a second metal material such as, for example, copper. In this regard, the metal material used for the metal lines 154 of the metallization layer M1 may also comprise, for example, copper. This use of the first metal material (tungsten) is consistent with the use of tungsten material for contacts and replacement metal gate structures at the first sub-layer, while the use of the second material (copper) for the sub-contacts in the remaining sub-layers supports the known advantages of copper use for wiring lines in integrated circuit devices. Aluminum presents an alternative second material choice. Each of the sub-contacts may further include a barrier liner (for example, made of titanium nitride (TiN)) to protect against diffusion of the metal species used for the sub-contact into the sub-layers of the ILD/PMD layer 146.
Conventional deposit, pattern and fill process steps may be used to produce the sub-layers and sub-contacts. For example, a mask defining the location of openings for the sub-contacts may be produced on top of a given sub-layer of the ILD/PMD layer 146. An opening is then formed in that given sub-layer using the mask and a reactive ion etch (RIE) is performed through the mask. The etch should extend completely through the given sub-layer to form the opening. An atomic layer deposition (ALD) technique is then used to deposit the metal barrier liner (such as TiN) on the walls of the opening, and a metal filling process (such as thermal chemical vapor deposition (CVD)) is then used to fill the opening with the metal material of the sub-contact (such as tungsten or copper). A chemical-mechanical polishing (CMP) process is then performed to remove excess metal barrier and fill material, with the CMP stopping at the top of the given sub-layer of the ILD/PMD layer 146. A chemical vapor deposition (CVD) process is then performed to deposit the next sub-layer of the ILD/PMD layer 146. The previous steps are then repeated to form the sub-contact in that next sub-layer. The process may be repeated as many times as are necessary to define the thickness of the ILD/PMD layer 146 from multiple deposited, patterned and filled sub-layers with sub-contacts. For example, the ILD/PMD layer 146 may have a thickness of 120-140 nm, with each sub-layer having a thickness of between 30-100 nm. The minimum width of the sub-contacts is set by the minimum dimension of the lithographic process used for fabrication. Conventional back-end-of-line (BEOL) processes are then performed to provide the necessary metallization levels.
Although specific reference is made herein to a planar MOSFET device and the formation of contacts for source, drain and gate, it will be understood that the techniques and structures for contacts described herein are applicable to an integrated circuit device including, without limitation, bipolar transistor devices, FinFET devices, diode devices, planar transistor devices with source and drain regions formed from UTBB or ETSOI substrates, and the like.
The structures described above for use as contacts in the ILD/PMD layer 146 may be advantageously extended for use in metallization layers. Reference is accordingly made to
The dielectric material layer 156 comprises a plurality of sub-layers including: a first sub-layer 156(1), a second sub-layer 156(2) and a third sub-layer 156(3). Although three sub-layers are shown, it will be understood that layer 156 may comprise more sub-layers than three if demanded by the application and the geometry of the device. The first, second and third sub-layers 156(1), 156(2) and 156(3) may have different or substantially same thicknesses as desired by the application and routing of wiring.
Although disclosed in the context of the M1 metallization layer, it will be understood that the sub-layers are equally applicable to any of the included further metallization layers (M2-Mn) required by the integrated circuit.
With respect to the metal line 154(1), a first sub-line 164(1) is provided in the first sub-layer 156(1). The first sub-line 164(1) has a thickness equal to the thickness of the first sub-layer 156(1). The first sub-line 164(1) has a first width and a first length.
Additionally, a second sub-line 164(2) is provided in the second sub-layer 156(2). The second sub-line 164(2) has a thickness equal to the thickness of the second sub-layer 156(2). The second sub-line 164(2) has a second width which is different from the first width and a second length. The second width may, for example, be less than the first width and the second length may be equal to the first length.
Additionally, a third sub-line 164(3) is provided in the third sub-layer 156(3). The third sub-line 164(3) has a thickness equal to the thickness of the third sub-layer 156(3). The third sub-line 164(3) has a third width different from the first and second widths and a third length. The third width may, for example, be less than the first and second widths and the third length may be equal to the second length.
The first, second and third sub-lines 164(1)-164(3) are in series electrical connection with each other to define the first line 154(1) which extends from the top surface 158 through the dielectric layer 156 to make physical and electrical contact with the contact 150 for the source region 132. It will be noted that the widths of the sub-lines 164 progressively decrease in size the further the sub-line is from the planar surface 148.
With respect to the metal line 154(2), a first sub-line 164(1) is provided in the first sub-layer 156(1). The first sub-line 164(1) has a thickness equal to the thickness of the first sub-layer 156(1). The first sub-line 164(1) has a first width and a first length.
Additionally, a second sub-line 164(2) is provided in the second sub-layer 156(2). The second sub-line 164(2) has a thickness equal to the thickness of the second sub-layer 156(2). The second sub-line 164(2) has a second width which is different from the first width and a second length. The second width may, for example, greater than the first width and the second length may be equal to the first length.
Additionally, a third sub-line 164(3) is provided in the third sub-layer 156(3). The third sub-line 164(3) has a thickness equal to the thickness of the third sub-layer 156(3). The third sub-line 164(3) has a third width different from the first and second widths and a third length. The third width may, for example, be greater than the first and second widths and the third length may be equal to the second length.
The first, second and third sub-lines 164(1)-164(3) are in series electrical connection with each other to define the second line 154(2) which extends from the top surface 158 through the dielectric layer 156 to make physical and electrical contact with the contact 150 for the drain region 134. It will be noted that the widths of the sub-lines 164 progressively increase in size the further the sub-contact is from the planar surface 148.
In an embodiment, a volume of conductive material for the first line 154(1) is substantially equal to a volume of conductive material for the second line 154(2). In this context, the volumes of conductive material are considered to be substantially equal if they are within 5% of each other. To accomplish this design goal, the layout designer selects the widths and lengths of the sub-lines for each of the sub-layers.
Additionally, the first and second sub-lines are positioned immediately adjacent each other without any intervening metal structure within said same dielectric layer 156. In this configuration, a first spacing distance in a direction parallel to the planar surfaces between first and second sub-lines on different sub-layers is less than a second spacing distance the direction parallel to the planar surfaces between first and second sub-lines located on different sub-layers. Indeed, this first spacing distance may be negative in that some overlap between sub-lines on different sub-layers in the vertical direction perpendicular to the planar surfaces is provided. This overlap is generally indicated at reference 168.
Although the lines 154(1) and 154(2) are shown in
Each of the sub-lines may further include a barrier liner (for example, made of titanium nitride (TiN)) to protect against diffusion of the metal species used for the sub-line into the sub-layers of the dielectric material layer 156.
Conventional deposit, pattern and fill process steps may be used to produce the sub-layers and sub-lines. For example, a mask defining the location of openings for the sub-lines may be produced on top of a given sub-layer of the dielectric material layer 156. An opening is then formed in that given sub-layer using the mask and a reactive ion etch (RIE) is performed through the mask. The etch should extend completely through the given sub-layer to form the opening. An atomic layer deposition (ALD) technique is then used to deposit the metal barrier liner (such as TiN) on the walls of the opening, and a metal filling process (such as thermal chemical vapor deposition (CVD)) is then used to fill the opening with the metal material of the sub-line (such as copper or aluminum). A chemical-mechanical polishing (CMP) process is then performed to remove excess metal barrier and fill material, with the CMP stopping at the top of the given sub-layer of the dielectric material layer 156. A chemical vapor deposition (CVD) process is then performed to deposit the next sub-layer of the dielectric material layer 156. The previous steps are then repeated to form the sub-line in that next sub-layer. The process may be repeated as many times as are necessary to define the thickness of the metallization layer from multiple deposited, patterned and filled sub-layers with sub-lines. For example, the metallization layer may have a thickness of 48 to 120 nm, with each sub-layer having a thickness of between 16 and 40 nm. The minimum dimension of the sub-lines is set by the minimum dimension of the lithographic process used for fabrication.
The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.
Patent | Priority | Assignee | Title |
10607947, | Dec 02 2016 | GLOBALFOUNDRIES U S INC | Semiconductor device comprising a die seal including long via lines |
Patent | Priority | Assignee | Title |
20040251549, | |||
20090121321, | |||
20120149186, |
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