A method of forming a wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.
|
8. A method of forming enlarged diameter vias that intersect underlying metal lines, the method comprising:
forming an inter-layer dielectric (ild) on top of the underlying metal lines, wherein the ild includes a bi-layer that includes two different ultra-low-k (ULK) dielectric materials;
patterning a surface of the ild with enlarged diameter vias having a characteristic diameter that exceeds a width of the underlying metal lines;
etching the enlarged diameter vias to an enlarged diameter via depth that extends at least to a lower surface of the underlying metal lines; and
filling the enlarged diameter vias with a metal liner and a bulk metal.
9. A method of forming enlarged diameter vias that intersect underlying metal lines, the method comprising:
forming an inter-layer dielectric (ild) on top of the underlying metal lines;
forming a tapered air gap in the ild, the tapered air gap extending downward to a lower surface of the underlying metal lines;
patterning a surface of the ild with enlarged diameter vias having a characteristic diameter that exceeds a width of the underlying metal lines;
etching the enlarged diameter vias to an enlarged diameter via depth that extends at least to the lower surface of the underlying metal lines; and
filling the enlarged diameter vias with a metal liner and a bulk metal.
1. A method of forming enlarged diameter vias that intersect underlying metal lines, the method comprising:
forming an inter-layer dielectric (ild) on top of the underlying metal lines;
patterning a surface of the ild with enlarged diameter vias having a characteristic diameter that exceeds a width of the underlying metal lines;
etching the enlarged diameter vias to an enlarged diameter via depth that extends at least to a lower surface of the underlying metal lines;
extending the enlarged diameter vias below the lower surface of the underlying metal lines and removing ild material underneath the underlying metal lines to create all-around vias; and
filling the all-round vias with a metal liner and a bulk metal.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
|
Technical Field
The present disclosure generally relates to high speed integrated circuits, and in particular, to the fabrication of interconnect structures using a self-aligned dual damascene process.
Description of the Related Art
As integrated circuit technology advances, building metal interconnect structures that are used to wire transistors together becomes more and more challenging. Metal lines can assume a variety of different shapes, from straight wires to cells made up of intertwined C-shapes. Regardless of their shapes, design rules for metal lines are typically based on scaling a pitch dimension that assumes a regular pattern of equal line widths and spacings between the metal lines at each metal layer. Metal line widths are generally expected to shrink with every new process generation to further improve integrated circuit performance.
Depending on the type of process integration scheme used, vias connecting stacked metal lines vertically to one another are constrained to be smaller than the metal lines in order for the via footprint to be surrounded by metal. Such a constraint exists, for example, when forming vias according to a self-aligned dual damascene process that avoids a separate via lithography step. Thus, as the metal line design widths shrink with each process generation, the self-aligned vias shrink as well. However, smaller vias incur higher via resistance, causing RC delays to worsen. In addition, smaller via footprints cause the via aspect ratio, i.e., the ratio of height to width, to increase, making the vias taller and narrower, and therefore more difficult to fill with metal. Incomplete via fill in turn degrades reliability by causing open circuit failures, for example. Thus, for multiple reasons, it is advantageous for via footprints to remain large, while metal lines continue to shrink with each technology generation.
An interconnect structure having wavy metal lines allows via footprints to exceed the nominal width of metal line portions connecting them. In one embodiment, the resulting metal line profile shape resembles a bicycle chain. In another embodiment, the metal line resembles a linear series of T-shaped unit cells, in which the width of the metal line alternates between a narrow value, an intermediate value, and a wide value. The wide value corresponds to a large via landing pad for vias forming an electrical connection to the next highest metal layer. To achieve greater lateral packing density, adjacent wavy metal lines can be staggered so that the via landing pads on one metal line are next to the narrow metal connecting portions of neighboring metal lines. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.
A wavy line interconnect structure can be formed using a dual damascene process in which vias are self-aligned without the need for a dedicated lithography mask. Instead, metal line trenches are lined with a sacrificial layer that completely fills the narrow spaces while underfilling the wide spaces that correspond to via locations. The sacrificial layer thus acts as a via hard mask, allowing etching of the underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger footprint provides low via resistance.
One way to pattern wavy metal lines using conventional optical lithography uses a mask cell design that includes a series of rectangular opaque features diagonally offset from one another along an axis. Via landing pads are then added at one end of the mask cell by placing two rectangular features adjacent to one another. The method disclosed takes advantage of the shortcomings of optical lithography to achieve the desired wavy line pattern by anticipating diffraction errors that will occur during exposure of the rectangular features. Such a technique is generally known in the art as optical proximity correction (OPC). Typically, OPC is used to produce square corners where the standard lithography tends to round off the corners of a circuit pattern. In this case, however, the rounding effect is intentional. During the patterning process, corners of the rectangular features will transfer to the photoresist and the metal trench as rounded features. Meanwhile, the offset rectangular features, instead of remaining distinct, will join together to approximate the desired undulating wavy line shape. In similar fashion, each rectangle pair will transfer to the metal trench layer as a combined shape, forming a single large landing pad to accommodate the vias.
According to one embodiment, large vias are designed to land on narrow portions of the wavy metal line instead of, or in addition to, vias that land on the designated landing pads. Normally, when a large via footprint exceeds the size of an underlying metal landing pad, the electrical contact area at the interface is reduced, thereby causing an increase in via resistance. However, if the large via is formed so that the via depth extends to the bottom of the metal line instead of stopping on the top surface of the metal line, an enlarged diameter via is formed that operates with significantly less via resistance. Furthermore, the enlarged diameter via need not be centered on the metal line, but can be aligned asymmetrically with respect to the metal line.
According to one embodiment, an interconnect structure featuring enlarged diameter vias includes a two-component inter-layer dielectric. The two-component ILD includes a bottom dielectric material adjacent to the metal line, and a top dielectric material adjacent to the via. Use of two different materials allows greater flexibility in the circuit design of the overall interconnect structure.
According to one embodiment, adjacent enlarged diameter vias are effectively encapsulated by substituting a silicon carbide-based insulator, e.g., SiC or SiCOH for the low-k ILD materials. Use of such a SiC-based insulator offers additional protection against dielectric breakdown. Forming an air gap within the SiC-based ILD then reduces capacitance between the adjacent enlarged diameter vias to compensate for the increased capacitance of the encapsulating material.
According to one embodiment, an enlarged diameter via surrounds the underlying metal line on all four sides, further increasing the electrical contact area to achieve an additional performance benefit.
In the drawings, identical reference numbers identify similar elements. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale.
In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure.
Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”
Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure.
Reference throughout the specification to integrated circuits is generally intended to include integrated circuit components built on semiconducting substrates, whether or not the components are coupled together into a circuit or able to be interconnected. Throughout the specification, the term “layer” is used in its broadest sense to include a thin film, a cap, or the like and one layer may be composed of multiple sub-layers.
Reference throughout the specification to conventional thin film deposition techniques for depositing silicon nitride, silicon dioxide, metals, or similar materials include such processes as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electro-less plating, and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. For example, in some circumstances, a description that references CVD may alternatively be done using PVD, or a description that specifies electroplating may alternatively be accomplished using electro-less plating. Furthermore, reference to conventional techniques of thin film formation may include growing a film in situ. For example, in some embodiments, controlled growth of an oxide to a desired thickness can be achieved by exposing a silicon surface to oxygen gas or to moisture in a heated chamber.
Reference throughout the specification to conventional photolithography techniques, known in the art of semiconductor fabrication for patterning various thin films, includes a spin-expose-develop process sequence typically followed by an etch process. Alternatively or additionally, photoresist can be used to pattern a hard mask (e.g., a silicon nitride hard mask), which, in turn, can be used to pattern an underlying film.
Reference throughout the specification to conventional etching techniques known in the art of semiconductor fabrication for selective removal of polysilicon, silicon nitride, silicon dioxide, metals, photoresist, polyimide, or similar materials includes such processes as wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical-mechanical planarization (CMP) and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. In some instances, two such techniques may be interchangeable. For example, stripping photoresist may entail immersing a sample in a wet chemical bath or, alternatively, spraying wet chemicals directly onto the sample.
Specific embodiments are described herein with reference to interconnect structures that have been produced; however, the present disclosure and the reference to certain materials, dimensions, and the details and ordering of processing steps are exemplary and should not be limited to those shown.
Turning now to the Figures,
With reference to
A second exemplary embodiment of such a wavy metal line design is shown in
The wavy metal line structures 120 are achieved by approximating the portions of varying widths using rectangular mask features in the wavy line mask design 110. For example, the wavy line mask design 110 can be implemented by forming rectangular opaque features 112 and 114 on a reticle made of chrome on a glass plate 113. When the reticle is exposed to light in an optical lithography stepper or scanner, the light is blocked by the rectangular opaque features 112 and 114. However, diffraction effects cause the pattern of rectangles to become blurred at the target surface, thereby producing the wavy-line patterns shown in
The optical lithography wavy line mask design 110 (
Intentional manipulation of mask features to compensate for shortcomings in lithographic capability is well known in the art of photolithography as Optical Proximity Correction (OPC). OPC is often used to pattern square corners that would otherwise become rounded by diffraction effects. In the present case, however, the rounded features forming the wavy metal line structures 120 are intentionally created by leveraging distortion that occurs in the lithography process, as opposed to correcting for the distortion. While it is true that conventional metal lines are not all as uniform and straight as those shown in
If it is desired to produce a wavy line pattern that is oriented horizontally or vertically instead of diagonally, simply rearranging the rectangular opaque features 112 along a horizontal or vertical axis instead of along the oblique axis 132 may not result in the desired wavy line pattern. One way to change the wavy line orientation is to rotate the wavy line mask design 110 to produce, for example, a vertical wavy line mask design 110A as shown in
At 152, wavy trenches are formed in a dielectric block.
At 156, large self-aligned vias are formed in the dielectric block, extending away from the wavy trenches.
At 158, the wavy trenches and the large self-aligned vias are filled with metal in the same process step.
At 160, photoresist is applied to the thick inter-layer dielectric (ILD) block 157. Applying the photoresist entails first applying an optical planarization layer (OPL) 159, followed by an anti-reflection coating (ARC) 161, and finally the actual photoresist 163. The OPL 159 is used to fine-tune planarization of the surface of the dielectric block 157 prior to exposure, in order to reduce distortion of the pattern. The OPL 159 is made of, for example, a spin-on glass (SOG), as is known in the art.
At 162, the photoresist 163 is patterned by exposure to light through a mask fabricated according to the wavy line mask design 110, followed by treatment with a developer that removes portions of the photoresist 163.
At 164, a wavy line trench 166 is etched in the dielectric block 157 down to a trench depth 167. The wavy line trench 166 includes a wide portion of width D where a large via 169 will be formed, as shown in
At 170, a sacrificial layer 171 is deposited into the wavy line trench 166. In one embodiment, the sacrificial layer 171 is made of a material such as polysilicon, low-temperature silicon dioxide, or SiN. The sacrificial layer 171 overfills the narrow portion of the trench (d) to a narrow portion thickness 172 having a notch 178 therein, while conformally underfilling the wide portion of the trench (D) to a wide portion thickness 175. Thus, as shown in
The via width 176 is much greater than the narrow portion, d, of the metal line, which eases formation of the overall interconnect structure. The significance of the independence of the via width from the nominal metal line width d is that a path is cleared for the nominal metal line width in future technology generations to shrink without causing via failures. The metal line widths can continue getting smaller and smaller with each technology generation while the via size remains the same. The narrow portion thickness 172 is larger than d/2, but smaller than D/2. By using the sacrificial layer 171 as a hard mask, a via lithography step is avoided. Via formation without the need for a separate mask layer is referred to by those skilled in the art as a self-aligned via.
In another embodiment, the sacrificial layer 171 is made of a direct self-aligned (DSA) polymer material. A DSA polymer sacrificial layer 171 fills the narrow portions (d) of the wavy line trench so that the narrow portion thickness 172 is negligible. Likewise, the DSA polymer sacrificial layer 171 deposits on the sidewalls of the wide portions (D) to form a hard mask having a negligible wide portion thickness 175. Consequently, use of the DSA polymer as the sacrificial layer 171 simplifies the etch process, as is shown below.
At 180, the sacrificial layer 171 is etched to expose a via landing pad 181 at the surface of the underlying bulk metal 153. A first anisotropic etch step removes the sacrificial layer 171 from the bottom of the wavy line trench 166, down to the trench depth 167. If a DSA polymer is used as the sacrificial layer 171, the first anisotropic etch step is not needed because the bottom of the trench is already exposed.
At 182, a second anisotropic etch continues removing dielectric material in a downward direction to the underlying three-metal layer, creating the large via 169. Finally, a third etch step removes the cap layer 155 to expose the bulk metal 153, as shown in
At 190, the sacrificial layer 171 is removed using an etch chemistry that has a high selectivity to the dielectric block 157. For example, if the sacrificial layer 171 is SiN and the dielectric 157 is silicon dioxide, the sacrificial layer 171 can be removed using a phosphoric acid dip.
At 192, the wavy line trench 166 and the large via 169 are filled with metal. The metal fill process includes first depositing a metal liner 195, e.g., titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), cobalt (Co), rubidium (Ru), and combinations thereof; followed by deposition of a bulk metal 197, e.g., aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), nickel silicide (NiSi), cobalt silicide (CoSi), and combinations thereof, wherein combinations include metal laminates, alloys, and the like.
At 194, a chemical mechanical planarization (CMP) step is performed to planarize the metal liner 195 and bulk metal 197 to the height of the dielectric block 157.
The resulting metal lines shown in
With reference to
In the embodiment shown in
The tapered shape of the air gaps 228 provides greater structural stability than is achieved using materials that incorporate air pockets in a more random arrangement. Advantages of such tapered air gaps 228 are described in greater detail in U.S. patent application Ser. No. 14/098,286 entitled, “Advanced Interconnect with Air Gap” and Ser. No. 14/098,346 entitled, “Trench Interconnect Having Reduced Fringe Capacitance”. The air gaps 228 have a maximum width in the range of about 10-50 nm with a target width of about 20 nm. In one embodiment, the tapered air gaps 228 extend downward to the lower surface 214 of the underlying metal lines 205.
In
The techniques presented herein are generic and can be used at any metal layer, to ease constraints on via formation, thus supporting metal structures having a variety of different line widths. Without the benefit of the structures and processes described herein, via aspect ratios would continue to increase as the nominal metal line width shrinks with each new technology generation. Thus, severing the dependence of via dimensions on metal line widths has important advantages and implications for future generations of integrated circuit development.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
It will be appreciated that, although specific embodiments of the present disclosure are described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not limited except as by the appended claims.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Radens, Carl, Clevenger, Lawrence A., Zhang, John H., Sutton, Akil K., Wise, Richard Stephen, Xu, Yiheng, Saulnier, Nicole A., Spooner, Terry Allen
Patent | Priority | Assignee | Title |
10515894, | Jun 30 2016 | International Business Machines Corporation | Enhanced self-alignment of vias for a semiconductor device |
11075161, | Jun 13 2019 | International Business Machines Corporation | Large via buffer |
Patent | Priority | Assignee | Title |
4125854, | Dec 02 1976 | SGS-Thomson Microelectronics, Inc | Symmetrical cell layout for static RAM |
5840624, | Mar 15 1996 | Taiwan Semiconductor Manufacturing Company, Ltd | Reduction of via over etching for borderless contacts |
7056823, | Mar 02 2000 | Round Rock Research, LLC | Backend metallization method and device obtained therefrom |
9076729, | Mar 13 2013 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming interconnection structure having notches for semiconductor device |
9214429, | Dec 05 2013 | STMicroelectronics, Inc.; International Business Machines Corporation | Trench interconnect having reduced fringe capacitance |
20060063372, | |||
20100327445, | |||
20150162277, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jun 16 2014 | ZHANG, JOHN H | STMicroelectronics, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 038435 | /0928 | |
May 02 2016 | International Business Machines Corporation | (assignment on the face of the patent) | / | |||
May 02 2016 | STMicroelectronics, Inc. | (assignment on the face of the patent) | / | |||
Nov 15 2016 | WISE, RICHARD STEPHEN | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041171 | /0810 | |
Nov 28 2016 | SAULNIER, NICOLE A | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041171 | /0810 | |
Nov 30 2016 | SUTTON, AKIL K | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041171 | /0810 | |
Dec 01 2016 | XU, YIHENG | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041171 | /0810 | |
Dec 07 2016 | SPOONER, TERRY ALLEN | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041171 | /0810 | |
Dec 14 2016 | CLEVENGER, LAWRENCE A | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041171 | /0810 | |
Jan 27 2017 | RADENS, CARL | International Business Machines Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041171 | /0810 |
Date | Maintenance Fee Events |
Jan 11 2021 | REM: Maintenance Fee Reminder Mailed. |
Jun 28 2021 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
May 23 2020 | 4 years fee payment window open |
Nov 23 2020 | 6 months grace period start (w surcharge) |
May 23 2021 | patent expiry (for year 4) |
May 23 2023 | 2 years to revive unintentionally abandoned end. (for year 4) |
May 23 2024 | 8 years fee payment window open |
Nov 23 2024 | 6 months grace period start (w surcharge) |
May 23 2025 | patent expiry (for year 8) |
May 23 2027 | 2 years to revive unintentionally abandoned end. (for year 8) |
May 23 2028 | 12 years fee payment window open |
Nov 23 2028 | 6 months grace period start (w surcharge) |
May 23 2029 | patent expiry (for year 12) |
May 23 2031 | 2 years to revive unintentionally abandoned end. (for year 12) |