A method for determining an optimized write pattern for low write error rate operation of a spin torque magnetic random access memory. The method provides a way to optimize the write error rate without affecting the memory speed. The method comprises one or more write pulses. The pulses may be independent in amplitude, duration and shape. Various exemplary embodiments adjust the write pattern based on the memory operating conditions, for example, operating temperature.
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8. A method of writing to and reading from a memory cell in a memory, comprising:
writing data into the memory cell by applying a write pulse pattern to the memory cell, wherein the write pulse pattern consists essentially of:
a first write pulse having a first amplitude and a first pulse duration; and
a second write pulse having the first amplitude and the first pulse duration, wherein the first write pulse and the second write pulse are consecutive write pulses separated by a delay period without an intervening read operation; and
after writing data to the memory cell, reading the data from the memory cell, wherein reading the data includes:
detecting a resistance of the memory cell; and
determining the data stored in the memory cell based on the resistance detected.
1. A method of writing to a magnetoresistive memory cell in a magnetic random access memory, wherein data is stored in a magnetic state of the magnetoresistive memory cell based on a magnetization vector of a free layer relative to a magnetization vector of a fixed layer, the method comprising:
applying a write pulse pattern to the magnetoresistive memory cell to write data into the magnetoresistive memory cell by setting the magnetic state of the magnetoresistive memory cell, the write pulse pattern consists essentially of:
a first write pulse having a first amplitude and a first pulse duration;
a second write pulse having the first amplitude and the first pulse duration; and
wherein the first write pulse and the second write pulse are consecutive write pulses separated by a delay period without an intervening read operation.
16. A method of writing to a magnetoresistive memory cell in a magnetic random access memory, wherein data is stored in a magnetic state of the magnetoresistive memory cell based on a magnetization vector of a free layer relative to a magnetization vector of a fixed layer, the method comprising:
applying a write pulse pattern to the magnetoresistive memory cell in the random access memory to write data into the magnetoresistive memory cell by setting the magnetic state of the magnetoresistive memory cell, the write pulse pattern consists essentially of a plurality of consecutive write pulses, the plurality of consecutive write pulses consisting essentially of write pulses each having a first amplitude and a first pulse duration;
wherein each consecutive write pulse in the plurality of consecutive write pulses is separated from a previous write pulse in the plurality of consecutive write pulses by a first delay period without an intervening read operation.
2. The method of
3. The method of
detecting an operating condition of the magnetic random access memory; and
determining the first pulse duration using the operating condition.
4. The method of
detecting an operating condition of the magnetic random access memory; and
determining duration of the delay period using the operating condition.
5. The method of
detecting an operating condition of the magnetic random access memory; and
determining the first amplitude using the operating condition.
6. The method of
detecting temperature corresponding to the magnetic random access memory; and
determining at least one of the first pulse duration, the first amplitude, and the delay period based on the temperature detected.
7. The method of
detecting at least one operating condition corresponding to the magnetic random access memory;
adjusting the write pulse pattern based on the at least one operating condition to produce an adjusted write pulse pattern, wherein adjusting the write pulse pattern includes adjusting a number of write pulses applied in the adjusted write pulse pattern; and
applying the adjusted write pulse pattern to the memory cell.
9. The method of
10. The method of
11. The method of
detecting at least one operating condition corresponding to the memory;
adjusting the write pulse pattern based on the at least one operating condition to produce an adjusted write pulse pattern; and
applying the adjusted write pulse pattern to the memory cell.
12. The method of
13. The method of
14. The method of
15. The method of
17. The method of
18. The method of
detecting an operating condition of the magnetic random access memory; and
determining the first pulse duration using the operating condition.
19. The method of
detecting an operating condition of the magnetic random access memory; and
determining duration of the first delay period using the operating condition.
20. The method of
detecting an operating condition of the magnetic random access memory; and
determining the first amplitude using the operating condition.
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This application is a divisional of application Ser. No. 13/631,395 filed Sep. 28, 2012. Application Ser. No. 13/631,395 is incorporated by reference herein in its entirety. This application and application Ser. No. 13/631,395 claim the benefit of U.S. Provisional Application No. 61/576,215 filed Dec. 15, 2011.
The exemplary embodiments described herein generally relate to integrated magnetic devices and more particularly relate to programming methods for magnetoresistive memories.
Magnetoelectronic devices, spin electronic devices, and spintronic devices are synonymous terms for devices that make use of effects predominantly caused by electron spin. Magnetoelectronics are used in numerous information devices to provide non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. The numerous magnetoelectronics information devices include, but are not limited to, Magnetoresistive Random Access Memory (MRAM), magnetic sensors, and read/write heads for disk drives.
Typically an MRAM includes an array of magnetoressistive memory elements. Each magnetoresistive memory element typically has a structure that includes multiple magnetic layers separated by various non-magnetic layers, such as a magnetic tunnel junction (MTJ), and exhibits an electrical resistance that depends on the magnetic state of the device. Information is stored as directions of magnetization vectors in the magnetic layers. Magnetization vectors in one magnetic layer are magnetically fixed or pinned, while the magnetization direction of another magnetic layer may be free to switch between the same and opposite directions that are called “parallel” and “antiparallel” states, respectively. Corresponding to the parallel and antiparallel magnetic states, the magnetic memory element has low (logic “0” state) and high (logic “1” state) electrical resistance states, respectively. Accordingly, a detection of the resistance allows a magnetoresistive memory element, such as an MTJ device, to provide information stored in the magnetic memory element.
There are two completely different methods used to program the free layer: field switching and spin-torque switching. In field-switched MRAM, current carrying lines adjacent to the MTJ bit are used to generate magnetic fields that act on the free layer. In spin-torque MRAM, switching is accomplished with a current pulse through the MTJ itself. The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer, with the final state (parallel or antiparallel) determined by the polarity of the current pulse. A reset current pulse will cause the final state to be parallel or logic “0”. A set current pulse, in the opposite polarity of reset current pulse, will cause the final state to be antiparallel or logic “1”. Spin-torque transfer is known to occur in MTJ devices and giant magnetoresistance devices that are patterned or otherwise arranged so that the current flows substantially perpendicular to the interfaces, and in simple wire-like structures when the current flows substantially perpendicular to a domain wall. Any such structure that exhibits magnetoresistance has the potential to be a spin-torque magnetoresistive memory element.
Spin-torque MRAM (ST-MRAM), also known as spin-transfer torque RAM (STT-RAM), is an emerging memory technology with the potential for non-volatility with unlimited endurance and fast write speeds at much higher density than field-switched MRAM. Since ST-MRAM switching current requirements reduce with decreasing MTJ dimensions, ST-MRAM has the potential to scale nicely at even the most advanced technology nodes. However, increasing variability in MTJ resistance and sustaining relatively high switching currents through bit cell select devices in both current directions can limit the scalability of ST-MRAM. The write current is typically higher in one direction compared to the other, so the select device must be capable of passing the larger of the two currents. In addition, ST-MRAM switching current requirements increase as the write current pulse duration is reduced. Because of this, the smallest ST-MRAM bitcell approach may require relatively long switching times.
Data stored in memory is defined in banks. A rank is a plurality of banks in a first direction (column) and a channel is a plurality of banks in a second direction (row). A process for accessing the memory comprises several clock cycles required for row and column identification and a read or write operation. The bandwidth for the data transfer may comprise a row of many thousands of bits.
The conventional scheme for programming spin-torque MRAM is to apply a single current or voltage pulse to the memory cells to reverse the direction of their storage layer. The duration of the pulse is set by design requirements such as memory interface specifications. Generally, the write operation has to be completed in less than 50 ns. The write voltage amplitude is set to meet the memory write error rate (WER) and lifetime requirements. It has to be greater than a certain value Vw to assure that all bits are programmed reliably, with a write error rate below a defined value WER0. For megabit memories, WER0 is typically less than 10−8. The write voltage amplitude also has to be low enough to assure long-term device integrity. For magnetic tunnel junctions, elevated write voltage reduces the memory lifetime because of dielectric breakdown. In some cases, it is not possible to find a write voltage that meets the desired write error rate WER0 and the required lifetime. Known solutions to improve the write error rate are adding one or several layers of error correction or using multiple write pulses.
Memory devices commonly include some form of error correcting code (ECC) in the output logic circuitry. If a memory bit is not set correctly during the write operation, the ECC may be used to correct the data during a subsequent access. However, if the WER is too high, ECC will not be able to efficiently handle all the failing bits.
The write error rate or switching distribution of magnetic bits as a function of the applied voltage can be well described by an error function. That is why a common approach to set the write voltage for an assembly of bits is to increase it until the write error rate reaches the desired value WER0. Because of the stochastic nature of the magnetization reversal and the presence of defects in the memory elements, deviations from the ideal error function are commonly observed, resulting in an anomalously high write error rate and forcing the write voltage to be raised to meet WER0.
Solutions based on write patterns composed of multiple pulses have been proposed to improve the overall memory write error rate in the presence of bits with anomalous switching distributions. However, such solutions significantly increase the write duration and negatively impact the memory speed performance.
Accordingly, it is desirable to provide a method of improving the write error rate of a memory array without impacting its performance, such as speed and endurance. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
A method and apparatus are provided for writing to a spin-torque magnetoresistive random access memory.
A first exemplary embodiment is a method of determining a write pattern for writing to a plurality of bits in a spin-torque magnetoresistive memory array, the method comprising determining a write voltage in accordance with design requirements for the array; determining the number of write pulses required for a predetermined write time and for minimizing a write error rate for the number of bits, wherein the number of write pulses is at least one; and applying the determined number of write pulses to the array.
A second exemplary embodiment is a method of determining a write pattern for writing to a plurality of bits in a spin-torque magnetoresistive memory array, the method comprising setting a write voltage Vw to a minimum voltage Vmin; b) setting a number of write pulses i to one and a write pulse duration t to a maximum duration Tmax; c) defining a write pattern as a single pulse of duration t with an amplitude Vw; d) characterizing a write error rate (WER) for the write pattern; e) defining write pulse settings as Vw, i, t and d if WER is less than a desired write error rate WER0; if WER is not less than WER0, f) setting i to i+1; g) setting the pulse duration t to (Tmax−(i−1)d)/i; and h) defining the write pattern as i pulses of duration t spaced by distance d with amplitude Vw; i) returning to the step d if t is not less than a minimum duration Tmin; and j) if t is less than Tmin, increasing Vw if Vw is not greater than or equal to a maximum voltage Vmax and returning to step b.
A third exemplary embodiment is a system for determining a write pattern for writing to a spin-torque magnetoresistive memory array, the system comprising a processor configured to determine a write voltage in accordance with design requirements for the array; determine the number of write pulses required for a predetermined write time and for minimizing the WER for the number of bits, wherein the number of write pulses is at least one; and apply the determined number of write pulses to the array; and a plurality of bits in the array configured to receive the determined number of write pulses.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and:
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary, or the following detailed description.
The exemplary method described herein defines an optimized write pattern, in terms of memory speed and endurance, which meets a desired write error rate WER0. In the case where the desired write error rate cannot be achieved by increasing the write voltage with a single pulse, breaking up the write pulse in multiple pulses of shorter duration provides a significant improvement of the write error rate. The duration of the write pattern is independent of the number of pulses it contains; therefore the memory speed is not affected. The multiple pulses may comprise different amplitudes, durations, and shapes. Various exemplary embodiments adjust the write scheme (number of pulses, etc.) based on the memory operating conditions, e.g. operating temperature.
The anomalously high write error rate of certain memory elements might be caused by the magnetic state of the bit free layer during the reversal process. For example, the magnetization of the free layer may adopt a non-uniform configuration preventing it from reversing during the current pulse. After the current is turned off, the magnetization of the free layer will relax to its initial state. For a multi pulse write approach to be efficient, the magnetization of the free layer needs to be either in the initial state or switched state when the pulses are applied. Therefore, in one exemplary embodiment, the delay between the write pulses should be long enough to allow the magnetization to relax to its equilibrium state—typically, a few nanoseconds or less.
In another exemplary embodiment, a write pulse pattern with reversed polarity between the write pulses may be used to reduce the minimum delay. The duration of the reversed polarity pulse is typically a few nanoseconds or less. The spin transfer torque induced by the current pulse acts like an anti-damping and causes the free layer magnetization to reverse. Adding a voltage pulse with reversed polarity in between two consecutive write pulses, will act like an enhanced damping and might help the magnetization of the free layer to relax faster to its equilibrium position. Therefore, the delay between the two consecutive write pulses could be reduced, allowing for longer write pulses for a given total write duration. The amplitude of the reversed polarity pulse is chosen low enough so that it will not cause the magnetic bit to be reset to its initial state in case a previous write pulse set it to the desired state.
The optimal write voltage is likely to change depending on the operating conditions of the memory, for example, temperature. Therefore, in another exemplary embodiment, the write pattern, for example, number of pulses, amplitude, or delay could be adjusted based on the operating conditions. While operating at high temperature, the minimum delay might be reduced because of a shorter relaxation time. This would allow for longer write pulses.
For simplicity and clarity of illustration, the drawing figures depict the general structure and/or manner of construction of the various embodiments. Descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring other features. Elements in the drawings figures are not necessarily drawn to scale: the dimensions of some features may be exaggerated relative to other elements to assist improve understanding of the example embodiments.
Terms of enumeration such as “first,” “second,” “third,” and the like may be used for distinguishing between similar elements and not necessarily for describing a particular spatial or chronological order. These terms, so used, are interchangeable under appropriate circumstances. The embodiments of the invention described herein are, for example, capable of use in sequences other than those illustrated or otherwise described herein.
The terms “comprise,” “include,” “have” and any variations thereof are used synonymously to denote non-exclusive inclusion. The term “exemplary” is used in the sense of “example,” rather than “ideal.”
In the interest of conciseness, conventional techniques, structures, and principles known by those skilled in the art may not be described herein, including, for example, standard magnetic random access memory (MRAM) process techniques, fundamental principles of magnetism, and basic operational principles of memory devices.
During the course of this description, like numbers may be used to identify like elements according to the different figures that illustrate the various exemplary embodiments.
Techniques and technologies may be described herein in terms of functional and/or logical block components, and with reference to symbolic representations of operations, processing tasks, and functions that may be performed by various computing components or devices. Such operations, tasks, and functions are sometimes referred to as being computer-executed, computerized, software-implemented, or computer-implemented. In practice, one or more processor devices can carry out the described operations, tasks, and functions by manipulating electrical signals representing data bits at memory locations in the system memory, as well as other processing of signals. The memory locations where data bits are maintained are physical locations that have particular electrical, magnetic, optical, resistive, or organic properties corresponding to the data bits. It should be appreciated that the various clock, signal, logic, and functional components shown in the figures may be realized by any number of hardware, software, and/or firmware components configured to perform the specified functions. For example, an embodiment of a system or a component may employ various integrated circuit components, e.g., memory elements, digital signal processing elements, logic elements, look-up tables, or the like, which may carry out a variety of functions under the control of one or more microprocessors or other control devices.
For the sake of brevity, conventional techniques related to programming memory, and other functional aspects of certain systems and subsystems (and the individual operating components thereof) may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter.
A magnetoresistive random access memory (MRAM) array includes write current drivers and sense-amplifiers positioned near a plurality of magnetoresistive bits. A write, or program, operation begins when a current of either one of the two different and opposite polarities, set or reset, is applied through the magnetic storage element, e.g., MTJ. Such write mechanism is employed in spin-transfer torque (STT) or spin torque (ST) MRAM. The spin-torque effect is known to those skilled in the art. Briefly, a current becomes spin-polarized after the electrons pass through the first magnetic layer in a magnetic/non-magnetic/magnetic tri-layer structure, where the first magnetic layer is substantially more magnetically stable than the second magnetic layer. The higher magnetic stability of the first layer compared to the second layer may be determined by one or more of several factors including: a larger magnetic moment due to thickness or magnetization, coupling to an adjacent antiferromagnetic layer, coupling to another ferromagnetic layer as in a SAF structure, or a high magnetic anisotropy. The spin-polarized electrons cross the nonmagnetic spacer and then, through conservation of spin angular momentum, exert a spin torque on the second magnetic layer that causes precession of its magnetic moment and switching to a different stable magnetic state if the current is in the proper direction. When net current of spin-polarized electrons moving from the first layer to the second layer exceeds a first critical current value, the second layer will switch its magnetic orientation to be parallel to that of the first layer. If a bias of the opposite polarity is applied, the net flow of electrons from the second layer to the first layer will switch the magnetic orientation of the second layer to be antiparallel to that of the first layer, provided the magnitude of the current is above a second critical current value. Switching in this reverse direction involves a fraction of the electrons reflecting from the interface between the spacer and the first magnetic layer and traveling back across the nonmagnetic spacer to interacting with the second magnetic layer.
Magnetoresistance is the property of a material to change the value of its electrical resistance depending on its magnetic state. Typically, for a structure with two ferromagnetic layers separated by a conductive or tunneling spacer, the resistance is highest when the magnetization of the second magnetic layer is antiparallel to that of the first magnetic layer, and lowest when they are parallel.
A chip select (CS) line 132 provides a CS signal from the memory controller 102 to the non-volatile memory 118. An address bus 137 and a data line 140 couples the memory controller 102 to the non-volatile memory 118. Other control and clock signals may exist between the memory controller 102 and non-volatile memory 118 that are not shown in
A conventional write operation consists of a voltage pulse of amplitude Vw and duration t applied to a memory element to set its magnetic state. Each memory element shows a switching probability distribution 205 as a function of write voltage that is theoretically described by an error function with average value Vc and standard deviation σVc, as illustrated by the line 204
Assuming that σVc and σVcee follow a normal distribution and that the physical mechanisms responsible for these distributions are uncorrelated, it is reasonable to choose the write pulse as a single voltage pulse of duration Tmax and amplitude Vw=Vc
+n√
σVc
2+
σVcee
2 where
Vc
,
σVc
, and
σVcee
are, respectively, the average switching voltage, the average switching voltage standard deviation, and the average element to element switching voltage standard deviation of the memory array. “n” is defined as the inverse standard normal distribution evaluated in 1/N where N is the number of memory elements in the array.
In practice, setting the write conditions is often complicated by a non-ideal behavior of the magnetic memory elements. It is common knowledge that magnetic tunnel junctions often show deviation from the ideal switching distribution especially for short write pulses, typically less than 50 ns. It has also been reported that the magnetic tunnel junctions show deviation from the ideal switching distribution at elevated bias. Because patterning small memory elements, typically less than 100 nm characteristic dimension, is a challenging process, σVcee
is significant, typically 4 to 10% of
Vc
. Therefore, the operating voltage Vw can be significantly higher than
Vc
resulting in non-ideal switching distributions.
In the example of
To address this issue, a write pattern composed of several pulses is described.
As illustrated by
The graph of
Numeral
Pulses
Individual pulse duration (ns)
505
1
10.0
504
1
20.0
503
1
50.0
502
1
100.0
515
2
4.0
514
2
9.0
513
2
24.0
512
2
49.0
525
3
2.0
524
3
5.3
523
3
15.3
522
3
32.0
For a more realistic description, a σVc
dependence on pulse duration was used. In the thermal activation regime, for example 502, 512 and 522, a write pattern composed of several pulses is always beneficial as it provides a lower minimal write error rate and does not constitute a significant increase in Vw. In the dynamical regime, for example 505, 515 and 525, the shorter pulse duration required by the multi-pulse approach leads to a significant increase of Vw which is detrimental to the memory operation as it will reduce its endurance.
The previous discussion has focused on memory elements showing non-ideal switching distributions manifesting as a write error rate plateau at elevated bias. The same approach could be applied to other anomalous behaviors that manifest as a low switching probability due to the magnetization of the free layer of the magnetic element not switching in response to a write voltage pulse.
In an actual memory, the magnetic bits will show a variety of non-ideal switching distributions, for example different levels of write error rate plateau. The bits with a plateau lower than WER0 can be considered as ideal. The total write pulse duration is also likely to be in the vicinity of the dynamical regime, typically less than 50 ns. Therefore, setting the optimal write pulse conditions will result from a tradeoff between the number of pulses i and the operating write voltage Vw. Increasing the number of pulses will improve the write error rate for non-ideal bits and therefore improve the overall memory write error rate. However, it will also raise the write voltage Vw for all the bits.
Vw can be set within a range Vmin to Vmax generally defined by the memory power supplies. Similarly the individual pulse duration, t, can be set within a range Tmin to Tmax. Tmax is the maximum single pulse duration the circuit can allow and still meet its speed requirement. Tmin will mostly likely be limited by the steep increase in switching voltage of the free layer in the dynamical regime, typically on the order of 1 to 10 ns.
Referring to
If the write error rate is greater than the desired write error rate WER0 708, step 714 sets i to equal i+1, sets the pulse duration t to equal (Tmax−(i−1)d)/i, and defines the write pattern as i pulses of duration t spaced by distance d with amplitude Vw. If t is greater than Tmin 716, the process 700 is repeated from step 706; however, if t is less than Tmin 716, and Vw is less than to Vmax 718, then Vw is increased 720 and the process 700 is repeated from step 704. In step 718, if Vw is greater than or equal to Vmax, the process is halted, unable to define appropriate write pulse settings 722 for the given memory specifications.
In another exemplary embodiment, the process 700 will be repeated for different operating conditions, such as operating temperature. The switching distribution of the memory elements and the relaxation time of the magnetization of the free layer change with temperature and are likely to shift the optimal write pulse settings i, Vw, t, and d. Therefore it might be advantageous to characterize the write pulse settings at different temperatures and adjust the memory settings as the temperature changes during its operation.
In another exemplary embodiment, illustrated
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims.
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