A gate line driver circuit for a display panel includes a pull up circuit to drive a gate line of a display panel to a positive voltage that causes display panel switch elements that are coupled to the gate line to transition into an on state, a first pull down transistor to drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state, and a second pull down transistor to maintain the gate line at a second negative voltage that is less negative than the first negative voltage so as to maintain the coupled display panel switch elements in the off state. Other embodiments are also described and claimed.
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17. A method for driving a gate line of a display panel, comprising:
pulling up a gate line of a display panel to a positive voltage that causes a plurality of display panel switch elements, that are coupled to the gate line, to turn on; then
pulling down the gate line to a first negative voltage that causes the switch elements to turn off; and then
maintaining the gate line at a second negative voltage, wherein the first voltage is more negative than the second voltage, and the second voltage maintains the switch elements in the off state.
1. A gate line driver circuit for a display panel, comprising:
a pull up circuit to drive a gate line of a display panel to a positive voltage that causes a plurality of display panel switch elements that are coupled to the gate line to transition into an on state;
a first pull down transistor to directly drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state; and
a second pull down transistor to directly drive and maintain the gate line at a second negative voltage, wherein the first voltage is more negative than the second voltage, and the second voltage maintains the coupled display panel switch elements in the off state.
8. A display system comprising:
an array of display elements;
a plurality of gate lines coupled to the display elements;
a plurality of switch elements each being coupled to a respective combination of display element and gate line;
a signal generator to produce a positive voltage clock signal, and first and second negative voltage clock signals wherein the first negative voltage clock signal is more negative than the second negative voltage clock signal; and
a plurality of gate drivers each being coupled to drive a respective one of the gate lines, each of the gate drivers having an output stage in which there are a high side transistor and first and second low side transistors, wherein the high side transistor is coupled to directly drive the respective gate line responsive to the positive voltage clock signal, and the first and second low side transistors are coupled to directly drive the respective gate line responsive to the first and second negative voltage clock signals.
2. The gate line driver circuit of
3. The gate line driver circuit of
4. The gate line driver circuit of
5. The gate line driver circuit of
6. The gate line driver circuit of
7. The gate line driver circuit of
9. The display system of
and wherein for each turn-off transition of the respective gate line, the first control signal is pulsed, or asserted and then de-asserted, before the second control signal is asserted, wherein assertion of the second control signal maintains the respective gate line at a voltage that causes the coupled switch elements to remain in their off states for a duration of a current display frame.
10. The display system of
11. The display system of
12. The display system of
13. The display system of
14. The display system of
15. The display system of
16. The display system of
18. The method of
19. The method of
20. The method of
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This non-provisional application claims benefit of the earlier filing date of U.S. Provisional Application Ser. No. 62/130,992, filed Mar. 10, 2015.
An embodiment of the invention relates to circuitry for driving the gate lines of a display element array, such as an active matrix liquid crystal display (LCD) panel that also has a metal oxide semiconductor (MOS) thin film transistor (TFT) array. Other embodiments are also described.
For many applications, and particularly in consumer electronic devices, the large and heavy cathode ray tube (CRT) has been replaced by flat panel display types such as liquid crystal display (LCD). A flat panel display contains an array of display elements. Each display element is to receive a signal that represents the picture element (pixel) value to be displayed at that location. In an active matrix array, the pixel signal is applied using a pixel transistor that is coupled to and integrated with the display element. The pixel transistor acts as a switch element. It has a carrier electrode that receives the pixel signal and a control electrode that receives a gate (select) signal. The gate signal may serve to turn on or turn off the transistor so as to selectively apply or “sample” the pixel signal onto the coupled display element. In many instance, the pixel transistor is formed as a thin film transistor (TFT) on the display panel as its substrate.
Typically, thousands or millions of copies of the display element and its associated switch element (e.g., an LCD cell and its associated field effect transistor, FET) are reproduced in the form of an array, on a substrate such as a plane of glass or other light transparent material. The array is overlaid with a grid of data lines and gate lines. The data lines serve to deliver the pixel signals to the carrier electrodes of the transistors and the gate lines serve to apply the gate signals to the control electrodes of the transistors. In other words, each of the data lines is coupled to a respective group of display elements, typically referred to as a column of display elements, while each of the gate lines is coupled to a respective row of display elements.
Each data line is coupled to a data line driver circuit that receives control and pixel signals from a signal generator. The latter translates incoming pixel values (for example, red, green and blue pixel values) into data signals (with appropriate timing). The data line driver then performs the needed voltage level shifting to produce a pixel signal with the needed fan-out (current capability).
As to the gate lines, each gate line is coupled to a gate line driver circuit that receives clock (control) signals from the signal generator. These clocks signals, together with a start or input pulse signal are generated into the domain of a reference clock that is received by the signal generator, along with horizontal and vertical sync signals for defining the scan of a each frame. Each gate driver circuit typically drives a respective gate line. The array of display elements are, in most cases, driven in a horizontal or line-by-line scanning fashion: the desired pixel signals for a selected row of display elements are provided on the data lines; and the selected row of display elements is “enabled” by a pulse that is asserted on the associated gate line, by the gate driver circuit of that gate line. The approach is to scan line-by-line or row-by-row in a vertical direction, until the entire display element array has been “filled” with the pixel values of a single image frame.
The gate driver circuitry has stringent requirements in terms of timing of the transitions in the gate signals that it generates (and that are applied to the gate lines). Due to the nature of the display element array where an entire row of display elements are activated essentially simultaneously (within a single gate signal pulse window), and the relatively large number of rows sometimes, the gate driver circuitry needs to provide precise control of the transitions in these gate drive signals. This is also desirable in view of the relatively high refresh rates of, for example, a 100 Hz display panel, in which the entire array of display elements are refreshed 100 times per second.
It is desirable that the time interval needed for switching off the pixel transistors on a gate line be made smaller, because the sooner the pixel transistors of a given row are turned off, the longer the time interval that is available for performing other needed display tasks, such as settling the data line voltages (pixel signals) for the next frame to be displayed. A faster gate driver circuit is therefore needed, i.e. one that produces a faster turn off phase, for the coupled pixel transistors so that the data line values may be sampled more quickly.
An embodiment of the invention is a gate driver circuit that has a pull up circuit to drive a gate line of a display panel to a positive voltage that causes display panel switch elements that are coupled to the gate line to transition into an on state, a first pull down transistor to drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state, and a second pull down transistor to maintain the gate line at a second negative voltage that is less negative than the first negative voltage so as to maintain the coupled display panel switch elements in the off state.
The above summary does not include an exhaustive list of all aspects of the present invention. It is contemplated that the invention includes all systems and methods that can be practiced from all suitable combinations of the various aspects summarized above, as well as those disclosed in the Detailed Description below and particularly pointed out in the claims filed with the application. Such combinations have particular advantages not specifically recited in the above summary.
The embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment of the invention in this disclosure are not necessarily to the same embodiment, and they mean at least one. Also, a given figure may be used to illustrate the features of more than one embodiment of the invention, and not all elements in the figure may be required for a given embodiment.
Several embodiments of the invention with reference to the appended drawings are now explained. Whenever aspects of the embodiments described here are not clearly defined, the scope of the invention is not limited only to the parts shown, which are meant merely for the purpose of illustration. Also, while numerous details are set forth, it is understood that some embodiments of the invention may be practiced without these details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.
The system also has gate line driver circuitry that generates, and is coupled to apply, an output pulse G(i) to each of the N gate lines 6. There is a separate gate line driver 5 (also referred to here as gate driver 5) coupled to drive a respective one of the gate lines 6 as shown. In this example, each gate driver 5 receives at least two clock signals, here, four clocks signals CKA, CKB, CKC, and CKD, which are produced by a signal generator 9. A clock signal is a precision generated digital periodic signal, e.g. binary, 50% duty cycle or square wave, whose transitions may be precisely controlled to be in synch with a reference clock (e.g., refclock). Note that the amplitude of a clock signal may be larger than the swing used by general purpose logic gates, particularly in the case of clock signals applied to drains or sources of the output stage transistors of the gate driver circuit 5 which as explained below may impart a larger amplitude to the output pulse G(i). In one embodiment, each of the clock signals has 50% duty cycle, and their half-period is equal to about twice the duration of a horizontal sync interval H. Other ways of defining the clock signals that are input to the gate driver circuitry are possible.
The gate driver 5 also has a Carrier-In input (In). This input may receive a start pulse (SP, also referred to here as input pulse), when the gate driver 5 is located at the edge of the display element array. Note however that some of the inputs to a particular gate driver 5 may be generated by another gate driver 5; for example, the Carrier-In of the third and any subsequent gate driver 5 is fed by the output pulse G of two rows prior, i.e. G(3) is responsive to G(1) at Carrier-In, G(4) is responsive to G(2) at Carrier-In, G(5) is responsive to G(3), etc. Other ways of triggering the output pulse G(i) of a given gate driver 5 are possible. In one embodiment, the gate drivers 5 are designed such that as a whole they act like a shift register, sequentially generating and applying an output pulse G(i) to each successive gate line 6, when triggered by the start pulse SP.
The clock signals and start pulse SP are produced by a signal generator 9 in response to translating or decoding conventional Hsync and Vsync video display timing signals together with a data enable signal (not shown) that may be received from a video/graphics/touchscreen, vgt, controller (not shown). The signal generator 9 also decodes the incoming pixel values from the vgt controller, into their corresponding voltage or current signals (data signals) for the data line drivers 3, which in turn create the pixel signals to be applied to each display element 2 by its associated switch element 7. The signal generator 9 may use a reference clock (refclock) that may be provided by the vgt controller, to precisely control the timing or signal transitions of the clocks CKA . . . CKD and SP that it produces.
Turning now to
In
The output stage also includes a pull down circuit, including first low side or pull down transistor 13 to directly drive the gate line to a first negative voltage to cause the coupled display panel switch elements to transition into an off state, and a second low side or pull down transistor 14. In this case, these two transistors 13, 14 are both n-channel MOS (NMOS) FETs whose drains are coupled to the gate line 6. These are operated as pull-down devices. The transistor 13, also labeled as Overdrive NMOS, has its source coupled to VGL_ovrdrv (here, −20V is used as an example, although other voltages are possible as explained below), while the transistor 14, labeled as Hold NMOS, has its source coupled to VGL_hold (here, −12V is used as an example, but other voltages are possible so long as they are sufficiently “low” to maintain the switch element 7 in its turned off state). The Overdrive NMOS (transistor 13) serves to over drive the gate line 6 for a “short” time during pull down, thereby rapidly discharging the control electrodes of the switch elements 7 (e.g., the gate electrodes of the coupled pixel TFTs). This lowers G(i), the voltage on the gate line 6, to a sufficiently low level as to thereby turn off the coupled TFTs. In contrast, the Hold NMOS (transistor 14) serves to directly hold or maintain a less negative (and non-damaging) voltage on the gate line 6, that is less negative than VGL_ovrdrv, after the gate line voltage has transitioned into an “off” range. In one embodiment, the Overdrive NMOS is a larger device than the Hold NMOS (e.g., it has a lower on resistance, Rds_on). That feature, combined with its more negative source line voltage, enables it to sink more current than the Hold NMOS, to thereby discharge the gate line 6 rapidly and force the pixel TFTs to turn off rapidly. An example behavior of the voltage on the gate line 6 during a turn off phase is shown
In
As seen in
Also, the particular example gate driver output stage in
While certain embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that the invention is not limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those of ordinary skill in the art. For example, although the simulation results above were obtained for the circuit in
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
6094095, | Jun 29 1998 | MONTEREY RESEARCH, LLC | Efficient pump for generating voltages above and/or below operating voltages |
6262598, | Mar 05 1999 | Sharp Kabushiki Kaisha | Voltage level shifter |
8004339, | Nov 19 2009 | Integrated Device Technology, Inc.; Integrated Device Technology, inc | Apparatuses and methods for a level shifter with reduced shoot-through current |
20030201803, | |||
20090046503, | |||
20090103382, | |||
20100231569, | |||
20120127138, | |||
20150042689, | |||
20150077407, | |||
20150102990, | |||
20150303925, |
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