Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.
|
4. A method of multiplexing a plurality of data structures into one or more aggregated data structures for transit via a virtualized bus interface, comprising:
aggregating a plurality of datagrams into an aggregated data block, the aggregating the plurality of datagrams into an aggregated data block being characterized at least in part by one or more commands;
aggregating the one or more commands into an aggregated command block; and
transmitting the aggregated data block and the aggregated command block.
1. processor apparatus, comprising:
a first digital processor;
a physical bus interface in data communication with the first digital processor; and
a computer readable medium comprising one or more computer readable instructions, the one or more computer readable instructions configured to, when executed by the first digital processor, cause the processor apparatus to:
receive a plurality of datagrams from a plurality of data interfaces;
for each one of the plurality of data interfaces:
order a corresponding subset of the plurality of datagrams into a corresponding session;
generate one or more commands based on one or more session operations associated with the corresponding session;
aggregate the plurality of datagrams into an aggregated data block;
aggregate the one or more commands into an aggregated command block; and
transmit the aggregated data block and the aggregated command block via the physical bus interface.
2. The processor apparatus of
3. The processor apparatus of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
|
|||||||||||||||||||||||||||||||
This application claims the benefit of priority to co-owned and U.S. Provisional Patent Application Ser. No. 62/050,973 of the same title filed Sep. 16, 2014, which is incorporated herein by reference in its entirety.
This application is also related to commonly owned and U.S. Provisional Patent Application Ser. No. 62/112,061 entitled “METHODS AND APPARATUS FOR CONTROLLED RECOVERY OF ERROR INFORMATION BETWEEN INDEPENDENTLY OPERABLE PROCESSORS” filed Feb. 4, 2015; U.S. Provisional Patent Application Ser. No. 62/061,605 entitled “METHODS AND APPARATUS FOR AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS” filed Oct. 8, 2014; and U.S. Provisional Patent Application Ser. No. 62/175,174 entitled “METHODS AND APPARATUS FOR SYNCHRONIZING UPLINK AND DOWNLINK TRANSACTIONS ON AN INTER-PROCESSOR COMMUNICATION LINK” filed Jun. 12, 2015, each of the foregoing incorporated herein by reference in its entirety.
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
The disclosure relates generally to the field of electronics devices, as well as networks thereof. More particularly, in one exemplary aspect, the disclosure is directed to methods and apparatus for aggregating packet transfer over a virtual bus-based interface.
Various types of data multiplexing approaches are currently known, One such exemplary data multiplexing solution implements Ethernet capabilities on a Universal Serial Bus (USB). In particular, the USB Implementers Forum (USB-IF) standards provide for a Communication Device Class (CDC) which supports three (3) subclasses: Ethernet Control Model (ECM), Ethernet Emulation Model (EEM), and Network Control Model (NCM). Those of ordinary skill in the related arts will recognize that the USB CDC NCM subclass was generally promulgated to address operation within e.g., handheld mobile devices such as cellular-enabled smartphones, etc. In large part, the USB CDC NCM subclass was tailored to improve power consumption, and maximize direct memory access (DMA) technologies which are common within such consumer electronics devices.
As described within “USB Communication Class Subclass Specification for Network Control Model (NCM) Devices; Revision 1.0 (Errata 1)” incorporated by reference in its entirety herein, USB CDC NCM is a protocol by which USB hosts and device can effectively exchange Ethernet frames. As used therein, the term “Ethernet frames” refer without limitation to IPv6 and IPv4 (Internet Protocol) datagrams that are configured for transport over a communication network. USB CDC NCM supports aggregation of multiple Ethernet frames within a single USB transfer, and also limited configuration of (e.g., placement, etc.) Ethernet frames within a USB transfer.
Unfortunately, existing bus protocols for USB CDC NCM do not support capabilities for multiplexing of interfaces, flow control, interface and session management, transfer hits and packet padding. Specifically, USB CDC NCM does not include: (i) mechanisms for multiplexing multiple logical interfaces over a single physical interface, (ii) mechanisms for exchanging session management and logical interface control, (iii) mechanisms for flow control, (iv) mechanisms for providing “transfer hints” about the data (e.g., metadata), and/or (v) mechanisms for padding data packets.
The present disclosure satisfies the foregoing needs by providing, inter alia, methods and apparatus for aggregating packet transfer over a virtual bus based interface.
In a first aspect, a processor apparatus is disclosed. In one embodiment, the processor apparatus includes: a first digital processor; a physical bus interface in data communication with the first digital processor; and a computer readable medium comprising one or more computer readable instructions. In one exemplary implementation the one or more computer readable instructions are configured to, when executed by the first digital processor, cause the first processor to: receive a plurality of datagrams from a plurality of data interfaces; for each one of the plurality of data interfaces: order a corresponding subset of the plurality of datagrams into a corresponding session; generate one or more commands based on one or more session operations associated with the corresponding session; aggregate the plurality of datagrams into an aggregated data block; aggregate the one or more commands into an aggregated command block; and transmit the aggregated data block and the aggregated command block via the physical bus interface.
In one variant, the one or more commands comprise one or more flow control commands for the corresponding session. In some cases, the corresponding session is associated with one data interface.
In another variant, the processor apparatus is embodied as one or more integrated circuits (ICs), such as part of a system-on-chip (SoC) device, and/or part of a chipset.
In a second aspect, a method of multiplexing a plurality of data structures is disclosed. In one embodiment, the multiplexing includes multiplexing into one or more aggregated data structures for transit via a virtualized bus interface, and the method includes: aggregating a plurality of datagrams into an aggregated data block, the aggregating the plurality of datagrams into an aggregated data block being characterized by one or more commands; aggregating the one or more commands into an aggregated command block; and transmitting the aggregated data block and the aggregated command block.
In one variant, the transmission of the aggregated data block is performed via the physical bus interface. In some cases, the transmission of the aggregated command block is performed via the physical bus interface. Alternatively, the transmission of the aggregated command block can be performed via an out-of-band interface.
In a second variant, the one or more commands indicate the addition or removal of a session comprised of a subset of the plurality of datagrams.
In a third variant, the one or more commands indicate the increase or decrease of a data rate associated with a session comprised of a subset of the plurality of datagrams.
In a fourth variant, the one or more commands indicate the presence of one or more padding data within a session comprised of a subset of the plurality of datagrams.
In a third aspect, a processor apparatus is disclosed. In one embodiment, the processor apparatus includes: a first digital processor; a physical bus interface in data communication with the first digital processor; and a computer readable medium comprising one or more computer readable instructions. In one exemplary implementation, the one or more computer readable instructions are configured to, when executed by the first digital processor, cause the first processor to: receive an aggregated data block and an associated aggregated command block; divide the aggregated command block into one or more constituent commands; divide the aggregated data block into a plurality of datagrams based on the one or more constituent commands; and provide the plurality of datagrams to corresponding ones of a plurality of data interfaces.
In one variant, the processor apparatus is embodied as one or more integrated circuits (ICs), such as part of a system-on-chip (SoC) device, and/or part of a chipset.
In another variant, the aggregated data block comprises one or more Internet Protocol (IP) datagrams. In one such case, the first processor is further configured to order at least a subset of the plurality of datagrams into a session associated with one data interface.
In a fourth aspect, a method of demultiplexing one or more aggregated data into a plurality of data structures is disclosed. In one embodiment, the method includes: receiving an aggregated data block and an associated aggregated command block; dividing the aggregated command block into one or more constituent commands; dividing the aggregated data block into a plurality of datagrams based on the one or more constituent commands; and generating at least one session from the plurality of datagrams.
In one variant, the method further includes identifying when at least one command block is missing or corrupted and responsively requesting a retransmission of the at least one command block.
In a second variant, the method further includes identifying when at least one command block is missing or corrupted and responsively flagging an error.
In a third variant, the method further includes separately queuing one or more aggregated data blocks and one or more aggregated command blocks; and identifying the aggregated data block and the associated aggregated command block based on at least one sequence number associated therewith.
In a fourth variant, the method further includes storing the at least one session within a receive buffer. In one such case, the method further indicates when the receive buffer is in danger of overflowing or under-flowing.
In a fifth variant, the generated at least one session is based at least in part on stateful information associated with a previous aggregated command block.
Other features and advantages of the present disclosure will immediately be recognized by persons of ordinary skill in the art with reference to the attached drawings and detailed description of exemplary embodiments as given below.
All Figures © Copyright 2014-2015 Apple Inc. All rights reserved.
Reference is now made to the drawings, wherein like numerals refer to like parts throughout.
Detailed Description of Exemplary Embodiments
Exemplary embodiments of the present disclosure are now described in detail. While these embodiments are primarily discussed in the context of modifications to a Peripheral Component Interconnect Express (PCIe) to support a virtual bus based packet interface, it will be recognized by those of ordinary skill that the present disclosure is not so limited. In fact, the various aspects of the disclosure are useful in any device or network of devices that is configured to incorporate and coordinate multiple independent processing elements as is disclosed herein.
Additionally, while the following embodiments describe specific implementations of e.g., dedicated address spaces, legacy support capabilities, and specific protocols, those of ordinary skill in the related arts will readily appreciate that such descriptions are purely illustrative, and that the present disclosure is not so limited, as is specifically contemplated for use with a variety of other implementations.
As used herein, the term “logical” or “virtual” are interchangeably used to refer, without limitation, to an abstraction (typically performed in software or machine logic) to represent physical mechanisms, attributes or functionalities as a data structure. For example, as used herein a “logical bus interface”, “virtual bus interface”, etc. refers generally to an abstraction or representation of a bus interface as a series of data structures. In contrast, as used herein a “physical bus interface” refers to the physical mechanisms, attributes or functionalities of a physically tangible bus interface.
As used herein, the term “in-band” refers to, without limitation, data transactions which are transacted within a logical or physical interface, and which affect the mechanisms, attributes or functionalities of the logical or physical interface. In contrast, the term “out-of-band” refers to data transactions which are not transacted within a logical or physical interface, and which affect the mechanisms, attributes or functionalities of the logical or physical interface.
Exemplary Data Multiplexing
Methods and apparatus are now described for supporting data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. In one such exemplary embodiment, the virtual bus multiplexing supports flow control for each of the virtualized bus interfaces. Flow control refers generally and without limitation to a process of managing a rate of data transmission of the one or more virtual bus interfaces to prevent data loss/corruption (e.g., overwhelming the receiver), or to achieve other desired performance.
Historically, most computing devices have been designed according to the Personal Computer (PC) paradigm, where a single processor is largely responsible for managing software execution. However, computing devices have significantly evolved to fit a diverse ecosystem of designs and uses; additionally, processor technologies have improved, offering significant computing power at near commodity prices. Within the context of consumer electronics (e.g., personal wireless devices (such as the iPhone), personal media devices (such as the iPad/iPod), and personal computers (such as the MacBook Pro and MacBook Air)), various considerations have resulted in designs which utilize multiple independent processor operation.
For example, in typical wireless devices, an applications processor (AP) operates independently from a wireless baseband modem processor (BB). During normal operation, the wireless device may selectively use one or both of the AP and BB, depending on the particular application. When either the AP or BB is not in active use (or in preparation for use, etc.), the processor is put to sleep so as to reduce power consumption, etc. Conceptually similar design paradigms are used for media devices (where the media processor is independent from an applications processor), etc.
As shown, the physical bus interface 104 includes an inter-processor communication (IPC) that is loosely based on the Peripheral Component Interconnect Express (PCIe) standard (e.g., as is described in “PCI Express Base Specification Revision 3.1” published Oct. 8, 2014. Those of ordinary skill in the related arts, given the contents of the present disclosure, will readily appreciate that other bus interface standards may be substituted with equal success. Various modifications to the underlying physical bus interface 104 (and protocols used therewith) to support IPC functionality is described in greater detail hereinafter.
In one exemplary embodiment, the first processor 102A includes an applications processor (AP). As shown in
In the exemplary embodiment, the physical bus interface 104 is a point-to-point communication channel between two PCIe ports (the RC and EP) allowing both to send/receive access requests (configuration read/write, I/O read/write, memory read/write) and interrupts. At the physical level, a link is composed of one or more lanes, each lane having receive and transmit component (pcie_rx, pcie_tx). Each lane is a full-duplex byte stream, transporting data packets in eight-bit “byte” formats, between the RC and EP of a link, in both directions simultaneously. The physical link 104 can support multiple logical links (or virtual bus interfaces) representing multiple ongoing data sessions.
As shown, both the first and the second processors (102A, 102B) are each coupled to a non-transitory computer readable medium (e.g., dynamic random access memory (DRAM)) (108A, 108B) and a memory management unit (MMU) (110A, 110B). The non-transitory computer readable medium is configured to store computer readable instructions for execution. As used herein, the term “memory” includes any type of integrated circuit or other storage device adapted for storing digital data including, without limitation, ROM, PROM, EEPROM, DRAM, SDRAM, DDR/2 SDRAM, EDO/FPMS, RLDRAM, SRAM, “flash” memory (e.g., NAND/NOR), and PSRAM. In some cases, the first and/or second processors may have an associated non-volatile memory 110 (e.g., a Flash memory) which is configured to store computer readable instructions, and retain the stored computer readable instructions without power.
In one embodiment, the computer readable instructions, when executed by at least one of the first or second processors (102A, 102B) is configured to multiplex multiple virtual bus interfaces over a single physical interface 104.
In one embodiment, the computer readable instructions, when executed by at least one of the first or second processors (102A, 102B) is configured to exchange session management information and virtual bus interface control information.
In one embodiment, the computer readable instructions, when executed by at least one of the first or second processors (102A, 102B) is configured to perform flow control by enabling, disabling, and/or throttling data transfer rates of the single physical interface 104. In one such variant, flow control is implemented based at least in part on a receiver of the data flow identifying a current and/or future overflow condition.
In one embodiment, the computer readable instructions, when executed by at least one of the first or second processors (102A, 102B) is configured to provide metadata regarding a data transaction. In one such variant, the metadata includes so-called “hint data” which indicates that the data conforms to a particular format e.g., IPv4, IPv6, etc.
In one embodiment, the computer readable instructions, when executed by at least one of the first or second processors (102A, 102B) is configured to insert padding data to conform to various transaction requirements (e.g., to ensure that a minimum amount of data is transferred). In some variants, the padding may be fixed (all zeros, or all ones), random, or proprietary in nature.
As shown, the aggregated data block header 202 includes a signature field, sequence number, block length, and first table index. The signature field is configured to indicate the presence of the aggregated data block header 202 (to differentiate the data block header from a datagram table or command block header). The sequence number is an automatically incrementing value which indicates continuity (i.e., that no aggregated data blocks have been skipped or lost). The block length provides the total length of the aggregated data block including the aggregated data block header 202, all the datagrams 204, and all the datagram tables 206. The first table index indicates the location of the next datagram table (which is not necessarily sequential).
As shown each datagram 204 includes padding information and a payload. In the exemplary case, the payload is an IP packet, however those of ordinary skill, given the contents of the present disclosure, will readily appreciate that other datagram formats may be substituted (e.g., proprietary and/or other application specific datagram formats).
As shown the datagram tables 206 include a signature, table length, interface identifier, next table index, and a plurality of datagram information (index, length, padding, etc.). Similar to the block header, the signature indicates the presence of a datagram table, the table length indicates the length of the table, and the next table index provides a reference to the location of the next datagram table. The interface identifier is configured to identify the virtual bus interface that the datagram table is associated with (i.e., each virtual bus interface has its own distinct set of datagrams and datagram tables), and the plurality of datagram information allows the virtual bus interface to unpack the datagrams associated therewith.
As shown, the aggregated command block header 302 includes a signature field, sequence number, block length, and first command index. The signature field is configured to indicate the presence of the aggregated command block header 302. The sequence number is an automatically incrementing value that can be used to recover the original ordered continuity in the event that one or more blocks is lost or received in non-consecutive order. The block length provides the total length of the aggregated command block including the aggregated command block header 302, and all the commands 304. The first command index indicates the location of the next command (which is not necessarily sequential).
As shown each command 304 includes a signature, command length, interface identifier, next command index, and a plurality of command information (command type, transaction identifier, and command parameters, etc.). The signature indicates the presence of a command, and the next command index provides a reference to the location of the next command. The interface identifier is configured to identify the virtual bus interface that the command is associated with, and the plurality of command information is used to manage the virtual bus interface (e.g., enable, disable, throttle, etc.).
As shown in
The virtual bus transactions of multiple virtual buses are queued into a subsequent sequential ordering of the aggregated data block and creation of multiple datagram tables. The references for each virtual bus transaction references the next virtual bus transaction (e.g., as a linked list array). The resulting aggregated data block can then be combined with the aggregated command blocks.
In one such embodiment, each virtual bus interface further includes one or more “sessions” which are a persistent and/or semi-persistent set of data transactions (e.g., datagrams) between two logical endpoints. In some embodiments, the session may include “stateful” transactions (i.e., the data transactions are based on a current state of the session), and/or “stateless” transactions (i.e., the data transactions are not based on a current state of the session). The session management commands for each virtual bus interface are queued within the command block aggregator/encoder as a command entry. For example, all of the commands associated with a particular interface identifier would be present within its corresponding command. The command entries are queued into an array. The references for each virtual bus command array references the next virtual bus command array (e.g., as a linked list array) to create the resulting aggregated command block.
In one exemplary embodiment, session management commands are configured to open and close new sessions within a virtual bus interface, and/or enable/disable virtual bus interfaces. For example, in one simplified case the session management commands may be configured to: open a session on a virtual bus interface, close a session on a virtual bus interface, enable flow control on a virtual bus interface, and disable flow control on a virtual bus interface. In some variants, commands may additionally be acknowledged (ACK) or not acknowledged (NACK). In some cases, NACK'd commands may be re-attempted until successful. In other cases, NACK'd commands may result in more sophisticated error handling.
As should be apparent to those of ordinary skill in the related arts, given the contents of the present disclosure, opening/closing a session will affect the amount of data (e.g., datagrams) transferred via a virtual bus interface, whereas enabling/disabling a virtual bus interface will suspend the virtual interface operation (e.g., a halt to all datagrams associated with the virtual interface).
As shown in
Methods—
At step 602 of the method 600, a plurality of datagrams are received from a plurality of data interfaces of a transmitter. In one exemplary implementation, the plurality of datagrams include IPv6 and IPv4 (Internet Protocol) datagrams that are configured for transport over a packet switched communications network. While the present description is presented within the context of datagrams, those of ordinary skill in the related arts will readily appreciate that virtually any data structure and/or data format may be substituted with equal success. Common examples of other suitable data structures include, without limitation: compressed data, encrypted data, streaming data (e.g., audio/visual data), bulk data, control data (e.g., flow control, error checking information, etc.), etc.
In one embodiment, the packet switched communications network is configured as a host-peripheral network topology, where one or more hosts are configured to control and/or manage data transactions. As artisans of ordinary skill in the related arts will readily appreciate, the various principles described herein may be broadly applicable to both mastered networks (i.e., where a device or process has supervisory control over other devices or processes), as well non-mastered technologies (e.g., peer networks where peer devices arbitrate over shared resources, and/or network technologies characterized by dedicated connectivity, etc.).
While the foregoing datagrams are configured for use within packet switched networks, as described herein, the datagrams are not in the exemplary implementations transmitted within a packet switched network. Instead, the various embodiments described hereinafter multiplex (or aggregate) the datagrams (and corresponding control commands) into an aggregated data stream which is transmitted via a virtualized bus interface. In one exemplary embodiment, the virtualized bus interface enables a high speed physical link to support the data transactions between the data interfaces at the transmitter and corresponding receiver data interfaces.
In one exemplary embodiment, the plurality of data interfaces are associated with one or more distinct software applications that transact data via the aforementioned virtualized bus interface. Various embodiments may further subdivide the various ones of the data interfaces into e.g., virtualized software sessions, virtualized software ports, etc. In other embodiments, the plurality of data interfaces may be coupled to one or more external data sources via e.g., a physical port or interface and an appropriate networking fabric, hub, switch, relay, repeater, and/or network bridge. Those of ordinary skill in the related arts will readily appreciate that any software entity that is configured to communicate datagrams (e.g., IPv6 and IPv4) can be coupled to a data interface with minimal (if any) modification. Still other embodiments may interchangeably combine both virtualized and physical data interfaces.
For each one of the plurality of data interfaces, corresponding subsets of the plurality of datagrams are ordered into a session (step 604 of the method 600). As used herein, each “session” constitutes a persistent and/or semi-persistent set of data transactions between two logical endpoints. In some variants, the sessions may include stateful and/or stateless transactions. Stateful transactions incorporate historic “state” information as to the previous delivery of datagrams so as to e.g., enable error correction, retransmission, error detection, etc. Stateless transactions can be transacted without reference to previous transactions.
As used herein, a logical endpoint is defined, without limitation, as either the originating network address or the terminating network address of the data transaction within a transit network. For example, within IPv6 and IPv4 technologies, a datagram is sent from a starting address to a destination address, via a network of intermediary devices. While intermediary nodes may assist in the delivery of the datagram via intermediate “hop” transactions, intermediary nodes do not significantly alter the payload of the datagrams.
In some embodiments, the sessions may be ordered according to a specific priority or other organizational scheme. Common examples of priorities/schemes include without limitation: sequential datagram delivery, delivery within a specified time frame, guaranteed delivery, prioritized delivery, best effort delivery, minimum throughput/maximum latency delivery, etc. Those of ordinary skill in the related arts will readily appreciate that higher priority datagrams may be prioritized over other datagrams.
In some embodiments, the session ordering may be required to insert “padding” or similar ancillary data to conform to various transaction requirements and/or to optimize processing transactions. For example, in order to ensure that a minimum amount of data is transferred, some variants may add data that is fixed (all zeros, or all ones), random, or proprietary in nature. Similarly, where an overflow condition may occur (or may be predicted to occur), one or more datagrams may be punctured (i.e., where portions of data are removed), or skipped altogether. In some variants, modifications to the session are further flagged so as to facilitate restoration and/or prevent undesirable data corruption errors.
In some embodiments, the session ordering may be further configured to insert datagrams which have been previously transmitted (but were corrupted, not acknowledged, or otherwise not properly received). For example, in some systems, each datagram must be acknowledged (ACK) or not acknowledged (NACK). When a datagram is transmitted, but a NACK is returned or an ACK is never received or an ACK is received outside of acceptable response times, then the transmitter may re-attempt the transmission. In some cases, only a limited number of retransmissions are accepted. In alternative embodiments, failure to receive an ACK within acceptable time periods flags an error but not a retransmission. Still other ACK/NACK schemes will be readily appreciated by those of ordinary skill in the related arts, the foregoing being purely illustrative.
At step 606 of the method 600, one or more commands are generated based on one or more session operations. In one exemplary embodiment, the session management commands for each virtual bus interface are queued within a command block aggregator/encoder as command entries. In one such implementation, the commands associated with a particular interface identifier are queued into an array for subsequent aggregation.
More generally, those of ordinary skill in the related arts will readily appreciate that commands and/or aggregated command blocks are configured to control the session operation (either alone or in conjunction with one another). For example, session operation may include opening/closing a session, flow control on a corresponding session, etc. In some exemplary instances, command blocks and/or aggregated command blocks are transacted so as to trigger changes to session operation. In other exemplary instances, command blocks and/or aggregated command blocks are transacted so as to respond to datagrams received on the session (e.g., or the lack of received datagrams). Still other variants will be readily appreciated by those of ordinary skill in the related arts.
In some embodiments, the session operation may include generating metadata. For example, in some embodiments, the metadata includes so-called “hint data” which indicates that the data conforms to a particular format e.g., IPv4, IPv6, etc. Hint data can be used by downstream software to quickly determine the contents of the datagrams, thereby reducing processing burdens, etc. Other common examples of hint data include data directed to identifying specific data formats, and/or data traffic requirements. For example, certain audio/visual data payloads may be encrypted according to proprietary standards which deviate from generic data handling.
In another example, the metadata may include flow control commands. Common examples of flow control commands include without limitation: enabling a session, disabling a session, reducing/increasing a data rate for a session, etc. In one such variant, flow control is implemented based at least in part on a receiver of one or more data sessions indicating a current and/or future overflow condition. For example, a receiver may indicate to the transmitter that the received datagrams exceed the receiver's receive buffer (overflowing), or that the receiver's buffer is in danger of under-flow (i.e., data is consumed faster than is being received). Still other implementations may identify overflow or under-flow conditions based on out-of-sequence or missing datagrams.
At step 608 of the method 600, the plurality of datagrams are aggregated into an aggregated data block. In one exemplary embodiment, the aggregated data block includes the plurality of datagrams and one or more associated data tables. In one such embodiment, each data table is configured to identify its associated datagrams, and provide a reference to another data table (similar to a linked list). Those of ordinary skill in the related arts will readily appreciate that other types of data structures may be used with equivalent success; for example, the aggregated data block may include a table index which identifies each data table, whereupon each data table may be configured to identify its associated datagrams. Still other schemes may be readily contemplated by those of ordinary skill in the related arts, given the contents of the present disclosure.
An aggregated data block may include without limitation one or more of: a header, a footer, a start/end indication (pre-amble, post-amble), order information, error correction data, identifying information, format information, state information, etc. For example, in one exemplary embodiment, the aggregated data block header includes a signature field, sequence number, block length, and first table index. More generally, each aggregated data block may provide information so as to enable the receiver to separate the aggregated data block into its constituent datagrams.
A datagram may include without limitation one or more of: a header, a footer, order information, error correction data, and a payload. In one exemplary embodiment, each datagram includes padding information and a payload. In the exemplary case, the payload is an IP packet, however those of ordinary skill, given the contents of the present disclosure, will readily appreciate that other datagram formats may be substituted (e.g., proprietary and/or other application specific datagram formats). More generally, each datagram includes sufficient information to indicate how the datagram is to be interpreted with respect to its associated session. In one exemplary embodiment, a datagram table includes a signature, table length, interface identifier, next table index, and a plurality of datagram information (index, length, padding, etc.) The datagram table is configured to identify which datagrams of the aggregated data block are allocated to its associated session.
In some embodiments, a null datagram table may be provided where there are no datagrams for a session within an aggregated data block. In still other embodiments, when there are no datagrams for a session within an aggregated data block, then no data table is provided. In still other embodiments, session control may be handled within control commands that are provided via the aggregated command block. Still other variants will be readily appreciated by those of ordinary skill in the related arts.
At step 610 of the method 600, in addition to aggregating the datagrams into an aggregated data block, the one or more commands are aggregated into an aggregated command block. In some variants, the aggregated command block may include other useful information such as e.g., a header, a footer, a start/end indication (pre-amble, post-amble), order information, error correction data, identifying information, etc. For example, in one exemplary embodiment, the aggregated command block begins with a header that includes a signature field, sequence number, block length, and first command index.
In one exemplary embodiment, the session management commands associated with each data interface are queued within the command block together. For example, all of the commands associated with a particular session or data interface are grouped together. In other embodiments, the session management commands are ordered according to a priority (so as to ensure that highest priority commands are received first). In still other embodiments, the session management commands are ordered so as to minimize processing burden for unpacking the aggregate data block (e.g., based on sequential order, etc.).
At step 612 of the method 600, the aggregated data block and the aggregated command block are transmitted via a physical bus interface. In other embodiments, the aggregated data block and the aggregated command block may be transacted via different physical interfaces. For example, in some implementations, the data transfer occurs via a primary link, whereas the commands are transacted via an out-of-band or auxiliary interface.
At step 702 of the method 700, an aggregated data block and associated aggregated command block are received. In some embodiments, the aggregated data block and associated aggregated command block are independently received. In other embodiments, the aggregated data block and associated aggregated command block are received concurrently. In still other embodiments, aggregated data blocks and aggregated command blocks are separately queued and a subsequent association is determined based on e.g., sequence numbers, etc.
At steps 704 of the method 700, the aggregated command block is divided into its constituent commands, and one or more session and ordering information is extracted from the aggregated command block. At step 706 of the method 700, the aggregated data block is divided into its constituent plurality of datagrams based on the extracted one or more session and ordering information. In some embodiments, steps 704 and 706 are performed concurrently or in parallel. In other embodiments, step 704 is performed prior to step 706 where the extracted command information is used to unpack the aggregated data block.
In some embodiments, the extracted command blocks and/or the extracted datagrams may be additionally verified for completeness and/or data corruptions. In the event of missing or corrupted datagrams and/or command blocks, the receiver may request a retransmission of the missing or corrupted datagrams and/or command blocks. In other variants, the receiver may log such errors for subsequent error analysis and/or to facilitate future resource allocations.
At step 708 of the method 700, the one or more of the plurality of datagrams are provided to corresponding ones of a plurality of data interfaces of a receiver. In some cases, the plurality of data interfaces of a receiver may receive other optimization information so as to reduce processing burdens where unnecessary (due to e.g., inactive sessions, hint track information, etc.).
While the foregoing methods are described based on a one-to-one relationship of one aggregated data block and one aggregated command block, it will be readily appreciated by those of ordinary skill in the related arts that a one-to-many, many-to-one or many-to-many relationship may be used with equal success with proper adaptation.
It will be recognized that while certain embodiments of the present disclosure are described in terms of a specific sequence of steps of a method, these descriptions are only illustrative of the broader methods described herein, and may be modified as required by the particular application. Certain steps may be rendered unnecessary or optional under certain circumstances. Additionally, certain steps or functionality may be added to the disclosed embodiments, or the order of performance of two or more steps permuted. All such variations are considered to be encompassed within the disclosure and claimed herein.
While the above detailed description has shown, described, and pointed out novel features as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from principles described herein. The foregoing description is of the best mode presently contemplated. This description is in no way meant to be limiting, but rather should be taken as illustrative of the general principles described herein. The scope of the disclosure should be determined with reference to the claims.
Garg, Saurabh, Sanghi, Karan, Pulyala, Radha Kumar
| Patent | Priority | Assignee | Title |
| 10331612, | Jan 09 2018 | Apple Inc | Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors |
| 10346226, | Aug 07 2017 | Time Warner Cable Enterprises LLC; Apple Inc | Methods and apparatus for transmitting time sensitive data over a tunneled bus interface |
| 10372199, | Oct 08 2014 | Apple Inc. | Apparatus for managing power and running and booting an inter-processor communication link between independently operable processors |
| 10372637, | Sep 16 2014 | Apple Inc. | Methods and apparatus for aggregating packet transfer over a virtual bus interface |
| 10489223, | Aug 07 2017 | Apple Inc.; Apple Inc | Methods and apparatus for scheduling time sensitive operations among independent processors |
| 10551902, | Nov 10 2016 | Apple Inc.; Apple Inc | Methods and apparatus for providing access to peripheral sub-system registers |
| 10551906, | Oct 08 2014 | Apple Inc. | Methods and apparatus for running and booting inter-processor communication link between independently operable processors |
| 10552352, | Jun 12 2015 | Apple Inc. | Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link |
| 10572390, | Feb 29 2016 | Apple Inc | Methods and apparatus for loading firmware on demand |
| 10585699, | Jul 30 2018 | Apple Inc.; Apple Inc | Methods and apparatus for verifying completion of groups of data transactions between processors |
| 10591976, | Nov 10 2016 | Apple Inc.; Apple Inc | Methods and apparatus for providing peripheral sub-system stability |
| 10684670, | Oct 08 2014 | Apple Inc. | Methods and apparatus for managing power with an inter-processor communication link between independently operable processors |
| 10719376, | Aug 24 2018 | Apple Inc. | Methods and apparatus for multiplexing data flows via a single data structure |
| 10775871, | Nov 10 2016 | Apple Inc.; Apple Inc | Methods and apparatus for providing individualized power control for peripheral sub-systems |
| 10789198, | Jan 09 2018 | Apple Inc. | Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors |
| 10841880, | Jan 27 2016 | Apple Inc. | Apparatus and methods for wake-limiting with an inter-device communication link |
| 10845868, | Oct 08 2014 | Apple Inc. | Methods and apparatus for running and booting an inter-processor communication link between independently operable processors |
| 10846224, | Aug 24 2018 | Apple Inc | Methods and apparatus for control of a jointly shared memory-mapped region |
| 10846237, | Feb 29 2016 | Apple Inc. | Methods and apparatus for locking at least a portion of a shared memory resource |
| 10853272, | Mar 31 2016 | Apple Inc. | Memory access protection apparatus and methods for memory mapped access between independently operable processors |
| 11068326, | Aug 07 2017 | Apple Inc. | Methods and apparatus for transmitting time sensitive data over a tunneled bus interface |
| 11176064, | May 18 2018 | Apple Inc. | Methods and apparatus for reduced overhead data transfer with a shared ring buffer |
| 11176068, | Jun 12 2015 | Apple Inc. | Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link |
| 11314567, | Aug 07 2017 | Apple Inc. | Methods and apparatus for scheduling time sensitive operations among independent processors |
| 11347567, | Aug 24 2018 | Apple Inc. | Methods and apparatus for multiplexing data flows via a single data structure |
| 11558348, | Sep 26 2019 | Apple Inc. | Methods and apparatus for emerging use case support in user space networking |
| 11606302, | Jun 12 2020 | Apple Inc. | Methods and apparatus for flow-based batching and processing |
| 11652728, | Sep 24 2021 | ARISTA NETWORKS, INC | Traffic loss avoidance in a border gateway protocol (BGP) network via flexible session tracking |
| 11775359, | Sep 11 2020 | Apple Inc. | Methods and apparatuses for cross-layer processing |
| 11792307, | Mar 28 2018 | Apple Inc | Methods and apparatus for single entity buffer pool management |
| 11799986, | Sep 22 2020 | Apple Inc. | Methods and apparatus for thread level execution in non-kernel space |
| 11809258, | Nov 10 2016 | Apple Inc. | Methods and apparatus for providing peripheral sub-system stability |
| 11824962, | Mar 28 2018 | Apple Inc. | Methods and apparatus for sharing and arbitration of host stack information with user space communication stacks |
| 11829303, | Sep 26 2019 | Apple Inc. | Methods and apparatus for device driver operation in non-kernel space |
| 11843683, | Mar 28 2018 | Apple Inc | Methods and apparatus for active queue management in user space networking |
| 11876719, | Jul 26 2021 | Apple Inc | Systems and methods for managing transmission control protocol (TCP) acknowledgements |
| 11882051, | Jul 26 2021 | Apple Inc. | Systems and methods for managing transmission control protocol (TCP) acknowledgements |
| Patent | Priority | Assignee | Title |
| 5943507, | Dec 22 1994 | Texas Instruments Incorporated | Interrupt routing circuits, systems and methods |
| 6553446, | Sep 29 1999 | Hewlett Packard Enterprise Development LP | Modular input/output controller capable of routing packets over busses operating at different speeds |
| 6948004, | Mar 28 2001 | Intel Corporation | Host-fabric adapter having work queue entry (WQE) ring hardware assist (HWA) mechanism |
| 7100020, | May 08 1998 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Digital communications processor |
| 7941682, | May 09 2007 | Gainspan, Inc. | Optimum power management of system on chip based on tiered states of operation |
| 8255725, | Apr 28 2009 | Kabushiki Kaisha Toshiba | Information processing apparatus and power-saving control method |
| 8352624, | Apr 18 2002 | ARDENCE DELAWARE, INC | System for and method of streaming data to a computer in a network |
| 8656228, | Jun 23 2010 | International Business Machines Corporation | Memory error isolation and recovery in a multiprocessor computer system |
| 8788822, | Jun 10 2005 | CA, INC | Enhanced QoS solution for thin client or remote access sessions |
| 20020169938, | |||
| 20050285862, | |||
| 20070070997, | |||
| 20100017655, | |||
| 20100098419, | |||
| 20110219208, | |||
| 20110320861, | |||
| 20150378737, | |||
| 20160364350, | |||
| FRP3013008, | |||
| JP2013246642, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Sep 16 2015 | Apple Inc. | (assignment on the face of the patent) | / | |||
| Jan 05 2016 | PULYALA, RADHA KUMAR | Apple Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 037636 | /0672 | |
| Jan 05 2016 | GARG, SAURABH | Apple Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 037636 | /0672 | |
| Jan 05 2016 | SANGHI, KARAN | Apple Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 037636 | /0672 |
| Date | Maintenance Fee Events |
| May 12 2021 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Date | Maintenance Schedule |
| Nov 28 2020 | 4 years fee payment window open |
| May 28 2021 | 6 months grace period start (w surcharge) |
| Nov 28 2021 | patent expiry (for year 4) |
| Nov 28 2023 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Nov 28 2024 | 8 years fee payment window open |
| May 28 2025 | 6 months grace period start (w surcharge) |
| Nov 28 2025 | patent expiry (for year 8) |
| Nov 28 2027 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Nov 28 2028 | 12 years fee payment window open |
| May 28 2029 | 6 months grace period start (w surcharge) |
| Nov 28 2029 | patent expiry (for year 12) |
| Nov 28 2031 | 2 years to revive unintentionally abandoned end. (for year 12) |