Disclosed is a fractional bandgap circuit and method to provide a same reference voltage value in a variety of circumstances of operation, including variations in manufacturing process, temperature, and a supply voltage. The disclosed fractional bandgap circuit and method also allows for low supply voltage operation within a compact layout area.
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1. A reference voltage generating circuit comprising:
a first servo loop comprising a first p-n junction with a first current density and a second p-n junction with a second current density different than the first current density, the first p-n junction providing a first voltage, the first servo loop outputting a first proportional to absolute temperature (ptat) current and a second ptat current;
a second servo loop to receive the first voltage provided at the first p-n junction of the first servo loop to output a first complementary to absolute temperature (ctat) current; and
a resistor coupled to ground and to the first servo loop to receive the first ptat current, wherein the resistor is coupled to the second servo loop to receive the first ctat current, wherein a voltage across the resistor is a reference voltage output, wherein the first servo loop is a ptat servo loop and the second servo loop is a ctat servo loop, wherein the second servo loop is to output a second ctat current, wherein the first ptat current and the first ctat current are combined to generate a first output current having a temperature dependence according to a configurable ratio, and wherein the second ctat current and the second ptat current are combined to generate a second output current that is temperature independent.
8. A method for providing a reference voltage, the method comprising:
generating a first proportional to absolute temperature (ptat) current and a second ptat current using a first servo loop comprising a first p-n junction and a second p-n junction; the first p-n junction providing a first voltage;
generating a first complementary to absolute temperature (ctat) current using a second servo loop, the second servo loop receiving the first voltage provided at the first p-n junction of the first servo loop to output the first ctat current, wherein the first servo loop is a ptat servo loop and the second servo loop is a ctat servo loop, and wherein the second servo loop is to output a second ctat current;
outputting the reference voltage from a resistor coupled to the first servo loop, the second servo loop, and to ground, wherein the resistor is coupled to the first servo loop to receive the first ptat current and wherein the resistor is coupled to the second servo loop to receive the first ctat current; and
combining the first ptat current and the first ctat current to generate a first output current having a temperature dependence according to a configurable ratio, wherein the second ctat current and the second ptat current are combined to generate a second output current that is temperature independent.
2. The reference voltage generating circuit of
a regulated ctat current source coupled to the second servo loop and an other circuit to compensate for a ptat dependence of the other circuit.
3. The reference voltage generating circuit of
a regulated ptat current source coupled to the first servo loop and an other circuit to compensate for a ctat dependence of the other circuit.
4. The reference voltage generating circuit of
5. The reference voltage generating circuit of
a single capacitor; and
two transistors coupled to the single capacitor.
6. The reference voltage generating circuit of
a gain boost servo loop with current mirroring coupled to the first servo loop to increase output accuracy.
7. The reference voltage generating circuit of
a plurality of resistors arranged in a flipped U-shaped configuration.
9. The method of
connecting a regulated ctat current source to the second servo loop and an other circuit to compensate for a ptat dependence of the other circuit.
10. The method of
connecting a regulated ptat current source to the first servo loop and an other circuit to compensate for a ctat dependence of the other circuit.
11. The method of
determining the reference voltage output according to a metal composition of the resistor, or an analog mux.
12. The method of
initializing from a start-up circuit coupled to the first servo loop, the start-up circuit comprising a single capacitor and two transistors coupled to the single capacitor.
13. The method of
mirroring current with a gain boost servo loop coupled to the first servo loop to increase output accuracy.
14. The method of
a plurality of resistors arranged in a flipped U-shaped configuration.
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This application claims priority under 35 U.S.C. § 119 to Chinese Patent Application No. 201510523798.2 filed on Aug. 24, 2015.
Low power, small size electronic components have benefits in a wide variety of consumer products. From radio-frequency identification (RFID) to mobile devices such as smartphones, manufacturers are constantly pursuing lower power consumption and smaller footprint designs for all of their electronic components.
One such component used in electronic devices is the bandgap reference circuit. Bandgap reference circuits are typically used to produce temperature independent reference voltages. Typical bandgap reference circuits may have supply requirements of at least 1.8 V. Attempts to provide designs to utilize less than 1.8V typically require three p-n junctions or the circuit may have three possible stable states. However, low power three p-n junction bandgap reference circuits are more expensive and complex to manufacture compared to higher power two p-n junction bandgap reference circuits. Therefore, manufacturers must make a tradeoff in design for power versus size and cost.
Additionally, a three-state design creates added complexity when designing and implementing a proper start-up circuit in comparison to start up circuits which may be used with a two state bandgap circuit design.
Therefore improved bandgap reference circuits are needed which can have low power usage as well as an efficient footprint.
In one embodiment, a reference voltage generating circuit includes a first servo loop (e.g., a PTAT servo loop) comprising a first p-n junction with a first current density and a second p-n junction with a second current density different than the first current density, a second servo loop (e.g., a CTAT servo loop) shares the first or the second p-n junction of the first servo loop, and a resistor coupled to the two servo loops and ground, wherein the voltage across the resistor is the reference voltage output.
In other embodiments, the reference voltage generating circuit includes a start-up circuit to ensure operation in a desired stable state and a gain-boost technique of current mirroring that achieves operation at a low supply voltage.
In another embodiment, the current from the PTAT servo loop and the current from the CTAT servo loop are combined in a configurable ratio, wherein the configurable ratio determines one or more of: a regulated temperature independent current, a canceling of temperature dependence of the resistor, or a regulated current source with a configurable temperature dependence.
In another embodiment, a method for provides a reference voltage. The method may include generating a first current with a first servo loop comprising a first p-n junction. The method may also include generating a second current with a second p-n junction, wherein a second servo loop is connected to one of the first or the second p-n junctions of the first servo loop. The method may also include outputting the reference voltage from a resistor coupled to the two servo loops and ground.
The above and other aspects, objects, and features of the present disclosure will become apparent from the following description of various embodiments, given in conjunction with the accompanying drawings.
The word “exemplary” or “example” is used herein to mean “serving as an example, instance, or illustration.” Any aspect or embodiment described herein as “exemplary” or as an “example” is not necessarily to be construed as preferred or advantageous over other aspects or embodiments.
In one embodiment, a reference voltage generating circuit is described herein as a fractional bandgap circuit (referred to herein simply as “FBC”) to provide a low-current, low-voltage, and temperature independent reference output. In one embodiment, the FBC implements two servo loops, a first of which produces a current that is proportional to absolute temperature (PTAT) and a second that produces a current that is complementary to absolute temperature (CTAT). The two servo loops may be combined with a resistor having a voltage independent of temperature. In one embodiment, the CTAT and PTAT are ratioed such that the temperature dependence of the voltage independent resistor is cancelled and the FBC has little to no temperature dependence.
In one embodiment, the FBC generates a first current PTAT with a first servo loop using two p-n junctions of differing current density. Unlike other bandgap circuit designs utilizing three p-n junctions, the FBC described herein utilizes two p-n junctions which saves area during manufacturing and can leverage lower cost wafer processing.
In one embodiment, a gain boost servo loop is connected with the PTAT servo loop to allow accurate mirroring at low supply voltage. In one embodiment, a third servo loop, without utilizing a third p-n junction, uses the voltage at one of the first two p-n junctions to generate a second current complementary to absolute temperature (CTAT). Current mirrors that replicate the internal current of the CTAT servo loop do not need a servo to allow accurate mirroring at low supply voltage. The mirrored PTAT and CTAT currents may be combined in a resistor to ground, to generate an output voltage that is a fixed fraction of the silicon bandgap voltage. In one embodiment, the output voltage is independent of process, temperature and supply voltage. Trimming techniques (e.g., with spare resistors or current mirrors, or both), may be added to allow trimming to a very accurate level if desired. Other trimming techniques known to those skilled in the art are also possible.
In some embodiments, the mirrored PTAT and CTAT currents are not equal and are opposite in temperature dependence. The output resistor of the FBC may have some known temperature dependence and the mirrored PTAT and CTAT currents that generate the fixed output reference voltage may be ratioed so that the temperature dependence of the combined currents accurately compensates for that of the output resistor. For example, if the temperature dependence of the output resistor were negative, the ratio of currents may be adjusted to compensate for that dependence by having additional PTAT current. The resulting fractional bandgap output voltage will be temperature-independent.
In some embodiments, two additional mirrored currents are summed to create a regulated, temperature-independent current. For example, by using two contributing currents of equal but opposite temperature coefficient. In some embodiments, the temperature-independent current is used with further mirroring to provide a regulated temperature-independent bias current utilized by the internal components of the design to maintain accurate performance and reliable circuit behavior. In addition, by still further mirroring, that current is used to generate and provide multiple regulated temperature-independent currents which may be used by other circuits outside the fractional bandgap.
In one embodiment, the CTAT current may be further mirrored to provide a regulated CTAT current source for an other circuit to use, to compensate for the PTAT dependence of those other circuits. In another embodiment, the PTAT current can be further mirrored to provide a regulated PTAT current source for use in other circuits, to compensate for the CTAT dependence of those other circuits. For example, a thermometer circuit may benefit from the regulated PTAT current source because a thermometer circuit may depend on the PTAT loop for the proportional to absolute temperature readings as well as the overall bandgap reference voltage.
In one embodiment, one mirrored PTAT current and one mirrored CTAT current may be ratioed as desired and combined to generate a current of any temperature-dependence, over a wide range, which may be needed for still other circuits. For example, a wide range might be −40 to 100° C. A “narrow” range of interest might be the temperature inside a meat storage unit where one wants to know the temperature, for example between −2 and +6° C., to an accuracy of 0.25° C. Other implementations or ranges are also possible within the scope of the embodiments described herein.
The FBC described herein may have two stable states, which enables use with a wide variety of two state compatible start-up circuits. In one embodiment, the FBC assumes either of two stable states, and a novel start-up circuit is provided to ensure that the circuit enters the desirable stable state. The start-up circuit can include a small capacitor and two transistors and may be manufactured with a low area low cost circuit. In one embodiment, FBC uses the described start-up circuit to initialize with zero current after startup. Further details of this start-up circuit are described below with regards to
In one embodiment, a U-shaped resistor element layout technique achieves high resistance in small area by flipping resistor elements. As introduced above, minimizing the size of a circuit is highly beneficial for real world applications in electronic components. For bandgap circuits, resistors may take up a large percentage of the total area of the circuit. In one embodiment, the high density layout is achieved by using alternately-flipped “U-shaped” resistor elements to use minimum spacing across the length of the resistor. Further details of this resistor element layout are described below with regards to
The sum of the two currents into R0 may not be independent of temperature. Rather, the two currents may be setup with a ratio to have a temperature-dependence complementary to that of R0, a high-resistivity (e.g., 1000 Ω/sq. or other resistance) resistor (e.g., a poly-silicon resistor). On the other hand, the two currents summed to create iZtc, a temperature independent current, are of equal but opposite temperature coefficient. In some embodiments, R0 is made up of many small identical resistor elements in series.
In one embodiment, the current from the PTAT servo loop and the current from the CTAT servo loop are combined in a configurable ratio. The configurable ratio determines (i.e., can be used to modify or affect) one or more of: a regulated temperature independent current, a canceling of temperature dependence of the resistor, or a regulated current source with a configurable temperature dependence.
In one embodiment, the illustrated PTAT servo-loop adjusts elemental currents of M1 and M2 so that the voltage on the node q1 215 (VBE1) is equal to the voltage on eq1 220, which is the voltage across the series combination of R1 225 and Q2 210. Thus the voltage across R1 225 is represented by ΔVBE, equal to the difference between the VBE voltages on Q1 205 and Q2 210. Given the Shockley relation:
and the current density ratio γ, this voltage difference between Q1 205 and Q2 210 is:
absolute temperature multiplied by a constant, and the resistor current is thus (ΔVBE)/R1, or
Thus me currents of the resistor and of the current sources are PTAT. Voltages VBE1 and VBE2 on Q1 205 and Q2 210 are CTAT, complementary to absolute temperature, given a PTAT current.
In one embodiment, R1 225 is made up of segments of identical resistor elements. The R1 225 resistor elements may be identical to, and common-centroided with, those elements in the main R0 130 resistor used for the vBgf output voltage 150.
In one embodiment, the currents through M1 230 and M2 235 are at a constant ratio of m1/m2. This ratio is very accurate when the loop is in regulation, since the drain voltages are then very nearly equal, along with the source, gate and body terminals being tied together. The currents are PTAT, since the M2 235 current equals the R1 225 current. In one embodiment, currents through M1 230 and M2 235 are mirrored in a fixed ratio through two additional transistors, M3 240 and M3B 245, to provide two PTAT currents from this module (e.g., as illustrated in
In one embodiment, the R2 305 resistor illustrated in
The expression
is a full bandgap expression that is unaffected by the choice of R0. The values for A, B, R2 and R1 are such that the total voltage in
is temperature independent. In one embodiment, the final value of the fractional bandgap output is a fixed fraction of a full bandgap voltage.
In one embodiment, the magnitude of vBgf 405 may be configured according to the number of resistor elements that make up R0 410. For example, the value of vBgf may be configured by tapping off the output from the R0 410 resistor stack (e.g., with additional optional resistor elements) by an analog mux or by metal options (e.g., the amount or configuration of the metal composition) in an integrated circuit fabrication mask. For example, if the FBC is configured to produce a fractional bandgap voltage of around 365 mV, equally valid fractional bandgap voltages may be created by tapping off the resistor R0 410.
In one embodiment, the R0 410 resistor used to determine the final magnitude of the fractional bandgap output (e.g., as illustrated in
The gain-boost loop illustrated in
In yet other embodiments, a similar gain boost mechanism is added to the CTAT servo loop, however the accuracy is not as affected at some voltages (e.g., around 700 mV) compared to the PTAT servo loop because the drain/source voltage of M4 310 will not be nearly as low as for M1 230 and M2 235. Therefore, q2 may be used as the reference for the CTAT servo loop rather than q1, which would be a higher voltage. Additionally, a higher reference voltage would require a combination of a larger R2 or greater resistor current, neither of which is to be desired. Accordingly, in some embodiments, the lower q2 voltage is utilized as the preferred reference for the CTAT servo loop. As an illustrated example using the example characteristics introduced for the FBC of
Also, other currents can be generated that are proportional to absolute temperature, as by M3C, or complementary to absolute temperature, as by M5C, for use in other circuits on the same chip, which may need such currents for temperature compensation or other purposes.
In one embodiment, adding another PTAT transistor, for example M3C, with biasPtat on the gate, will create the PTAT current 680 from bandgap circuit 640. Such a PTAT current could simply go through a resistor to ground. Since the current is simply a multiple of I2 (i.e., I2 of
In one embodiment, the startup circuit is implemented for the q1 and eq1 of the PTAT servo loop 200. For example, startup circuit 700 may be coupled to the upper op amp of
In one embodiment, the FBC with startup circuit utilizes a bias current for the op amps. For example, the FBC itself may be used to generate this bias current. The startup circuit provides the initial bias current by pulling down the gates of the current sources in the two loops, as discussed above. Thus those sources will provide initial current to the biasN node (and to the diode-connected nMos transistor). Once the bandgap circuit stabilizes, including both the PTAT and CTAT servo loops, the biasN node is at a stable voltage and the needed bias currents will thus be generated in the op amps.
It should be noted that this provision for the bias currents just described constitutes a feedback loop itself in the bandgap circuit as a whole. This added loop (and all feedback loops in the bandgap circuit) should be ensured to be stable as usual, as is understood by those practiced in the art.
The FBC resistors may use many elements to allow common-centroiding, and reasonable resolution for choosing values for the desired resistor ratios. The resistor element size may be determined as a small fraction of the total resistance of any of the three main resistors discussed above (e.g., R1, R2, and R0). The layout of the resistor element of
In one embodiment, the resistor may be connected to the FBC at input 950 and continue with a tap 955 to bring the two resistor elements together. The resistor elements of
The technique used in traditional large resister designs results in a density of 1.68 kΩ/um2. In that layout, a poly line-width of 0.6 um was used. Also the layout technique required spacing of 0.34 um, vs. a minimum spacing allowed of 0.25 um. Pushed to the same narrow poly line-width of 0.24 um, one can get 6.71 kΩ/um2. Compared with the example resistor layout of
In one embodiment, the resistors in the FBC may be laid out in a common-centroid arrangement of numerous smaller resistor elements to maintain maximum matching accuracy in the resistor ratios. For example, three resistors, R0, R1, and R2 may be arranged in a sequence of: [R0 R1 R2 R0 R1 R1 R0 R2 R1 R0], where the four R0 elements would be connected in series, with the geometric center of them in the center of the arrangement. The four R1 elements above would also be connected in series, with the geometric center of them also in the center of the arrangement. The two R2 elements above would be connected in series, with the geometric center of them also in the center of the arrangement. The ratio of the resistance of this example common-centroid arrangement above R0:R1:R2 would be 2:2:1. A common-centroid arrangement may guard against a linear variation in the resistor value as a function of position. This variation would average out with a presumption that the metal connecting the resistor elements is of negligible resistance.
At block 1010, the embodiment generates, within the reference voltage generating circuit, a first current with a first servo loop including a first p-n junction. For example, the first servo loop may be a PTAT servo loop (e.g., PTAT servo loop 110).
At block 1015, the embodiment generates, within the reference voltage generating circuit, a second current with a second p-n junction, where a second servo loop shares the first or the second p-n junction of the first servo loop. For example, the second servo loop may be a CTAT servo loop (e.g., CTAT servo loop 120).
At block 1020, the embodiment mirrors current from the reference voltage generating circuit with a gain boost servo loop. For example, the gain boost servo loop as illustrated in
At block 1025, the embodiment outputs reference voltage of the reference voltage generating circuit using a resistor coupled to the first servo loop, second servo loop, and to ground. In some embodiments, the voltage is determined according to metal composition of the resistor, or an analog mux.
The foregoing discussion merely describes some exemplary embodiments of the present invention. One skilled in the art will readily recognize from such discussion, the accompanying drawings and the claims that various modifications can be made without departing from the spirit and scope of the invention.
Additionally, in the above drawings of the embodiments, signals may be represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediary devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” means at least one current signal, voltage signal or data/clock signal. The meaning of “a”, “an”, and “the” include plural references. The meaning of “in” includes “in” and “on”.
As used herein, unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. The term “substantially” herein refers to being within 10% of the target.
For purposes of the embodiments described herein, unless otherwise specified, the transistors are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. Source and drain terminals may be identical terminals and are interchangeably used herein. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors—BJT PNP/NPN, BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.
Wang, Steve, Schnaitter, William
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