In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.
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11. A silicon carbide semiconductor device comprising:
a first epitaxial layer of a first conductivity type, formed on a front surface of a silicon carbide substrate;
a first semiconductor region of a second conductivity type, selectively formed in the first epitaxial layer;
a second semiconductor region of the first conductivity type, selectively formed in the first epitaxial layer at a depth shallower than the first semiconductor region;
a trench that penetrates the second semiconductor region and the first semiconductor region, and reaches a portion of the first epitaxial layer deeper than the first semiconductor region;
a gate insulating film provided in the trench;
a gate electrode provided in the trench, and surrounded in the trench by the gate insulating film;
a first electrode that contacts the second semiconductor region and the first epitaxial layer; and
a second electrode provided on a rear surface of the silicon carbide substrate, wherein
the first semiconductor region has a second-conductivity-type impurity concentration profile in which concentration differences in a depth direction form a plurality of bell-shaped curves at a plurality of peaks.
1. A silicon carbide semiconductor device comprising:
a first epitaxial layer of a first conductivity type, formed on a front surface of a silicon carbide substrate;
a second epitaxial layer of a second conductivity type, formed on an opposite side of the first epitaxial layer from the silicon carbide substrate;
a first semiconductor region of the second conductivity type selectively formed in the second epitaxial layer, the first semiconductor region having an impurity concentration that is higher than that of an adjacent portion of the second epitaxial layer;
a second semiconductor region of the first conductivity type, selectively formed in the second epitaxial layer at a position shallower than the first semiconductor region;
a trench that penetrates the second semiconductor region, the first semiconductor region, and the adjacent portion of the second epitaxial layer, and reaches the first epitaxial layer;
a gate insulating film provided in the trench;
a gate electrode provided in the trench, and surrounded in the trench by the gate insulating film;
a first electrode that contacts the second semiconductor region and the adjacent portion of the second epitaxial layer; and
a second electrode provided on a rear surface of the silicon carbide substrate, wherein
the first semiconductor region has a second-conductivity-type impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration higher than that of the adjacent portion of the second epitaxial layer.
2. The silicon carbide semiconductor device according to
the concentration differences in the depth direction of the second-conductivity-type impurity concentration profile of the first semiconductor region form a plurality of bell-shaped curves at a plurality of peaks of impurity concentration higher than that of the adjacent portion of the second epitaxial layer.
3. The silicon carbide semiconductor device according to
in the second-conductivity-type impurity concentration profile, the impurity concentration sharply decreases at a border of the second epitaxial layer and the first epitaxial layer.
4. The silicon carbide semiconductor device according to
the peak of the impurity concentration of the second-conductivity-type impurity concentration profile is positioned farther on a first electrode side than a border of the second epitaxial layer and the first epitaxial layer.
5. The silicon carbide semiconductor device according to
the first semiconductor region is provided uniformly in a direction parallel to the front surface of the silicon carbide substrate.
6. The silicon carbide semiconductor device according to
a third semiconductor region of the first conductivity type and formed in the first epitaxial layer, the third semiconductor region having an impurity concentration higher than that of an adjacent portion of the first epitaxial layer, wherein
the third semiconductor region contacts the second epitaxial layer and, from a border with the second epitaxial layer, reaches a position deeper on a second electrode side than a bottom of the trench.
7. The silicon carbide semiconductor device according to
a fourth semiconductor region of the second conductivity type, selectively formed in the third semiconductor region, the fourth semiconductor region covering the bottom of the trench.
8. The silicon carbide semiconductor device according to
the fourth semiconductor region penetrates the third semiconductor region from the bottom of the trench in the depth direction.
9. The silicon carbide semiconductor device according to
a fifth semiconductor region of the second conductivity type, formed in the third semiconductor region between the trench and an adjacent trench so as to contact the second epitaxial layer.
10. The silicon carbide semiconductor device according to
the fifth semiconductor region penetrates the third semiconductor region in the depth direction.
12. The silicon carbide semiconductor device according to
among a plurality of peaks, the impurity concentration at a first peak on a first electrode side is higher than that of a second peak on a second electrode side.
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This application is based upon and claims the benefit of priority of the prior Japanese Patent Application Nos. 2016-017568 filed on Feb. 1, 2016, and 2016-165172 filed on Aug. 25, 2016, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
Embodiments of the invention relate to a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Related Art
Silicon carbide (SiC) is anticipated to be a next generation semiconductor material of silicon (Si). Compared to conventional semiconductor devices using Si as a material, semiconductor devices using silicon carbide (hereinafter, silicon carbide semiconductor device) have various advantages such as reducing device resistivity in the ON state to several hundredths and use in environments of high temperatures (200 degrees C. or more). Such advantages are enabled by characteristics of the material itself such as the bandgap of SiC being about 3 times that of Si and the dielectric breakdown field strength being nearly 10 times that of Si.
Schottky barrier diodes (SBD) and planar vertical metal oxide semiconductor field effect transistors (MOSFET) have become commercial SiC semiconductor devices.
A trench gate structure is a 3-dimensional structure in which a metal oxide semiconductor (MOS) gate (MOS insulated gate) is embedded in a trench formed in a semiconductor base formed of silicon carbide (hereinafter, silicon carbide base) and a portion along a trench side wall is used as a channel (inversion layer). Therefore, when the device area (chip area) is compared between devices of the same on-resistance (Ron), the device area of the trench gate structure can be made significantly smaller than that of a planar gate structure in which a MOS gate is provided in a flat shape on a silicon carbide base and thus, a trench gate structure may be considered a promising device structure.
A structure of a conventional silicon carbide semiconductor device will be described taking a vertical MOSFET of a trench gate structure as an example.
In the n-type current spreading region 103, a first p-type region 111 is selectively provided to cover a bottom of a trench 107 entirely. The first p-type region 111 is provided to a depth reaching the n−-type drift region 102. Further, a second p-type region 112 is selectively provided between adjacent trenches 107 (mesa portion), in the n-type current spreading region 103. The second p-type region 112 contacts the p-type base region 104 and is provided to a depth reaching the n−-type drift region 102. Reference numerals 105, 106, 108, 109, and 113 to 115 are an n+-type source region, a p++-type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode, respectively.
As such a vertical MOSFET of a trench gate structure, a device has been proposed that includes a p-type base layer of a 2-layer structure having p-type semiconductor layers of differing impurity concentrations, sequentially formed by epitaxial growth (for example, refer to Japanese Patent Application Laid-Open Publication No. 2012-099601 (paragraph 0030, FIG. 1) and Japanese Patent Application Laid-Open Publication No. 2015-072999 (paragraph 0060, FIG. 9)). In Japanese Patent Application Laid-Open Publication Nos. 2012-099601 and 2015-072999, among the p-type semiconductor layers forming the p-type base layer, punch-through is suppressed at the p-type semiconductor layer of the higher impurity concentration and the on-resistance is reduced at the p-type semiconductor layer of the lower impurity concentration. Further, a technique of implanting impurity ions (p-type) such as aluminum (Al) ions, boron (B) ions, etc. on a top surface of an n-type semiconductor layer in a vertical MOSFET of a trench gate structure to form the p-type semiconductor layer has been proposed (for example, refer to Japanese Patent Application Laid-Open Publication No. 2014-241435 (paragraph 0028)).
A silicon carbide semiconductor device according to one aspect of the present invention includes a first epitaxial layer of a first conductivity type, formed on a front surface of a silicon carbide substrate; a second epitaxial layer of a second conductivity type, formed on an opposite side of the first epitaxial layer from a silicon carbide substrate side thereof; a first semiconductor region of the second conductivity type and selectively formed in the second epitaxial layer, the first semiconductor region having an impurity concentration that is higher than that of the second epitaxial layer; a second semiconductor region of the first conductivity type, selectively formed in the second epitaxial layer at a position shallower than the first semiconductor region; a trench that penetrates the second semiconductor region, the first semiconductor region, and the second epitaxial layer, and reaches the first epitaxial layer; a gate electrode provided in the trench, via a gate insulating film; a first electrode that contacts the second semiconductor region and the second epitaxial layer; and a second electrode provided on a rear surface of the silicon carbide substrate. The first semiconductor region has a second-conductivity-type impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration higher than that of the second epitaxial layer.
In the silicon carbide semiconductor device, the first semiconductor region has the second-conductivity-type impurity concentration profile in which the concentration differences in the depth direction form a plurality of bell-shaped curves at a plurality of peaks of impurity concentration higher than that of the second epitaxial layer.
In the silicon carbide semiconductor device, in the second-conductivity-type impurity concentration profile, the impurity concentration sharply decreases at a border of the second epitaxial layer and the first epitaxial layer.
In the silicon carbide semiconductor device, the peak of the impurity concentration of the second-conductivity-type impurity concentration profile is positioned farther on a first electrode side than the border of the second epitaxial layer and the first epitaxial layer.
In the silicon carbide semiconductor device, the first semiconductor region is provided uniformly in a direction parallel to the front surface of the silicon carbide substrate.
The silicon carbide semiconductor device includes a third semiconductor region of the first conductivity type and formed in the first epitaxial layer, the third semiconductor region having an impurity concentration higher than that of the first epitaxial layer. The third semiconductor region contacts the second epitaxial layer and from a border with the second epitaxial layer, reaches a position deeper on a second electrode side than a bottom of the trench.
The silicon carbide semiconductor device includes a fourth semiconductor region of the second conductivity type, selectively formed in the third semiconductor region, the fourth semiconductor region covering the bottom of the trench.
In the silicon carbide semiconductor device, the fourth semiconductor region penetrates the third semiconductor region from the bottom of the trench in the depth direction.
The silicon carbide semiconductor device includes a fifth semiconductor region of the second conductivity type, formed in the third semiconductor region between the trench and an adjacent trench so as to contact the second epitaxial layer.
In the silicon carbide semiconductor device, the fifth semiconductor region penetrates the third semiconductor region in the depth direction.
A silicon carbide semiconductor device according to another aspect includes a first epitaxial layer of a first conductivity type, formed on a front surface of a silicon carbide substrate; a first semiconductor region of a second conductivity type, selectively formed in the first epitaxial layer; a second semiconductor region of the first conductivity type, selectively formed in the first epitaxial layer at a position shallower than the first semiconductor region; a trench that penetrates the second semiconductor region and the first semiconductor region, and reaches the first epitaxial layer; a gate electrode provided in the trench, via a gate insulating film; a first electrode that contacts the second semiconductor region and the first epitaxial layer; and a second electrode provided on a rear surface of the silicon carbide substrate. The first semiconductor region has a second-conductivity-type impurity concentration profile in which concentration differences in a depth direction form a plurality of bell-shaped curves at a plurality of peaks.
In the silicon carbide semiconductor device, among the plurality of peaks, the impurity concentration at a first peak on a first electrode side is higher than that of a second peak on a second electrode side.
A method of manufacturing a silicon carbide semiconductor device according to another aspect of the present invention includes forming a first epitaxial layer of a first conductivity type on a front surface of a silicon carbide substrate; forming a second epitaxial layer of a second conductivity type on the first epitaxial layer; selectively forming a first semiconductor region of the second conductivity type by ion implantation in the second epitaxial layer, the first semiconductor region having an impurity concentration higher than that of the second epitaxial layer; selectively forming a second semiconductor region of the first conductivity type in the second epitaxial layer, at a position shallower than the first semiconductor region; forming a trench to penetrate the second semiconductor region, the first semiconductor region, and the second epitaxial layer, and reach the first epitaxial layer; forming a gate electrode in the trench, via a gate insulating film; forming a first electrode contacting the second semiconductor region and the second epitaxial layer; and forming a second electrode on a rear surface of the silicon carbide substrate. The first semiconductor region is formed to have a second-conductivity-type impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration higher than that of the second epitaxial layer.
In the method of manufacturing a silicon carbide semiconductor device, the first semiconductor region is formed by a plurality of stages of ion implantation to have the second-conductivity-type impurity concentration profile in which the concentration differences in the depth direction form a plurality of bell-shape curves at a plurality of peaks of impurity concentration higher than that of the second epitaxial layer.
In the method of manufacturing a silicon carbide semiconductor device, the ion implantation is performed using an accelerating voltage so that the peak of the impurity concentration in the second-conductivity-type impurity concentration profile is formed at a position deeper than an ion implantation surface.
The method of manufacturing a silicon carbide semiconductor device includes forming a third epitaxial layer of the second conductivity type on the second epitaxial layer after forming the first semiconductor region and before forming the second semiconductor region.
In the method of manufacturing a silicon carbide semiconductor device, the ion implantation is performed using an accelerating voltage so that the peak of the impurity concentration in the second-conductivity-type impurity concentration profile is formed at a position equal to or deeper than an ion implantation surface.
In the method of manufacturing a silicon carbide semiconductor device, the ion implantation is performed using an accelerating voltage so that the peak of the impurity concentration in the second-conductivity-type impurity concentration profile is formed at a depth position farther on a first electrode side than a border of the second epitaxial layer and the first epitaxial layer.
A method of manufacturing a silicon carbide semiconductor device according to one aspect of the present invention includes forming a first epitaxial layer of a first conductivity type on a front surface of a silicon carbide substrate; selectively forming a first semiconductor region of a second conductivity type in the first epitaxial layer by ion implantation; selectively forming a second semiconductor region of the first conductivity type in the first epitaxial layer, at a position shallower than the first semiconductor region; forming a trench to penetrate the second semiconductor region and the first semiconductor region, and reach the first epitaxial layer; forming a gate electrode in the trench, via a gate insulating film; forming a first electrode contacting the second semiconductor region and the first epitaxial layer; and forming a second electrode on a rear surface of the silicon carbide substrate. The first semiconductor region is formed by a plurality of stages of ion implantation to have a second-conductivity-type impurity concentration profile in which concentration differences in a depth direction form a plurality of bell-shape curves at a plurality of peaks.
In the method of manufacturing a silicon carbide semiconductor device, the first semiconductor region is formed to have the second-conductivity-type impurity concentration profile in which among the plurality of peaks, an impurity concentration at a first peak on a first electrode side is higher than that at a second peak on a second electrode side.
Objects, features, and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings.
Embodiments of a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or − appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without +or −. In the description of the embodiments below and the accompanying drawings, identical constituent elements will be given the same reference numerals and will not be repeatedly described.
The semiconductor device according to the present invention is configured using a semiconductor material (hereinafter, wide bandgap semiconductor) having a wider bandgap than silicon. A structure of a semiconductor device (silicon carbide semiconductor device) using silicon carbide (SiC) as the wide bandgap semiconductor will be described as an example.
The silicon carbide base 10 is formed by sequentially growing on an n+-type supporting substrate (n+-type silicon carbide substrate) 1 formed of silicon carbide, silicon carbide layers (first and second epitaxial layers) 21, 22 that become an n−-type drift region 2 and the p-type base region 4. Each MOS gate is configured by the p-type base region 4, an n+-type source region (second semiconductor region) 5, a p++-type contact region 6, a trench 7, a gate insulating film 8, and a gate electrode 9. In particular, in a surface layer of a source side (a source electrode 16) of the n−-type silicon carbide layer 21, an n-type region (hereinafter, n-type current spreading region (third semiconductor region)) 3 is provided so as to contact the p-type base region 4. The n-type current spreading region 3 is a so-called current spreading layer (CSL) that reduces carrier spreading resistance. The n-type current spreading region 3, for example, is provided uniformly in a direction (hereinafter, horizontal direction) parallel to a base front surface (a front surface of the silicon carbide base 10). Although the n-type current spreading region 3 may be omitted, provision of the n-type current spreading region 3 enables on-resistance and breakdown voltage to be improved.
The portion of the n−-type silicon carbide layer 21 exclusive of the n-type current spreading region 3 is the n−-type drift region 2. In the n-type current spreading region 3, first and second p+-type regions (fourth and fifth semiconductor regions) 11, 12 are each selectively provided. The first p+-type region 11 is provided so as to cover a bottom and a bottom corner portion of the trench 7. The bottom corner portion of the trench 7 is the boundary of a side wall and the bottom of the trench 7. The first p+-type region 11 is provided from a position deeper than an interface of the p-type base region 4 and the n-type current spreading region 3, on the drain side to a depth that does not reach an interface of the n-type current spreading region 3 and the n−-type drift region 2. Provision of the first p+-type region 11 enables formation of a pn junction between the first p+-type region 11 and the n-type current spreading region 3, near the bottom of the trench 7.
The second p+-type region 12 is provided between adjacent trenches 7 (mesa portion), away from the first p+-type region 11 and contacts the p-type base region 4. Portions of the second p+-type region 12 may extend on the trench 7 sides and partially contact the first p+-type regions 11. Further, the second p+-type region 12 is provided from the interface of the p-type base region 4 and the n-type current spreading region 3 to a depth that does not reach the interface of the n-type current spreading region 3 and the n−-type drift region 2. Provision of the second p+-type region 12 enables formation of a pn junction between the second p+-type region 12 and the n-type current spreading region 3, between the adjacent trenches 7, at a position deeper than the bottom of the trenches 7. Formation of the pn junctions by the first and second p+-type regions 11, 12 and the n-type current spreading region 3 in this manner enables application of high electric field to a trench 7 bottom portion of the gate insulating film 8 to be prevented.
In the p-type silicon carbide layer 22, the n+-type source region 5 and the p++-type contact region 6 are each selectively provided to contact each other. The depth of the p++-type contact region 6, for example, may be deeper than the n+-type source region 5. The portion of the p-type silicon carbide layer 22 exclusive of the n+-type source region 5 and the p++-type contact region 6 is the p-type base region 4. In the p-type base region 4, a p+-type region (hereinafter, high-concentration implantation region (first semiconductor region)) 13 is formed by ion implantation of a p-type impurity (hatched portion).
The high-concentration implantation region 13, for example, is provided uniformly in the horizontal direction so as to include portions of the p-type base region 4 where a channel is formed. The portions of the p-type base region 4 where the channel is formed are the portions of the p-type base region 4 along the side walls of the trench 7. Reference characters 4a and 4b are, respectively, a portion (hereinafter, the first p-type base portion) farther on the drain side than the high-concentration implantation region 13 and a portion (hereinafter, the second p-type base portion) farther on the source side than the high-concentration implantation region 13, in the p-type base region 4. The first and the second p-type base portions 4a, 4b have an impurity concentration that is lower than that of the high-concentration implantation region 13.
The first and the second p-type base portions 4a, 4b and the high-concentration implantation region 13 configure the p-type base region 4. In the portions of the first and the second p-type base portions 4a, 4b and of the high-concentration implantation region 13, along the side walls of the trenches 7, an n-type inversion layer (channel) is formed during the ON state. In
In particular, the high-concentration implantation region 13 has a p-type impurity concentration profile 31 in which concentration differences in the depth direction form a bell-shaped curve at a peak 13a of impurity concentration higher than that of the p-type silicon carbide layer 22 forming the p-type base region 4. In other words, the peak 13a of the p-type impurity concentration profile 31 is in the p-type base region 4, and the impurity concentration decreases from the position of the peak 13a, on both principal surface sides (source side and drain side) of the base by respective predetermined slopes. The depth of the position of the peak 13a of the high-concentration implantation region 13 is within a range from a position deeper than or equal to the depth of the position of the interface of the n+-type source region 5 and the p-type base region 4 and a position shallower than the depth of the position of the interface of the p-type base region 4 and the n-type current spreading region 3.
Preferably, the depth of the position of the peak 13a of the high-concentration implantation region 13 may be within a range from the interface of the n+-type source region 5 and the p-type base region 4 to a depth that is about 80% of a thickness t2 of the p-type base region 4 (=0.8×t2), and the peak 13a may be positioned within a range from the interface of the n+-type source region 5 and the p-type base region 4 to a depth that is about 10% to 70% of the thickness t2 of the p-type base region 4. The reason for this is that the tradeoff relation of reduced on-resistance and reduced variation of gate threshold voltage Vth is further improved. The thickness t2 of the p-type base region 4 is a thickness from the interface of the n+-type source region 5 and the p-type base region 4 to the interface of the p-type base region 4 and the n-type current spreading region 3.
In other words, the peak 13a of the high-concentration implantation region 13 is at a position that is shallower than the n-type current spreading region 3 with respect to the base front surface and that is away from the n-type current spreading region 3 in depth. When the depth of the position of the peak 13a of the high-concentration implantation region 13 is the depth of the position of the interface of the n+-type source region 5 and the p-type base region 4, the high-concentration implantation region 13 contacts the n+-type source region 5 and the p++-type contact region 6 whereby, the second p-type base portion 4b is not formed. The p-type impurity concentration profile resulting from ion implantation of a p-type impurity for forming the high-concentration implantation region 13 will be described in detail hereinafter.
The high-concentration implantation region 13 may have multiple impurity concentration peaks 13a at differing depths. In this case, the depths of the positions of all of the impurity concentration peaks 13a of the high-concentration implantation region 13 are within the ranges described above. Disorder in the crystal structure (for example, defects such as dislocations) occurs partially in the p-type base region 4 to a greater extent with the ion implantation for forming the high-concentration implantation region 13 than in a case of only epitaxial growth. Therefore, when the p-type base region 4 is formed by only epitaxial growth without ion implantation of an impurity (i.e., the conventional structure depicted in
The trench 7 penetrates the n+-type source region 5, the high-concentration implantation region 13, and the p-type base region 4 from the base front surface and reaches the n-type current spreading region 3. In the trench 7, the gate insulating film 8 is provided along the side walls of the trench 7 and the gate electrode 9 is provided on the gate insulating film 8. A source-side end of the gate electrode 9 may or may not protrude outwardly from the base front surface. The gate electrode 9 is electrically connected to a gate pad (not depicted) at a portion not depicted. An interlayer insulating film 14 is provided on the entire base front surface so as to cover the gate electrode 9 embedded in the trench 7.
The source electrode (first electrode) 16 contacts the n+-type source region 5 and the p++-type contact region 6 via a contact hole in the interlayer insulating film 14 and is electrically insulated from the gate electrode 9 by the interlayer insulating film 14. Between the source electrode 16 and the interlayer insulating film 14, for example, a barrier metal 15 may be provided that prevents diffusion of metal atoms from the source electrode 16 to the gate electrode 9 side. On the source electrode 16, a source pad 17 is provided. On a rear surface of the silicon carbide base 10 (rear surface of the n+-type silicon carbide substrate 1 forming the n+-type drain region), a drain electrode (second electrode) 18 is provided.
The p-type impurity concentration profile resulting from the ion implantation of a p-type impurity for forming the high-concentration implantation region 13 will be described.
As depicted in
Further, consequent to the ion implantation of a p-type impurity for forming the high-concentration implantation region 13, in the p-type silicon carbide layer 22, the p-type impurity concentration profile 31 having a peak 31a impurity concentration at a position deeper than the peak 32a of the n-type impurity concentration profile 32 from the base front surface is formed. The peak 31a of the p-type impurity concentration profile 31 is the peak 31a of the impurity concentration profile of the high-concentration implantation region 13. Further, in the p-type impurity concentration profile 31, the impurity concentration decreases on the source side and the drain side by respective predetermined slopes, from the position of the peak 31a in a bell-shaped curve. Additionally, in the p-type impurity concentration profile 31, the impurity concentration sharply decreases at an interface 30b of the p-type silicon carbide layer 22 and the n−-type silicon carbide layer 21, and the impurity concentration decreases by a predetermined slope from the interface 30b toward to drain side. The peak 31a of the impurity concentration of the p-type impurity concentration profile 31, for example, is 6×1017 atoms/cm3. In the present specification and claims, the term “sharply decreases” refers to a change in impurity concentration of between four times and ten times over a distance in depth of between 0.01 μm and 0.25 μm. According to one embodiment, as shown in
The p-type impurity concentration profile 31 such as this is obtained by performing the ion implantation of a p-type impurity for forming the high-concentration implantation region 13 after the p-type silicon carbide layer 22 forming the p-type base region 4 is formed by epitaxial growth. When the p-type base region 104 is formed by only epitaxial growth such as in the conventional structure (refer to
The impurity concentration of the p-type silicon carbide layer 22 forming the p-type base region 4, for example, may be preferably within a range of 1×1016 atoms/cm3 or more to 2×1017 atoms/cm3 or less, as within this range, effects identical to those of the above example are obtained. Further, the impurity concentration of the peak 31a of the p-type impurity concentration profile 31 may be preferably within a range of 2×1016 atoms/cm3 or more to 5×1018 atoms/cm3 or less. When the peak 31a of the impurity concentration of the p-type impurity concentration profile 31 is set to be higher than the impurity concentration of the p-type silicon carbide layer 22, effects identical to those of the above example are obtained. Although a channel length L is assumed to be 0.6 μm, configuration is not limited hereto and the channel length L may be preferably 0.3 μm or more and 1 μm or less. The channel length L is a length from the intersection 30a of the n-type impurity concentration profile 32 and the p-type impurity concentration profile 31 to the interface 30b of the p-type silicon carbide layer 22 and the n−-type silicon carbide layer 21.
The method of manufacturing a silicon carbide semiconductor device according to the first embodiment will be described.
As depicted in
Subsequently, as depicted in
As depicted in
Next, as depicted in
Next, as depicted in
Next, as depicted in
Next, as depicted in
Next, as depicted in
Next, the source pad 17 is formed so as to be embedded in the contact hole. A portion of a metal layer deposited to form the source pad 17 may be used as a gate pad. In the rear surface of the n+-type silicon carbide substrate 1, a metal film of a nickel (Ni) film, a titanium (Ti) film, etc. is formed in a contact portion of the drain electrode 18 using sputtering deposition. The metal film may be a combination of stacked Ni films, Ti films. Thereafter, annealing such as rapid thermal annealing (RTA) is performed so as to convert the metal layer into a silicide and form an ohmic contact. Thereafter, for example, a thick film such as a stacked film formed by sequentially stacking a Ti film, a Ni film, and a gold (Au) film is formed by electron beam (EB) deposition, etc. to form the drain electrode 18.
In the epitaxial growth and ion implantation described above, as the n-type impurity (n-type-dopant), for example, nitrogen (N) and/or phosphorus (P), which are an n-type with respect to silicon carbide, arsenic (As), antimony (Sb), etc. may be used. As the p-type impurity (p-type-dopant), for example, boron (B) and/or aluminum (Al), which are a p-type with respect to silicon carbide, gallium (Ga), indium (In), thallium (Tl), etc. may be used. Thus, the MOSFET depicted in
As described above, according to the first embodiment, formation of the high-concentration implantation region by ion implantation in the p-type base region formed by epitaxial growth generates the bell-curve shaped impurity concentration profile in which the impurity concentration in the p-type base region differs in the depth direction. Additionally, formation of the high-concentration implantation region by ion implantation in the p-type base region generates partial crystal structure disorder in the p-type base region. As a result, compared to the impurity concentration profile in the depth direction for a case of a structure formed by only an epitaxial layer such as a conventional structure (refer to
Moreover, in general, although the smaller the variations of the carrier density of the channel are, the smaller the variations of the gate threshold voltage can be made, in the epitaxial growth of the silicon carbide, control of the impurity concentration becomes difficult and variations in the carrier density of the channel increase. Therefore, in a conventional structure (refer to
Further, according to the first embodiment, even when a commercial silicon carbide base is used on which a p-type silicon carbide layer is formed by epitaxial growth on an n-type silicon carbide substrate to become the p-type base region, the same effects described above are obtained by forming the high-concentration implantation region by ion implantation in the p-type base region.
A method of manufacturing a silicon carbide semiconductor device according to a second embodiment will be described.
In particular, first, similar to the first embodiment, the n+-type silicon carbide substrate 1 is prepared and the processes up to the formation process of the n-type current spreading region 3 are sequentially performed (refer to
Next, as depicted in
Further, by the processes up to here, the silicon carbide base (semiconductor wafer) 10 in which the n−-type silicon carbide layer 21 and the p-type silicon carbide layer 22 are sequentially deposited on the n+-type silicon carbide substrate 1 is formed. Thereafter, similar to the first embodiment, the processes including the formation process of the n+-type source region 5 and subsequent processes are sequentially performed (refer to
As described above, according to the second embodiment, effects identical to those of the first embodiment may be obtained. Further, conventionally, in performing ion implantation so that the impurity reaches a deep position from the ion implantation surface, for example, problems arise in that specialized manufacturing equipment capable of ion implantation (mega-implantation) by high acceleration energy is necessary, the ion implantation is time-consuming, etc. In contrast, according to the second embodiment, the epitaxial growth is divided into and performed in multiple sessions and based on each p-type silicon carbide layer thickness, the depth of the position of the high-concentration implantation region may be determined freely. As a result, without the use of specialized manufacturing equipment capable of mega-implantation, the high-concentration implantation region may be formed in the base region, at a deep position from the base front surface side.
The structure of the semiconductor device according to a third embodiment will be described.
In particular, the first p+-type region 11 penetrates the n-type current spreading region 3 from the bottom of the trench 7 in the depth direction and protrudes into the n−-type drift region 2. The second p+-type region 12 penetrates the n-type current spreading region 3 from the interface of the p-type base region 4 and the n-type current spreading region 3 in the depth direction and protrudes into the n−-type drift region 2. The depth of the position of the drain-side ends of the first and the second p+-type regions 11, 12 may be the same as that of the interface of the n-type current spreading region 3 and the n−-type drift region 2.
The method of manufacturing a silicon carbide semiconductor device according to the third embodiment suffices to make, in the method of manufacturing a silicon carbide semiconductor device according to the first embodiment, the depth of the first p+-type region 11 and the depth of the p+-type partial region 12a, which becomes a portion of the second p+-type region 12, deeper than the n-type partial region 3a, which becomes a portion of the n-type current spreading region 3.
As described above, according to the third embodiment, regardless of the depths of the first and the second p+-type regions, effects identical to those of the first and the second embodiments may be obtained.
The semiconductor device according to a fourth embodiment will be described. The structure of the semiconductor device according to the fourth embodiment is the same as that of the first embodiment (refer to
In particular, the high-concentration implantation region 13 has the p-type impurity concentration profile 41 in which concentration differences in the depth direction form two bell-shaped curves at peaks 13b, 13c where the impurity concentration is higher than that of the p-type silicon carbide layer 22 forming the p-type base region 4. In other words, the p-type impurity concentration profile 41 has the peaks 13b, 13c in the p-type base region 4, and from the respective positions of the peaks 13b, 13c, the impurity concentration decreases by respective predetermined slopes on both sides (the source side and the drain side) of the base. The depths of the positions of the depth peaks 13b, 13c of the high-concentration implantation region 13 is preferably the same depth as that of the peak 13a in the first embodiment.
Next, the p-type impurity concentration profile 41 resulting from the ion implantation of a p-type impurity for forming the high-concentration implantation region 13 will be described in detail.
Hereinafter, in the description of
Further, by the ion implantation of a p-type impurity for forming the high-concentration implantation region 13, the p-type impurity concentration profile 41 having the peaks 41b, 41c of the impurity concentration at positions deeper from the base front surface than a peak 42a of the n-type impurity concentration profile 42 is formed in the p-type silicon carbide layer 22. The peaks 41b, 41c of the p-type impurity concentration profile 41 are the peaks 13b, 13c of the impurity concentration profile of the high-concentration implantation region 13, respectively. Further, in the p-type impurity concentration profile 41, impurity concentration decreases in a bell-shaped curve from the positions of the peaks 41b, 41c by respective predetermined slopes on the source side and the drain side. In addition, in the p-type impurity concentration profile 41, the impurity concentration decreases sharply at an interface 40b of the p-type silicon carbide layer 22 and the n−-type silicon carbide layer 21 and the impurity concentration decreases from the interface 40b to toward drain side by a predetermined slope.
The p-type impurity concentration profile 41 such as this, is obtained by performing the ion implantation of a p-type impurity similar to the p-type impurity concentration profile 31 and is not obtained by only epitaxial growth. Further, the impurity concentration of the p-type silicon carbide layer 22 and the impurity concentration of the peaks 41b, 41c of the p-type impurity concentration profile 41 are preferably the same values as those of the impurity concentration of the p-type silicon carbide layer 22 of the first embodiment and the peak 31a of the p-type impurity concentration profile 31, respectively. Further, in the fourth embodiment, although a case is given where the p-type impurity concentration profile 41 has the peaks 41b, 41c, the p-type impurity concentration profile 41 may have more than two peaks.
The method of manufacturing a silicon carbide semiconductor device according to the fourth embodiment will be described. The method of manufacturing a silicon carbide semiconductor device according to the fourth embodiment differs from the method of manufacturing a silicon carbide semiconductor device according to the first embodiment in the process for forming the high-concentration implantation region 13. In particular, in the ion implantation process for forming the high-concentration implantation region 13, the ion implantation is divided into and performed in two sessions.
In particular, first, similar to the first embodiment, the n+-type silicon carbide substrate 1 is prepared and the processes up to the formation process of the p-type silicon carbide layer 22 are sequentially performed (refer to
Thereafter, similar to the first embodiment, the formation process of the n+-type source region 5 and the processes thereafter are sequentially performed (refer to
As described above, according to the fourth embodiment, effects identical to those of the first embodiment may be obtained. In the fourth embodiment, although the high-concentration implantation region 13 of the first embodiment is formed by two ion implantation sessions, the high-concentration implantation region 13 of the second embodiment and of the third embodiment may be formed by two ion implantation sessions. In these cases as well, effects identical to those of the second embodiment and of the third embodiment may be obtained.
The semiconductor device according to a fifth embodiment will be described. The structure of the semiconductor device according to the fifth embodiment is the same as that of the first embodiment (refer to
Although in the p-type impurity concentration profile 41, the impurity concentration decreases sharply at the interface 40b, in the p-type impurity concentration profile 51, the impurity concentration decreases by a predetermined slope from the position of the peak 51c on the drain side. Further, the peak 51b on the source side is a factor determining the gate threshold voltage Vth and the higher the impurity concentration of the peak 51b is, the higher the gate threshold voltage Vth may be raised (made higher). The peak 51c of the drain side is a factor determining the short channel effects and the closer the position of the peak 51c is to the n-type current spreading region 3, the more the short channel effects may be suppressed.
Next, the method of manufacturing a silicon carbide semiconductor device according the fifth embodiment will be described. In the method of manufacturing a silicon carbide semiconductor device according to the fifth embodiment, the processes for forming the first p-type base portion 4a, the second p-type base portion 4b, and the high-concentration implantation region 13 differ from those of the method of manufacturing a silicon carbide semiconductor device according to the fourth embodiment. In particular, in place of forming the p-type silicon carbide layer 22 by epitaxial growth, an n-type silicon carbide layer 22′ is formed by epitaxial growth. By ion implantation of a p-type impurity into the n-type silicon carbide layer 22′, the first p-type base portion 4a, the second p-type base portion 4b, and the high-concentration implantation region 13 are formed by return to the p-type.
In particular, first, similar to the first embodiment, the n+-type silicon carbide substrate 1 is prepared and the processes up to the formation process of the n-type current spreading region 3 are sequentially performed (refer to
Next, a p-type impurity is implanted by two ion implantation sessions into the entire n-type silicon carbide layer 22′ so as to form the high-concentration implantation region 13 having the predetermined thickness t1, at a predetermined depth in the n-type silicon carbide layer 22′ (refer to
Thereafter, similar to the first embodiment, the formation process of the n+-type source region 5 and the processes thereafter are sequentially performed (refer to
As described above, according to the fifth embodiment, effects identical to those of the first embodiment may be obtained. Further, similar to the second embodiment, the n-type silicon carbide layer 22′ may be formed by epitaxial growth separated into two sessions. In this case, effects identical to those of the second embodiment may be obtained.
Next, the semiconductor device according to a sixth embodiment will be described. The structure of the semiconductor device according to the sixth embodiment is the same as that of the first embodiment (refer to
In particular, the high-concentration implantation region 13 has the p-type impurity concentration profile 61 in which concentration differences in the depth direction form two bell-shaped curves at peaks 13b, 13c where the impurity concentration is higher than that of the p-type silicon carbide layer 22 forming the p-type base region 4. In other words, the p-type impurity concentration profile 61 has the peaks 13b, 13c in the p-type base region 4 and the depths of the positions of the peaks 13b, 13c differ. Further, in the p-type impurity concentration profile 61, from the respective positions of the peaks 13b, 13c, the impurity concentration decreases by respective predetermined slopes on both sides (the source side and the drain side) of the base. The depth of the position of one of the peaks 13b, 13c of the high-concentration implantation region 13 may be preferably the depth of the position of the peak 13a in the first embodiment.
The p-type impurity concentration profile 61 resulting from the ion implantation of a p-type impurity for forming the high-concentration implantation region 13 will be described in detail.
In the p-type impurity concentration profile 61, similar to the p-type impurity concentration profile 51, the impurity concentration decreases by a predetermined slope from the position of the peak 61c on the drain side. Further, the depths of the positions of the peaks 61b, 61c in the p-type impurity concentration profile 61 are the same as the depths of the peaks 51b, 51c in the p-type impurity concentration profile 51. The impurity concentration of the peak 61b on the source side is higher than the impurity concentration of the peak 61c on the drain side. In particular, the impurity concentration of the peak 61c on the drain side may be preferably 10% to 70% of the impurity concentration of the peak 61b on the source side.
Further, in the sixth embodiment, although a case is depicted where the p-type impurity concentration profile 61 has two peaks (the peaks 61b, 61c), the p-type impurity concentration profile 61 may have more than two peaks. In this case, the impurity concentration of the peak closest to the source side is higher than the impurity concentration of the peak closest to the drain side. In particular, the impurity concentration of the peak closest to the drain side may be preferably 10% to 70% of the impurity concentration of the peak closest to the source side. Further, the impurity concentrations of peaks other than the peak closest to the source side and the peak closest to the drain side may be equal, or the impurity concentrations may gradually decrease toward the drain side.
The method of manufacturing a silicon carbide semiconductor device according to the sixth embodiment will be described. In the method of manufacturing a silicon carbide semiconductor device according to the sixth embodiment, the ion implantation process differs from that in the method of manufacturing a silicon carbide semiconductor device according to the fifth embodiment. In particular, the high-concentration implantation region 13 having the p-type impurity concentration profile 61 in which the impurity concentration of the peak 61b is higher than the impurity concentration of the peak 61c is formed by ion implantation.
In particular, first, similar to the fifth embodiment, the n+-type silicon carbide substrate 1 is prepared and the processes up to the formation process of the n-type silicon carbide layer 22′ are sequentially performed (refer to
As a result, similar to the fifth embodiment, the n-type silicon carbide layer 22′ is returned to the p-type to become the p-type silicon carbide layer 22; and in the p-type silicon carbide layer 22, a portion farther on the drain side than the high-concentration implantation region 13 becomes the first p-type base portion 4a described above, and a portion farther on the source side (the opposite side with respect to the n+-type silicon carbide substrate 1) than the high-concentration implantation region 13 becomes the second p-type base portion 4b described above. The p-type base region 4 is formed by the first and the second p-type base portions 4a, 4b and the high-concentration implantation region 13. Further, similar to the fourth embodiment, formation may be by more than two ion implantation sessions. The number of ion implantation sessions, similar to the fifth embodiment, for example, may be preferably a range from 2 to 5. Further, similar to the fourth embodiment, the high-concentration implantation region 13 having the p-type impurity concentration profile 61 may be formed by ion implanting multiple types of differing p-type ion species.
Thereafter, similar to the first embodiment, the formation process of the n+-type source region 5 and the processes thereafter are sequentially performed (refer to
As described above, according to the sixth embodiment, effects identical to those of the first embodiment may be obtained. Further, according to the sixth embodiment, in the p-type impurity concentration profile, the impurity concentration of the peak on the source side is higher than the impurity concentration of the peak on the drain side. As a result, on-resistance may be reduced without changing the gate threshold voltage and variation of the gate threshold voltage. This is because the gate threshold voltage is determined by the impurity concentration of the peak on the source side and by making the impurity concentration of the peak on the drain side a low impurity concentration on an order enabling the short channel effect to be suppressed, increase of the channel resistance may be suppressed. Here, the short channel effect is a sharp decrease of the gate threshold voltage consequent to a shortening of the channel length. Further, similar to the second embodiment, the n-type silicon carbide layer 22′ may be formed by epitaxial growth separated into two sessions. In this case, effects identical to those of the second embodiment may be obtained.
The frequency of occurrence of leak current between the drain and source was verified.
Plural MOSFET chips (refer to
Variation of the gate threshold voltage Vth was verified.
From the results depicted in
On the other hand, in the first example, for one semiconductor wafer surface, although variation of the impurity concentration of the p-type base region 4 within a standard deviation of ±3σ of the mean was ±30%, the same as the first conventional example, variation of the impurity concentration of the high-concentration implantation region 13 was confirmed to be ±10%. Further, it was confirmed that the gate threshold voltage Vth within a standard deviation of ±3σ of the mean could be controlled to be within a range from 4.4V to 5.6V.
Similarly, in the second example, for one semiconductor wafer surface, although variation of the impurity concentration of the p-type base region 4 within a standard deviation of ±3σ of the mean was ±30%, the same as the first conventional example, variation of the impurity concentration of the high-concentration implantation region 13 was confirmed to be ±10% for both the fourth embodiment and the sixth embodiment. Further, it was confirmed that the gate threshold voltage Vth within a standard deviation of ±3σ of the mean could be controlled to be within a range from 4.35V to 5.65V. These results illustrate that by formation of the high-concentration implantation region 13 in the p-type base region 4, variation of the gate threshold voltage Vth is rate limited by the variation of the impurity concentration of the high-concentration implantation region 13.
Although not depicted, for MOSFET chips manufactured according to the method of manufacturing a silicon carbide semiconductor device according to the fifth embodiment described above, it was confirmed by the inventor that effects identical to those of the second example could be obtained.
The optimal depth of the position of the peak 13a of the high-concentration implantation region 13 was verified.
In the second conventional example and the first and second comparison examples, the carrier mobility of the channel and the channel dependency of the gate threshold voltage Vth each differ and therefore, were qualitatively evaluated. For the second conventional example and the first and second comparison examples, the carrier mobility of the channel was assumed for a case where the carrier mobility of the channel was set to be 2.0×1017/cm3. Since respective subthreshold current values also differed for the second conventional example and the first and second comparison examples, the gate threshold voltage Vth was also qualitatively evaluated. Cell pitch (arrangement interval of unit cells) was set as 6.0 μm and the drain voltage Vd was set to be 20V.
Conditions of the second conventional example and the first and second comparison examples were as follows. As depicted in
As depicted in
As depicted in
In both the first and second comparison examples, thicknesses t11, t12 of the first and second portions of the p-type base region 34 were the same, 0.275 μm. Further, in both the first and second comparison examples, although the impurity concentration profile of the p-type base region 34 is changed to have a step-shape in the depth direction, the high-impurity-concentration second and first portions 34b, 34c are assumed to have impurity concentration profiles having a Gaussian distribution formed consequent to ion implantation. In other words, the second and first portions 34b, 34c of the p-type base region 34 in the first and second comparison examples assume the high-concentration implantation region 13 of the present invention.
From the results depicted in
In the first to third examples, although a case where aluminum is used as the p-type-dopant (p-type impurity) forming the p-type base region 4 and the high-concentration implantation region 13 is described as an example, the p-type-dopant is not limited hereto and even when a p-type-dopant above becoming a p-type with respect to silicon carbide is used, the same effects are obtained. Further, even when the p-type-dopant used when the p-type base region 4 is formed by epitaxial growth and the p-type-dopant used when the high-concentration implantation region 13 is formed by ion implantation are different ion species, the same effects are obtained.
In the description above, various changes not departing from the spirit of the present invention are possible. In the described embodiments, for example, dimensions, impurity concentrations, etc. of components may be variously set according to required specifications, etc. Further, in the described embodiments, although a MOSFET is described as an example, without limitation hereto, various silicon carbide semiconductor devices conducting and blocking current by gate driving control based on a predetermined gate threshold voltage are widely applicable. A gate-driving-controlled silicon carbide semiconductor device, for example, may be an insulated gate bipolar transistor (IGBT) or the like. Further, in the described embodiments, although a case where silicon carbide is used as a wide bandgap semiconductor is described as an example, a wide bandgap semiconductor other than silicon carbide, for example, gallium nitride (GaN) and the like may be used. In the described embodiments, a first conductivity type is assumed to be an n-type and a second conductivity type is assumed to be a p-type; however, the present invention is further valid when the first conductivity type is a p-type and the second conductivity type is an n-type. In this case, in an n-type base region, an n+-type high-concentration implantation region is formed having an impurity concentration profile identical to the p-type impurity concentration profile in
On the contrary, in the described conventional structure, although a channel having favorable crystallinity is obtained by forming the p-type base region 104 by epitaxial growth and reduced on-resistance is possible by high carrier mobility, control of the impurity concentration during epitaxial growth of the silicon carbide layer is extremely difficult. Variation of the impurity concentration by current epitaxial growth techniques is ±30% for a product unit (including a semiconductor wafer surface, each batch process of the manufacturing process, and between batch processes) that includes all products to be manufactured within a predetermined period as a single unit. When the variation of the p-type impurity concentration of the p-type base region 104 is ±30%, a problem arises in that the variation of the gate threshold voltage Vth increases. Further, when a vertical MOSFET of a trench gate structure is manufactured (produced), a problem arises in that defective chips that are defective consequent to leak current between the drain and source (hereinafter, leak defect) increase and yield decreases.
The silicon carbide semiconductor device and the method of manufacturing a silicon carbide semiconductor device according to the present invention enable variation of the gate threshold voltage to be reduced while maintaining low on-resistance. Additionally, an effect is achieved in that leak defects may be reduced and yield may be increased.
As described, the silicon carbide semiconductor device and the method of manufacturing a silicon carbide semiconductor device according to the present invention are useful for, for example, semiconductor devices used in power converting equipment such as converters and inverters, and power supply devices such as in various industrial machines and are particularly suitable for silicon carbide semiconductor devices of a trench gate structure.
Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.
Wakimoto, Setsuko, Iwaya, Masanobu
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