An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
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1. A device comprising:
an integrated circuit die;
a first insulating layer over the integrated circuit die;
a first metallization pattern in the first insulating layer over the integrated circuit die, wherein the first metallization pattern comprises:
a first dummy pattern defining a first hole extending through a first conductive region; and
a first signal line electrically connected to the integrated circuit die;
a second insulating layer over the first insulating layer and the first metallization pattern; and
a second metallization pattern in the second insulating layer over the first metallization pattern, wherein the second metallization pattern comprises a second dummy pattern defining a second hole extending through a second conductive region, and wherein the second hole projectively overlaps a portion of the first hole and a portion of the first conductive region.
7. A package comprising:
an integrated circuit die;
an encapsulant extending along sidewalls of the integrated circuit die;
a through via extending through the encapsulant and electrically connected to the integrated circuit die;
a first dielectric layer over the integrated circuit die and the encapsulant;
a first dummy pattern in the first dielectric layer, wherein the first dummy pattern comprises:
a first conductive material; and
a plurality of first holes extending through the first conductive material and disposed in a first grid of first rows and columns;
a second dielectric layer over the first dielectric layer; and
a second dummy pattern in the second dielectric layer, wherein the second dummy pattern comprises:
a second conductive material; and
a plurality of second holes extending through the second conductive material and disposed in a second grid of second rows and columns, wherein the second grid is offset from the first grid.
15. A method for forming a package, the method comprising:
encapsulating an integrated circuit die in an encapsulant;
depositing a first dielectric layer over the integrated circuit die and the encapsulant;
forming a first metallization pattern over the first dielectric layer, wherein the first metallization pattern comprises:
a first dummy pattern comprising first holes extending through a first conductive material, wherein the first conductive material comprises a first dummy line disposed between adjacent ones of the first holes; and
a first signal line electrically connected to the integrated circuit die;
depositing a second dielectric layer over the first dielectric layer and the first metallization pattern; and
forming a second metallization pattern over the second dielectric layer, wherein the second metallization pattern comprises a second dummy pattern comprising second holes extending through a second conductive material, wherein a line perpendicular to a major surface of the second dielectric layer extends through a first one of the second holes and the first dummy line.
2. The device of
3. The device of
4. The device of
5. The device of
6. The device of
8. The package of
a third dielectric layer over the second dielectric layer; and
a third dummy pattern in the third dielectric layer, wherein the third dummy pattern comprises:
a third conductive material; and
a plurality of third holes extending through the third conductive material and disposed in a third grid of third rows and columns, wherein the second grid is offset from the third grid.
10. The package of
11. The package of
12. The package of
13. The package of
14. The package of
16. The method of
17. The method of
18. The method of
depositing a third dielectric layer over the second metallization pattern;
forming a third metallization pattern over the second metallization pattern, wherein the third metallization pattern comprises:
a third dummy pattern comprising third holes extending through a third conductive material, wherein the third conductive material comprises a second dummy line disposed between adjacent ones of the third holes, and wherein the line extends through the second dummy line; and
a second signal line electrically connected to the first signal line.
19. A method of
patterning an opening in the third dielectric layer to expose a portion of the second dummy pattern electrically connected to the first signal line; and
filling the opening with a conductive material.
20. The method of
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This application claims the benefits of U.S. Provisional Application Ser. No. 62/329,823, filed on Apr. 29, 2016, which application is hereby incorporated herein by reference in its entirety.
In an aspect of packaging technologies, such as wafer level packaging (WLP), redistribution layers (RDLs) may be formed over a die and electrically connected to active devices in a die. External input/output (I/O) pads such as solder balls on under-bump metallurgy (UBMs) may then be formed to electrically connect to the die through the RDLs. An advantageous feature of this packaging technology is the possibility of forming fan-out packages. Thus, the I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads packed on the surfaces of the dies can be increased.
In such packaging technologies, a molding compound may be formed around the die to provide surface area to support the fan-out interconnect structures. For example, RDLs may include one or more polymer layers formed over the die and molding compound. Conductive features (e.g., conductive lines and/or vias) are formed in the polymer layers and electrically connect I/O pads on the die to the external I/O pads over the RDLs. The external I/O pads may be disposed over both the die and the molding compound.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Various embodiments are described in a particular context, namely, an integrated fan-out (InFO) package having a particular configuration. Various embodiments may also be applied, however, to other semiconductor devices, such as, devices having stacked layers of metallization patterns disposed in a dielectric material.
The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 100 may be a wafer, such that multiple packages can be formed on the carrier substrate 100 simultaneously. The release layer 102 may be formed of a polymer-based material, which may be removed along with the carrier substrate 100 from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer 102 is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a Light-to-Heat-Conversion (LTHC) release coating. In other embodiments, the release layer 102 may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer 102 may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate 100, or may be the like. The top surface of the release layer 102 may be leveled and may have a high degree of co-planarity.
As illustrated in
In
In
The dielectric layers 104 and 108 and the metallization patterns 106 may be referred to as a back-side redistribution structure. As illustrated, the back-side redistribution structure includes the two dielectric layers 104 and 108 and one metallization pattern 106. In other embodiments, the back-side redistribution structure can include any number of dielectric layers, metallization patterns, and vias. One or more additional metallization pattern and dielectric layer may be formed in the back-side redistribution structure by repeating the processes for forming a metallization patterns 106 and dielectric layer 108. Vias may be formed during the formation of a metallization pattern by forming the seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer. The vias may therefore interconnect and electrically couple the various metallization patterns.
Further in
In
Before being adhered to the dielectric layer 108, the integrated circuit dies 114 may be processed according to applicable manufacturing processes to form integrated circuits in the integrated circuit dies 114. For example, the integrated circuit dies 114 each comprise a semiconductor substrate 118, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor material, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate 118 and may be interconnected by interconnect structures 120 formed by, for example, metallization patterns in one or more dielectric layers on the semiconductor substrate 118 to form an integrated circuit.
The integrated circuit dies 114 further comprise pads 122, such as aluminum pads, to which external connections are made. The pads 122 are on what may be referred to as respective active sides of the integrated circuit dies 114. Passivation films 124 are on the integrated circuit dies 114 and on portions of the pads 122. Openings are through the passivation films 124 to the pads 122. Die connectors 126, such as conductive pillars (for example, comprising a metal such as copper), are in the openings through passivation films 124 and are mechanically and electrically coupled to the respective pads 122. The die connectors 126 may be formed by, for example, plating, or the like. The die connectors 126 electrically couple the respective integrated circuits of the integrated circuit dies 114.
A dielectric material 128 is on the active sides of the integrated circuit dies 114, such as on the passivation films 124 and the die connectors 126. The dielectric material 128 laterally encapsulates the die connectors 126, and the dielectric material 128 is laterally co-terminus with the respective integrated circuit dies 114. The dielectric material 128 may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof, and may be formed, for example, by spin coating, lamination, CVD, or the like.
Adhesive 116 is on back-sides of the integrated circuit dies 114 and adheres the integrated circuit dies 114 to the back-side redistribution structure 110, such as the dielectric layer 108 in the illustration. The adhesive 116 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 116 may be applied to a back-side of the integrated circuit dies 114, such as to a back-side of the respective semiconductor wafer or may be applied over the surface of the carrier substrate 100. The integrated circuit dies 114 may be singulated, such as by sawing or dicing, and adhered to the dielectric layer 108 by the adhesive 116 using, for example, a pick-and-place tool.
In
In
In
In
In
The metallization pattern 138 may include signal lines (e.g., for power, ground, and/or electrical signals to the integrated circuit dies 114) as well as dummy patterns formed to fill spaces between the signal lines as explained in greater detail below with respect to
In
In
In
In
In
In
In
In
The front-side redistribution structure 160 is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure 160. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed above may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed above may be repeated. One having ordinary skill in the art will readily understand which steps and processes would be omitted or repeated.
In
In
In
As further illustrated in
The substrate 302 may include active and passive devices (not shown in
The substrate 302 may also include metallization layers (not shown) and through vias 306. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate 302 is substantially free of active and passive devices.
The substrate 302 may have bond pads 303 on a first side the substrate 202 to couple to the stacked dies 308, and bond pads 304 on a second side of the substrate 302, the second side being opposite the first side of the substrate 302, to couple to the conductive connectors 314. In some embodiments, the bond pads 303 and 304 are formed by forming recesses (not shown) into dielectric layers (not shown) on the first and second sides of the substrate 302. The recesses may be formed to allow the bond pads 303 and 304 to be embedded into the dielectric layers. In other embodiments, the recesses are omitted as the bond pads 303 and 304 may be formed on the dielectric layer. In some embodiments, the bond pads 303 and 304 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads 303 and 304 may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. In an embodiment, the conductive material of the bond pads 303 and 304 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.
In an embodiment, the bond pads 303 and 304 are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBMs 303 and 304. Any suitable materials or layers of material that may be used for the UBMs 303 and 304 are fully intended to be included within the scope of the current application. In some embodiments, the through vias 306 extend through the substrate 302 and couple at least one bond pad 303 to at least one bond pad 304.
In the illustrated embodiment, the stacked dies 308 are coupled to the substrate 302 by wire bonds 310, although other connections may be used, such as conductive bumps. In an embodiment, the stacked dies 308 are stacked memory dies. For example, the stacked memory dies 308 may include low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, or the like memory modules.
In some embodiments, the stacked dies 308 and the wire bonds 310 may be encapsulated by a molding material 312. The molding material 312 may be molded on the stacked dies 308 and the wire bonds 310, for example, using compression molding. In some embodiments, the molding material 312 is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material 312, wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof.
In some embodiments, the stacked dies 308 and the wire bonds 310 are buried in the molding material 312, and after the curing of the molding material 312, a planarization step, such as a grinding, is performed to remove excess portions of the molding material 312 and provide a substantially planar surface for the second packages 300.
After the second packages 300 are formed, the packages 300 are bonded to the first packages 200 by way of conductive connectors 314, the bond pads 304, and the metallization pattern 106. In some embodiments, the stacked memory dies 308 may be coupled to the integrated circuit dies 114 through the wire bonds 310, the bond pads 303 and 304, through vias 306, the conductive connectors 314, and the through vias 112.
The conductive connectors 314 may be similar to the conductive connectors 166 described above and the description is not repeated herein, although the conductive connectors 314 and 166 need not be the same. In some embodiments, before bonding the conductive connectors 314, the conductive connectors 314 are coated with a flux (not shown), such as a no-clean flux. The conductive connectors 314 may be dipped in the flux or the flux may be jetted onto the conductive connectors 314. In another embodiment, the flux may be applied to the surfaces of the metallization patterns 106.
In some embodiments, the conductive connectors 314 may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the second package 300 is attached to the first package 200. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors 314. In some embodiments, an underfill (not shown) may be formed between the second package 300 and the first package 200 and surrounding the conductive connectors 314. The underfill may be formed by a capillary flow process after the second package 300 is attached or may be formed by a suitable deposition method before the second package 300 is attached.
The bonding between the second package 300 and the first package 200 may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding. In an embodiment, the second package 300 is bonded to the first package 200 by a reflow process. During this reflow process, the conductive connectors 314 are in contact with the bond pads 304 and the metallization patterns 106 to physically and electrically couple the second package 300 to the first package 200. After the bonding process, an inter-metallization compound (not shown) may form at the interface of the metallization patterns 106 and the conductive connectors 314 and also at the interface between the conductive connectors 314 and the bond pads 304 (not shown).
The semiconductor package 500 includes the packages 200 and 300 being mounted to a substrate 400. The substrate 400 may be referred to a package substrate 400. The package 300 is mounted to the package substrate 400 using the conductive connectors 166.
The package substrate 400 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the package substrate 400 may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate 400 is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for package substrate 400.
The package substrate 400 may include active and passive devices (not shown in
The package substrate 400 may also include metallization layers and vias (not shown) and bond pads 402 over the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate 400 is substantially free of active and passive devices.
In some embodiments, the conductive connectors 166 can be reflowed to attach the package 200 to the bond pads 402. The conductive connectors 166 electrically and/or physically couple the substrate 400, including metallization layers in the substrate 400, to the first package 200.
The conductive connectors 166 may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the package 200 is attached to the substrate 400. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors 166. In some embodiments, an underfill (not shown) may be formed between the first package 200 and the substrate 400 and surrounding the conductive connectors 166. The underfill may be formed by a capillary flow process after the package 200 is attached or may be formed by a suitable deposition method before the package 200 is attached.
As discussed above, any of the metallization patterns within various RDLs (e.g., 106, 138, 146, and/or 154) may include signal lines (e.g., providing power, ground, and/or electrical routing to the integrated circuit dies 114) as well as dummy patterns between and among the signal lines. Generally, the term “dummy pattern” refers to conductive features included for reasons other than electrical routing. For example, in an embodiment, the dummy patterns are electrically insulated from other conductive features in the package, and the dummy patterns are not electrically connected to any active devices. In other embodiments, a conductive via, such as, a conductive via connecting signal lines in layers above and below the dummy pattern, may extend through the dummy pattern, and the dummy pattern may be electrically connected to signal lines in other layers. However, in such embodiments, the dummy pattern may not provide any electrical routing for features (e.g., signal lines) within the layer in which the dummy pattern is disposed.
The dummy patterns may be included to provide a more uniform metallization pattern to improve the planarity of various dielectric layers in which respective the metallization patterns 106, 138, 146, and/or 154 are disposed. In various embodiments, the dummy patterns may be formed and patterned during the formation of various signal lines using any suitable process, such as those described above. Thus, additional process costs to form dummy patterns may be reduced. In other embodiments, the dummy pattern and the signal lines may be formed separately (e.g., the dummy pattern and the signal lines may be formed sequentially in any suitable order) and/or using a different process (e.g., the dummy pattern may be formed by depositing a conductive layer and subsequently etching openings through the conductive layer).
Because the dummy patterns and the signal lines within a metallization pattern may be formed simultaneously, the material of the dummy patterns and the signal lines may also be the same. In various embodiments the dummy patterns comprise holes extending through a conductive material of the dummy pattern. For example, the dummy patterns may include mesh grids having holes disposed in a grid of rows and columns. The holes in the dummy patterns may be included to reduce stress induced by the metallization patterns in various dielectric layers of the resulting package. For example, in some embodiments, a total surface area of holes in a dummy pattern may be at least about 30% to about 40% of a total surface of the dummy pattern. It has been observed by including holes having the above areas, stress may be reduced to a suitable level. Thus, manufacturing defects may be reduced and package reliability may be improved. In other embodiments, the holes may occupy a different surface area percentage in relation to a surface area the entire dummy pattern.
Referring first to
When the holes 608 have a substantially rectangular planar profile (e.g., profile of holes 608 in a planar view), an area of the holes 608 in a top-down view may be maximized within a particular spacing restraint of the resulting device (e.g., a particular critical dimension for a given technology node). By maximizing an area of each hole 608, the stress reduction properties of the holes 608 on the dummy pattern 604 may be increased. In other embodiments, a shape of the holes 608 may be different (e.g., circular, ovular, or any other suitable shape).
The conductive material 606 may be disposed in a pattern of multiple columns and rows, thereby defining a plurality of holes 608 there-between. Throughout the description, portions of the conductive material 606 disposed around the holes 608 may also be referred to as dummy lines, such as dummy lines 606A and dummy lines 606B. In the illustrated orientation of
As further illustrated by
Referring back to
The dummy pattern 616 includes a plurality of holes 620 extending through a conductive material 618 of the dummy pattern 604. Each of the holes 620 may be filled with a portion of the dielectric layer 614. The holes 620 may be arranged in a grid of rows and columns, and each row and column in the array may include a same number or a different number of the holes 620. For example, as illustrated by
Referring back to the top down view of
The conductive material 618 may be disposed between adjacent holes 620. Throughout the description, portions of the conductive material 618 disposed around the holes 620 may also be referred to as dummy lines, such as dummy lines 618A and dummy lines 618B. In the illustrated orientation of
Furthermore, the mesh grid of the dummy pattern 616 is offset from the mesh grid of the dummy pattern 604. For example, in areas where the dummy patterns 604 and 616 overlap, the holes 620 of the dummy pattern 616 are offset from the holes 608 of the dummy pattern 604, and the holes 620 of the dummy pattern 616 are disposed directly over at least a portion of the conductive material 606 of the dummy pattern 604. Put another way, the holes 620 defined by dummy pattern 616 projectively overlaps at least a portion of the conductive material 606 of the dummy pattern 604. Referring to
Furthermore, referring back to
The dummy pattern 626 may be similar to the dummy patterns 616 and 604 (see
It has been observed that by offsetting the holes in dummy patterns in adjacent dielectric layers, the planarity of a top-most dielectric layer (e.g., the dielectric layer 624) may be improved. For example, in an embodiment, a top surface 624A (see
In accordance with an embodiment, a device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern defining a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern defining a second hole extending through a second conductive region. The second hole projectively overlaps a portion of the first hole and a portion of the first conductive region
In accordance with another embodiment, a package includes an integrated circuit die, an encapsulant extending along sidewalls of the integrated circuit die, a through via extending through the encapsulant and electrically connected to the integrated circuit die, and a first dielectric layer over the integrated circuit die and the encapsulant. The package further includes a first dummy pattern in the first dielectric layer. The first dummy pattern includes a first conductive material and a plurality of first holes extending through the first conductive material and disposed in a first grid of first rows and columns. The package also includes a second dielectric layer over the first dielectric layer and a second dummy pattern in the second dielectric layer. The second dummy pattern includes a second conductive material and a plurality of second holes extending through the second conductive material and disposed in a second grid of second rows and columns. The second grid is offset from the first grid.
In accordance with yet another embodiment, a method includes encapsulating an integrated circuit die in an encapsulant, depositing a first dielectric layer over the integrated circuit die and the encapsulant, and forming a first metallization pattern over the first dielectric layer. The first metallization pattern includes a first dummy pattern and a first signal line electrically connected to the integrated circuit die. The first dummy pattern includes first holes extending through a first conductive material. The first conductive material includes a first dummy line disposed between adjacent ones of the first holes. The method also includes depositing a second dielectric layer over the first dielectric layer and the first metallization pattern. The method also includes forming a second metallization pattern over the second dielectric layer. The second metallization pattern includes a second dummy pattern having second holes extending through a second conductive material. A line perpendicular to a major surface of the second dielectric layer extends through a first one of the second holes and the first dummy line.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Yu, Chen-Hua, Yeh, Der-Chyang, Chen, Hsien-Wei, Wu, Chi-Hsi, Hsu, Li-Han, Hsieh, Cheng-Hsien, Wu, Wei-Cheng
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