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The ornamental design for a circuit tester, as shown and described. |
FIG. 1 is a perspective view of a circuit tester showing my new design;
FIG. 2 is a perspective view thereof with the cover thereof closed;
FIG. 3 is a perspective view thereof with the test leads thereof pulled out;
FIG. 4 is a front elevational view thereof;
FIG. 5 is a rear elevational view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof;
FIG. 8 is a left side elevational view thereof;
FIG. 9 is a right side elevational view thereof;
FIG. 10 is a front elevational view thereof with the cover thereof closed;
FIG. 11 is a rear elevational view thereof with the cover thereof closed;
FIG. 12 is a top plan view thereof with the cover thereof closed;
FIG. 13 is a bottom plan view thereof with the cover thereof closed;
FIG. 14 is a left side elevational view thereof with the cover thereof closed;
FIG. 15 is a right side elevational view thereof with the cover thereof closed;
FIG. 16 is a front elevational view thereof in which the cover is turned until reaching a rear face of a body proper; and,
FIG. 17 is a bottom plan view thereof in which the cover is turned until reaching the rear face of the body proper.
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 17 1998 | KAISE, HIDEO | Kaise Kabushiki Kaisha | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 009461 | /0384 | |
Aug 17 1998 | MURASE, MASAZO | Kaise Kabushiki Kaisha | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 009461 | /0384 | |
Sep 10 1998 | Kaise Kabushiki Kaisha | (assignment on the face of the patent) | / |
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