FIG. 1 is a front view of the housing for a test chip of the invention in an open position.
FIG. 2 is a back view of the housing for a test chip of FIG. 1.
FIG. 3 is a top view of the housing for a test chip of FIG. 1.
FIG. 4 is a bottom view of the housing for a test chip of FIG. 1.
FIG. 5 is a side view from the right in an open position of the housing for a test chip of FIG. 1.
FIG. 6 is a side view from the left in an open position of the housing for a test chip of FIG. 1.
FIG. 7 is a perspective view of the housing for a test chip of FIG. 1.
FIG. 8 is a front view of the housing for a test chip of the invention in a closed position.
FIG. 9 is a back view of the housing for a test chip of FIG. 8.
FIG. 10 is a top view of the housing for a test chip of FIG. 8.
FIG. 11 is a bottom view of the housing for a test chip of FIG. 8.
FIG. 12 is a side view from the right of the housing for a test chip of FIG. 8.
FIG. 13 is a side view from the left of the housing for a test chip of FIG. 8; and,
FIG. 14 is a perspective view of the housing for a test chip of FIG. 8.
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