The ornamental design for a jig for measuring withstand voltage of semiconductor element, as shown and described.
FIG. 1 is a front view of a first embodiment of the jig for measuring withstand voltage of semiconductor element, which has tapped holes used to hold a substrate provided with a semiconductor element and has a hollow to contain insulating liquid to submerge the substrate during measurement of a withstanding voltage of the element, showing our new design;
FIG. 2 is a rear view thereof;
FIG. 3 is a top plan view thereof;
FIG. 4 is a bottom plan view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a left side view thereof;
FIG. 7 is a front perspective view thereof;
FIG. 8 is a sectional view taken along line 8-8 of FIG. 3 thereof;
FIG. 9 is a referential top plan view showing the state in use thereof; and,
FIG. 10 is a referential front perspective view showing the state in use thereof.
The broken line showing is for illustrative purpose only and forms no part of the claimed design.