FIG. 1 is a top perspective view of a light emitting diode chip showing our design;
FIG. 2 is a top view thereof;
FIG. 3 is a bottom view thereof;
FIG. 4 is an end view thereof;
FIG. 5 is an opposing end view thereof:
FIG. 6 is a side view thereof;
FIG. 7 is an opposing side view thereof;
FIG. 8 is a top perspective view of a light emitting diode chip showing our design;
FIG. 9 is a top view thereof;
FIG. 10 is a bottom view thereof;
FIG. 11 is an end view thereof;
FIG. 12 is an opposing end view thereof:
FIG. 13 is a side view thereof; and,
FIG. 14 is an opposing side view thereof.
The broken lines shown in the drawings depict portions of the light emitting diode chip that form no part of the claimed design.
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 27 2018 | | CreeLED, Inc. | (assignment on the face of the patent) | | / |
Aug 03 2018 | TAYLOR, WILLIAM SHELDON | Cree, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 046546 | /0486 |
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Aug 03 2018 | DRISCOLL, DANIEL CARLETON | Cree, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 046546 | /0486 |
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