The ornamental design for a batterypack, as shown and described.
FIG. 1 is a perspective view of a first embodiment of our new design.
FIG. 2 is a front view thereof.
FIG. 3 is a back view thereof.
FIG. 4 is a left-side view thereof.
FIG. 5 is a right-side view thereof.
FIG. 6 is a top view thereof; and,
FIG. 7 is a bottom view thereof.
The broken line showing is included for the purpose of illustrating unclaimed portions of the design for a battery pack and forms no part of the claimed design.
Integrated circuit structure incorporating one or more asymmetric field effect transistors as power gates for an electronic circuit with stacked symmetric field effect transistors