An electronic control logic system for processing the results of a spectrophotometer analysis of a serum chemistry comprised of a serum and one or more chemical reagents. The spectrophotometer output representing air as a light path and another output representing the test chemistry as a light path are integrated and the air path integrated value allowed to exponentially decay until its value is equal to that of the integrated test chemistry path value. The decay time is converted into a train of digital pulses representative of the optical density of the test chemistry. These pulses are counted and their total stored for comparison with the corresponding optical density of a standard solution. The concentration of the element for which the particular test was designed to detect is known for the standard solution, so the percentage concentration of that element in the test chemistry may be thereby ascertained. Programable variations are provided to enable the evaluation of test results from a kinetic or an end point test. The results of the analysis, together with a test identification number and a patient identification number is selectively applied by a printer control logic section for suitable printing of the data.
|
9. An automatic method for determining the percentage concentration of an element a substance in a test solution, which comprises the steps of reading the generating a first electrical signal having a value representative of a parameter characteristic of the test solution; reading the generating a second electrical signal having a value representative of said parameter for a standard solution having a known concentration of the element substance therein; calculating a value for generating and storing a third electrical signal having a value representing the known concentration of the substance in said standard solution; generating a standardizing scale factor representing the concentration of the element in the solution needed for said parameter of the solution to equal a predetermined value signal with calculation means by arithmetically operating automatically on said parameter value for said standard solution second and third electrical signals; multiplying with multiplication means the calculated scale factor signal by the value of said parameter for said solution said first electrical signal to obtain an output signal; and storing the result of said multiplying step whereby said result is the and presenting said output signal, said output signal having a value of the percentage concentration of the element substance in the test solution.
6. An apparatus for determining the concentration of an element a substance in a test solution, which comprises analyzation means for determining the generating a first electrical signal having a value representative of a parameter characteristic of the test solution and the value and for generating a second electrical signal having a value representative of said parameter for a standard solution having a known concentration of the element substance therein; storage means for generating and storing a third electrical signal having a value representing the known concentration of the substance in said test solution; calculation means for determining a value for automatically generating a standardizing scale factor representing the concentration of the element in the solution needed for said parameter value to equal a predetermined value signal, said calculation means including having arithmetic means for operating on the values of said second and third electrical signals said parameter value for said standard solution in computing said standardizing scale factor value signal, said arithmetic means also being for operating on said parameter of the solution with first electrical signal and said standardizing scale factor signal to compute obtain an output signal having a value of the concentration of the element substance in the test solution.
29. An automatic method for determining the concentration of a substance in a succession of test solutions which comprises the steps of generating a first electrical signal having a value representative of a parameter characteristic of a blank solution and generating a second electrical signal having a value representative of said parameter for a standard solution having a known concentration of the substance therein, generating and storing a third electrical signal having a value representing the known concentration of the substance in said standard solution, generating a standardizing scale factor signal with calculation means for arithmetically operating automatically on said first, second, and third electrical signals, successively generating a fourth electrical signal for each of said test solutions, each of said fourth signals having a value representative of said parameter of its respective test solution, and multiplying with multiplication means the scale factor signal by each of said fourth electrical signals to obtain a succession of output signals each having a value of the substance concentration for one of said test solutions.
24. An apparatus for determining the concentration of a substance in each of a plurality of test solutions, comprising analyzation means for generating a first electrical signal having a value representative of a parameter characteristic of a blank solution and for generating a second electrical signal having a value representative of said parameter for a standard solution having a known concentration of the substance therein, storage means for generating and storing a third electrical signal having a value representative of the known concentration of the substance in said standard solution, and calculation means for automatically operating arithmetically on said first, second, and third electrical signals to generate a standardizing scale factor signal, said analyzation means being also for successively generating a fourth electrical signal having a value representative of said parameter for each of said test solutions, and said calculation means being also for arithmetically operating successively on each of said fourth electrical signals and said scale factor signal to obtain an output signal for each of the test solutions having a value of the substance concentration in each test solution.
3. An automatic method for determining the percentage concentration of an element a substance in a test solution, which comprises the steps of reading the value of the light transmittance of the solution; computing the optical density a value representative of the solution optical density from said solution light transmittance value; multiplying said representative optical density value by a scale factor value, said scale factor value being equal to the percentage concentration value of the element which would cause the optical density value to equal one, said multiplying step including comprising generating a first digital pulse train having pulses reoccurring at a predeterminable frequency;, counting and storing the number of pulses generated in said first pulse train;, generating a second digital pulse train identical to said first pulse train;, altering the frequency of said second pulse train in accordance with the representative optical density value of said solution ;, counting and storing the number of pulses in the thereby altered second pulse train;, comparing the stored number of pulses from said first pulse train with said scale factor value;, and stopping the generating of said first and second pulse trains when the stored number of pulses from said first pulse train equals said scale factor value, whereby the stored number of pulses having occurred in said altered second pulse train represents the percentage concentration of the element substance in the solution; and storing the resulting value of said multiplying step.
34. An automatic method for determining the concentration of a substance in a succession of test solutions which comprises the steps of generating a first electrical signal having a value representative of a parameter characteristic of a first blank solution and generating a second electrical signal having a value representative of said parameter for a standard solution having a known concentration of the substance therein, generating and storing a third electrical signal having a value representing the known concentration of the substance in said standard solution, generating a standardizing scale factor signal with calculation means for arithmetically operating automatically on said first, second, and third electrical signals, successively generating a fourth electrical signal for each of said test solutions and a fifth electrical signal for each of a plurality of second blank solutions each corresponding with one of said test solutions, said fourth and fifth signals each having a value representative of said parameter of its respective solution, successively comparing and taking the difference between each of said fourth signals and the fifth electrical signal corresponding thereto, and arithmetically operating on said successively obtained difference values with the value of said scale factor signal to obtain a series of output signals each having a value of the substance concentration in one of said test solutions.
32. An apparatus for determining the concentration of a substance in each of a plurality of test solutions comprising analyzation means for generating a first electrical signal having a value representative of a parameter characteristic of a first blank solution and for generating a second electrical signal having a value representative of said parameter for a standard solution having a known concentration of the substance therein, storage means for generating and storing a third electrical signal having a value representing the known concentration of the substance in said standard solution, and calculation means for automatically operating arithmetically on said first, second, and third electrical signals to generate a standardizing scale factor signal, said analyzation means being also for successively generating a series of fourth electrical signals each having a value representative of said parameter for one of said test solutions and a series of fifth electrical signals each having a value representative of said parameter for one of a plurality of second blank solutions each corresponding with one of said test solutions, and said calculation means also comprises subtraction means for successively comparing and taking the difference between each of said fourth electrical signals and the fifth electrical signal corresponding thereto and means for arithmetically operating on said successively obtained difference values with said scale factor signal to generate a series of output signals each having a value of the substance concentration in one of said test solutions.
5. An apparatus for determining the concentration of an element a substance in a test solution, which comprises analyzation means for determining the a value of representing the optical density of the solution; calculation means for determining generating a value for a standardizing scale factor representing the concentration of the element in the solution needed for said optical density value to equal one; multiplication means for multiplying said determined representative optical density value by said scale factor value thereby obtaining the value of the concentration of the element substance in the solution, including said multiplication means having a digital signal generator having with first and second outputs for generating a first digital signal having a predetermined frequency on said first and second outputs, a digital rate multiplier coupled to said first generator output and to said analyzation means for altering said digital frequency on said first output in accordance with said representative optical density value to generate a second digital signal, first storage means for storing a third digital signal representative of said scale factor value, second storage means coupled to said digital rate multiplier for storing said third second digital signal, said first storage means being coupled to said second generator output for receiving said first digital signal, and detection means for detecting when the value of said first digital signal equals the value of said third digital signal stored in said first storage means and for inhibiting said generator concurrently with such detection whereby the value of said second digital signal in said second storage means equals the concentration of the element substance in the test solution.
35. An apparatus for determining the rate of reaction of a known reagent with a sample solution having a quantity of a reacting substance therein, comprising analyzation means for generating a first electrical signal having a value representative of a parameter characteristic of a standard solution having a known concentration of the substance and said known reagent therein, and for generating a second electrical signal having a value representative of said parameter for said standard solution at the end of a preselected time interval after generation of said first electrical signal; storage means for generating and storing a third electrical signal having a value representative of the known concentration of the substance in said standard solution; calculation means for automatically operating arithmetically on said first, second, and third electrical signals for generating a standardizing scale factor signal; said analyzation means being also for generating a fourth electrical signal having a value representative of said parameter for a test solution having the sample solution and said known reagent therein, and for generating a fifth electrical signal having a value representative of said parameter for said test solution at the end of a preselected time interval after generation of said fourth signal, said test solution time interval being equal to the standard solution time interval; and said calculation means also comprising subtraction means for comparing and taking the difference between said fourth and fifth electrical signals and arithmetic means for arithmetically operating on said difference value with said scale factor signal to obtain an output signal having a value of the rate of reaction of the reagent with the sample solution.
4. An apparatus for determining the concentration of an element a substance in a test solution, which comprises analyzation means for determining the generating a first electrical signal having a value representative of the optical density of the test solution, said analyzation means including having optical means for determining generating an analog signal representative of the light transmittance of the test solution and for generating an analog signal in accordance therewith, conversion means for converting said analog signal to a digital said first electrical signal representative of the value of the optical density of the solution, and first storage means for storing said digital first electrical signal, said analyzation means also being for determining generating a second electrical signal having a value representative of the optical density value of a standard solution having a known concentration value of the element substance therein, and for determining generating a third electrical signal having a value representative of the optical density value of a blank solution; calculation means for determining a value for automatically generating a standardizing scale factor representing the concentration of the element in the solution needed for said optical density value to equal one signal, said calculation means including having subtraction means comparing and for taking the difference between the optical density value of the standard solution and the optical density value of the blank solution said second and third electrical signals and for storing the difference value thereby obtained in said first storage means, second storage means for generating and storing a fourth electrical signal having a value representing said known concentration value of the substance in said standard solution, and division means for dividing the value of said known concentration fourth electrical signal by said difference stored in said first storage means value between said second and third electrical signals to obtain said standardizing scale factor signal ; and multiplication means for multiplying said determined optical density first electrical signal by said scale factor value factor signal thereby obtaining the obtaining an output signal having a value of the concentration of the element substance in the test solution; and display means for presenting said concentration value.
1. An apparatus for determining the concentration of an element a substance in a test solution, which comprises analyzation means for determining the light transmittance of a the solution and for generating a first analog signal in accordance therewith; said analyzation means being adaptable for determining the light transmittance of a reference substance and also for generating a second reference analog signal in accordance therewith; conversion means for generating a first digital signal from said first and second reference analog signals, said first digital signal having a first numerical value associated therewith as representative of the optical density of said solution; and calculation means for calculating the percentage concentration of the element substance in said solution from said first digital signal, said calculation means including having generation means for generating and storing a second digital signal having a second numerical value associated therewith representative of the concentration of the element needed in said solution for said first numerical value to equal one; a standardizing scale factor value, a digital pulse generator for generating a first digital pulse train having pulses occurring at a predeterminable frequency and having first and second outputs;, frequency alteration means coupled to said conversion means and said first pulse generator output for altering said frequency in accordance with said first digital signal whereby a second digital pulse train is generated;, first counting means coupled to said second pulse generator output for counting the pulses occurring in said first pulse train;, second counting means coupled to said frequency alteration means for counting the number of pulses occurring in said second pulse train;, detection means for detecting when the number of said first pulse train pulses counted by said first counting means equals said second numerical value and for inhibiting said digital pulse generator when the equation occurs, whereby the number of pulses counted by said second counting means prior to the inhibiting of said generator represents the numerical value of the concentration of the element substance in said first solution.
2. An apparatus as claimed in
7. An apparatus as claimed in
8. An apparatus as claimed in
10. A method as claimed in
11. An apparatus as claimed in
12. An apparatus as claimed in
13. An apparatus as claimed in
14. An apparatus as claimed in
15. An automatic method as set forth in
16. An automatic method as set forth in
17. An automatic method as set forth in
18. An apparatus as claimed in
19. An apparatus as claimed in
20. An apparatus as claimed in
21. An apparatus as claimed in
23. An automatic method as claimed in
25. An apparatus as claimed in
27. An apparatus as claimed in
28. An apparatus as claimed in
30. An automatic method as claimed in
33. An apparatus as claimed in
36. An apparatus as set forth in
|
This invention relates to an electronic system and method for processing a signal obtained from the electro-optical analyzation of a precisely prepared serum chemistry.
The chemical analyzation of a serum, e.g., for the presence of sugar or albumin content, or any of many other assays vital to medical diagnosis, is generally performed by adding specific amounts of various reactive chemicals or reagents to a sample of serum in a specific sequence and under specified conditions of temperature and time thereby causing a change in color or light absorbance to occur which is related to the amount of the substance being measured in serum. Various manual and automated procedures have been used.
Manual procedures are usually performed in a laboratory by a trained technician. The technician prepares a test sample, commonly referred to as a test chemistry, comprised of a portion of a serum specimen to be tested and the proper amounts of the chemical reagents specified for that particular test. The resulting test chemistry, after formulation, must be analyzed with specific care taken to note the extent to which a desired reaction has taken place.
The reaction evaluation is done using a spectrophotometer. The output of the spectrophotometer represents the amount of a certain band width of light which the chemistry under test passes with respect to the amount of the same band width of light passed by a sample containing all other constituents in the test except the serum. The level of this comparative transmittance must be then transformed into units which represent the element concentrations or optical density of the test chemistry to present meaningful data to the technician so that he might evaluate the test.
Disadvantages of manual procedures include not only an undue amount of time and labor, but this type of laboratory testing is at most, even under the most optimum conditions only proportioned to the skill of the technician.
Several systems have also been proposed and used which present the optical density of test chemistries by means of a strip recorder. This technique results in a cumbersome amount of data paper, along with the inherent reading problems which are highly susceptible to error.
In accordance with the invention, a serum chemistry may be loaded into the flow cell of a spectrophotometer for optical analysis. The difference in light transmittance between an air path and a path through the test chemistry is detected by a photomultiplier tube, the output of which is connected to an amplifier and associated control circuits. Feeback means may be provided to automatically adjust the voltage across the photomultiplier tube to provide changes in its sensitivity due to operating temperature or to the wave length of the observed light.
The position of the flow cell may be used to set up logic conditions to institute the selective integration at the amplified photomultiplier tube output for both the test and reference air paths. The integrated value of the reference path signal is always greater than that of the integrated value of the test path signal since the reference path consists of air while the test path consists of test solution. The integrated value of the reference signal may be permitted to logarithmically decay until it equals that of the integrated value of the test signal. The time required for the integrated reference signal to decay to the value of the integrated test value is proportional to the optical density at the test solution. This relies in part on the relationship that optical density is equal to the logarithm of the incident light minus the logarithm of the transmitted light. The required decay time is transformed into a proportional digital pulse train and selectively placed in an optical density memory.
The processing of the digital representation of the optical density of a test chemistry is done under the control of a logic programmer section. This programmer section receives information from a programmed card which is interpreted by a card reader in a manner explained and described in a co-pending application, U.S. Ser. No. 179,133.
Several different types of tests may be programmed each of which require the processing of the optical density signal in a different manner. For the most part, the end point light absorbance of the reaction between a serum sample and test reagents is observed. The optical density of the reacted test chemistry may be compared within a calculation portion of the electronic system to that of a serum blank or a reagent blank. In the performance of the former, two serum samples are mixed with two different combinations of reagents to effect two different test reactions. The optical density of the first test chemistry must then be compared with the optical density of the second test chemistry to obtain the desired comparative optical density.
An end point reagent blank test requires that a chemistry consisting of reagents alone must be first spectrally analyzed and the resulting optical density reading stored for comparison with subsequent test chemistry readings. The test chemistries in this case are comprised of different serum samples all having the same reagents added to them.
A test may also be performed which requires that the optical density of the same test chemistry be ascertained at two precisely controlled points in time. Furthermore, it may be required that this be done for two or three such intervals to ensure that the reaction is taking place properly and is linear.
The arithmetic portion of the electronic system is preferably calibrated before the performance of any of the above tests to effect a standardization of the results with respect to a known base value and to simultaneously convert the optical density of the chemistries into concentration units. This calibration is completely automatic and may be done by the use of a solution with a known 64outputsection 100.
The read sequence, once initiated by the programmer 98 in this manner, is placed under control of the spectrophotometer logic 70. The resetting of the read command flip-flop 338 is performed by the timing out of its input from the output of the NAND gate 350 in the exponential discharge control 346. The resetting read command flip-flop 338 applies a true signal to the input of an inverting amplifier 638 whose output is applied to the output NAND gate 632 in the read control flip-flop 630. The resulting false signal on an input of this NAND 632 causes the flip-flop 630 to be reset. The resulting time output on this flip-flop 630 once again enables the 5 kilohertz clock gate 566 so that the 5 kilohertz clock is once again applied through the delay circuitry 576 to clock the binary counter 572 and preset each new counter value through the sixteen line decoder 578. This results in the fourth output of the line decoder 583 going true once again and the fifth output 584 going false.
The fifth output line 584 is connected to a NOR gate 640 whose output is connected through a second NOR gate 642 to the preset line of the blank storage register 102. The false signal on the fifth output line of the line decoder 578 presets the number which has been clocked into the optical density counter 108 during the read cycle into the blank storage register 102.
The sixth output line 585 of the 16 line decoder is not used so its output is ignored. The seventh output line 586 is clocked next which applies a false signal to a NOR gate 644 whose output is connected to the optical density counter presetting NOR gate 624. The resulting false signal on the output of this NOR gate 624 presets the optical density counter with the nine complement of the contents of the blank storage register 102.
The next output line 587 of the 16 line decoder 578 is inverted by a NOR gate 646 whose output is connected to the NOR gate 628 which applies the set to the read control flip-flop 630. The output on the eighth line 587 of the 16 line decoder is thereby used to initiate a second read cycle. During the first sequencing, as being explained here, of the sixteen line decoder the second read cycle is generally used to read the optical density of a standard solution which has been placed in the next test tube in the test wheel after that containing the blank solution. The concentration of this standard solution is a known value and is that value which was manually dialed into the standard units value switches 116 by the machine operator and which has previously been preset into the percentage concentration counter 112, through the multiplication accumulator 118 and into the calculation counter 110.
At the conclusion of the second read cycle, a reset signal is again applied from the read command flip-flop 338, inverted by the inverter 638 and used to reset the read control flip-flop 630. This resetting once again enables the five kilohertz clock to clock the binary counter 572 and preset the sixteen line decoder 578.
At the conclusion of the read cycle, the eighth line of the decoder 587 goes true once again and the ninth output line 588 goes false. This output line 588 is connected to the input of a NOR gate 648 which remains inhibited during this, the calibration sequence, by another input line 650 which comes from the program card reader and has a true signal on it unless a kinetic test sequence is in progress. During the kinetic test, however, this output 588 from the decoder would pass through the NOR gate 648 and through the blank storage register NOR gate 642 and be applied to the blank register 102 to preset the optical density counter contents into the blank storage register 102.
The next output line 589 of the decoder 578 also is used to control a kinetic test. It is connected to the input of a NOR gate 652 whose output is gated through another NOR gate 620, inverted by an inverter 622 and applied to the optical density counter NOR gate 624 whose output is used to preset the optical density counter 108. This gating sequence is inhibited, however, by a second input to this first NOR gate 652 which is the conductor 650 coming from the card reader on which the kinetic test is selected.
The next output line 590 of the decoder to go false is connected to two NAND gates 532 and 538 through an inverter 534 to enable those NAND gates 532 and 538. The gates 532 and 538 are used to set and reset, respectively, the flip-flop 630 in the multiply/divide select circuitry 126. Their enablement permits the selection of the proper path for the DRM and master counter clock outputs. Since this is the first cycle of the 16 line decoder, a calibration mode is assumed to be under way. However, the false signal on the eleventh output line 590 of the 16 line decoder enables the NAND gates 532 and 538 in a test mode also. The differentiation between the test and calibration modes is made by using input lines 654, 655 and 672 from a patient-identification decoder. If an end point reagent blank (EPRB) test has been programmed the signal on the input conduct 654 is inverted by an inverter 656 and applied to two NAND gates 658 and 660. The output of the first of these NAND gates 658 is applied to the multiply/divide input NAND gate 662 and to the blank storage register resetting NAND gate 602 603. This NAND gate 602 603 is enabled whenever it receives a false signal from the first output line 580 of the programming decoder 578.
The first of the EPRB NAND gates 658 also has an input from an inverter 664 whose input is connected to the output of a NAND gate 666 which comes from the blank and standard solution detection circuitry which will be explained below.
Similarly to the above, the end point serum blank (EPSB) line 656 655 from the program card reader has its signal inverted by an inverter 668 and is applied to the input of two NAND gates 669 and 670. The output of the first of these NAND gates 669 is also applied to the same NAND gates 662 as the output of the EPRB test NAND gate 658.
An output from the programmer signifying that a kinetic test has been programmed is supplied by a conductor 672 through an inverter 673 to the input of two NAND gates 674 and 675. The output of the first of these NAND gates 674 is applied as an input of the NAND gate 662 whose other inputs are from the EPRB and the EPSB NAND gates 658 and 669, respectively. The output of this NAND gate 662 is the multiply or divide information which selects the proper gating within the multiply and divide selection circuitry 126. It is important also at this point to recall that at the beginning of each test being performed, i.e., the EPRB, the EPSB or the kinetic test, a calibration of the calculator section 100 is necessary and is performed by analysis first a blank chemistry and then comparing the blank chemistry reading with the reading obtained from a standard chemistry for which the percentage concentration is known.
During the calibrate mode for each of the above tests, the output of the NAND gate 662 whose inputs signify the type of test selected is false during a calibration mode and true during the actual test performance. This output is, in part, decided by the inputs to each of the NAND gates 658, 660, 669, 670, 674, and 675 that each have one input from the card reader and another input from an inverter 664 whose input is supplied from the NAND gate 666 leading from the blank and standard detection logic.
This logic comprises five NOR gates 676-680 which receive, as will be explained, their inputs from conductors leading from the main machine control logic. These lines 681 through 688 represent the position number, i.e., one to one-hundred of the test chemistry under analysis at any given moment. The lines are weighted, respectively, with weights of one, two, four, eight, ten, twenty, forty and eighty. True signals are selectively applied to these conductors to represent the particular test tube in the test extraction position. The first input line 681 is applied to the first NOR gate 676 and to another NOR gate 689. The second input line, representing the second test tube position is similarly connected to the input of the second 677 of the first series of NOR gates 676 through 680 and also to another NOR gate 690. The outputs of the two second series NOR gates 689 and 690 are applied as inputs to two controlling NAND gates 691 and 692.
The third and fourth input lines 683 and 684 are both applied through a first series NOR gate 678 to the inputs of both of the controlling NAND gates 691 and 692. The fifth and sixth inputs 685 and 686 are both applied to a NOR gate 679 and the last two inputs 687 and 688 are both applied to the last NOR gate 680. The outputs of these latter two NOR gates 679 and 680 are both applied to a NAND gate 693 whose output is inverted by a NOR gate 694 and applied to both of the controlling NAND gates 691 and 692. Only when the first or second input lines 681 and 682 are true will either of the controlling NAND gates 691 and 692 have a true output. This is because only the first two test tube positions are used to hold the calibrating blank and standard solutions.
The second of these NAND gates 692 has a true output when the solution in the first test tube is being analyzed and represents the blank chemistry signal. The first of these NAND gates 691 has a true output only during the second analysis which is that of the known standard solution. The outputs of both of these NAND gates 691 and 692 are applied to the input of the NAND gate 666 whose output and inverted output is applied to all of the test selection NAND gates 658, 660, 669, 670, 674, and 675. A true signal on either of these inputs is used to gate the respective NAND gates so that the output of the multiply-divide selection circuit input NAND 662 is false during the calibration mode and true during a test mode. The output conductor 514 of this NAND 662, as has already been explained, is applied to one controlling NAND 532 and inverted and applied to the other controlling NAND 538 for setting or resetting the selection flip-flop 530. These NAND gates 532 and 538 are disabled until the 11th output line 590 of the line decoder 578 goes false.
The 12th line 591 of the line decoder 578 is applied to a NAND gate 696 in the calculation control. The output of this NAND gate 696 is applied to the NAND gate 456 which sets the calculation control flip-flop 454 as previously explained. To reiterate, the output of this flip-flop 454 is inverted by a NAND gate 460 and used to enable a NAND gate 462 whose other input is from the one megahertz clock 94. The enabling of this NAND gate 462 allows the master counter 104 to be clocked. If a calibration mode is under way, the one-hundred kilohertz output of the master counter will be applied to the clocking input of the percentage concentration counter 112 while the one-hundred kilohertz signal will also be multiplied by the contents of the optical density counter 108 in the digital rate multiplier 124 and applied to the calculation counter 110. If, on the other hand, a test is under way, the 100 kilohertz master counter output will be applied to the calculation counter 110 and the digital rate multiplier output will be applied to the standard units value counter 112. The fill detector 128 resets the calculation control flip-flop 454, as also previously explained, and enables another NAND gate 458 which permits the printer to be clocked from a five kilohertz supply. The latter enablement is also dependent upon a print command originating in the programmer.
The 13th pulse received by the binary counter 572 which is decoded by the line counter 578 places a false signal on the 13th output line 592 of the decoder 578. This false signal on the 13th output line 592 is applied to a NOR gate 698 whose output is applied through a second NOR gate 616 to the preset input of the multiplication accumulator 118. This sequencing is used in the calibration mode to preset the standard units value into the multiplication accumulator 118 from the percentage concentration counter 112 during the calculation enablement by the calculation control flip-flop 454. During test mode, however, another input 699 to the first NOR gate 698 has a true signal imposed on it by the three test mode NAND gates 558 658, 669 and 674. The output of these NAND gates is true whenever both inputs to their input NAND gate 666 are true signifying that the contents of either the first or second test tube is not being examined so that a test must be under way.
The 14th output line of the line decoder 578 is the next to go false. This output line 593 is used to initiate the print command to the printer logic 132. Its false signal is applied through two inverters 700 and 701 and inverted again by a third inverter 702 after having its pulse width extended by a capacitive and resistive combination 703. The output of the third inverter 702 is inverted once again by a NAND gate 704 before the print command signal is applied to the print gating NAND 458 which has already been enabled by the termination of a calculation mode by the calculation control flip-flop 454. The other input of this NAND gate 458 is a five kilohertz clock which is used to gate the printer logic sequencing as will hereinafter be described.
The next output line 594 of the line decoder 578 is applied to a NOR gate 706 which is enabled by its other input from the card reader which signifies that a kinetic test has been programmed. If this is the case, this NOR gate 706 will be enabled to put a true signal on its output which is used to initiate the operation of a one-shot 708. The subsequent false going output of this one-shot 709 is connected by a line 709 to reset the binary counter 572 when the one-shot is pulsed by the NOR gate 706. The pulse width of the one-shot output maintains this reset condition on the counter 572 until after the occurrence of the next clock pulse from the five kilohertz clock. The one-shot then times out so that the value preset into the sixteen line decoder 578 is a zero. This has the effect of putting a false signal on the first decoder output line 580 and begins a kinetic recycling of the line decoder outputs to re-read and re-evaluate the same test chemistry at later points in time. This kinetic recycling will continue until the kinetic recycle NOR gate 706 is disabled by its input line from the card reader. The number of recycles is controlled by the main control logic so that when the desired number of recycles has been completed the enabling line to this NOR gate 706 again goes true.
At the conclusion of a test or calibration mode, the 16th output line 595 of the line decoder 578 goes false to initiate a programmer stop and a reset sequence. This output 595 is applied to a NAND gate 712 whose output is inverted by an inverter 713 and applied to the reset input of the programmer control flip-flop 562 to reset that flip-flop and await the next program start pulse. The main sequencing of the 16 line decoder 578, as just described, is identical in the calibration mode for both end point reagent blank test and the end point serum blank test. The kinetic calibration mode, however, is different in some aspects. During the first time period when the fourth output line 583 of the decoder is false, which is used in the EPSB and EPRB to initiate a read command, an output of the kinetic calibration NAND gate 675 is inverted by an inverter 714 and used as an inhibiting input to the NOR gate 626 whose other input is the fourth decoder output line 583. The output of the inverter 714 is also used as an input for the NOR gate 646 which has, as another input, the 8th output line 587 from the decoder, which, for the other test modes, is the read command for the standard solution. These two NOR inputs from the inverter 714 are used to inhibit any reading during the kinetic calibration interval because the kinetic test does not rely on any test standard or test blank for its results but is concerned with changes in each of the examined test chemistries during a precise interval of time.
Each of the three test modes has its own particular requirements. The EPRB test requires the optical density of the blank test chemistry to be stored in the blank storage register 102 after the calibration process. The output of the EPRB test NAND gate 658 is applied as an inhibit to the NAND gate 602 603 which thereby prohibits the blank storage register 102 from being reset. The percentage concentration counter 112 as well as the multiplier accumulator 118 are inhibited from being reset during the EPRB, or actually any other test, by an inhibit line 699 which is true during any test, and which is connected to the output of each of the test NAND gates 658, 669 and 674. The output of the EPRB test NAND 658 is also applied through an inverting amplifier 714 715 to inhibit the operation of two NOR gates 644 and 640. The outputs of these NOR gates 644 and 640 thereby inhibit the presetting of the optical density counter 108 and the blank storage register 102, respectively.
The performance of a test implies that neither a test blank nor a standard solution is being analyzed. As previously explained, a true signal has been applied to the multiply and divide input conductor 514 to permit the subsequent one-hundred kilohertz master counter output to be applied to the calculation counter 110 and the digital rate multiplier output to be applied to the percentage concentration value counter 112. As also previously mentioned, the input conductor from the test NAND gates 658, 669 and 674 maintains an inhibit upon the multiplier accumulator preset so that at the conclusion of a test sequence, the test value is not preset into the multiplier accumulator as was the standard units value during the calibration mode.
The end point serum blank test is different from the end point reagent blank test in that two test chemistries are prepared from each serum sample. For this reason, the resetting of the blank storage register 102 is not inhibited when the first output line 580 of the line decoder goes false to reset that register. The presetting of the blank value into the blank storage register 102 when the fifth output line 584 of the 16 line decoder 578 goes false and the presetting of the nines complement of the contents of the blank storage register 102 into the optical density counter 108 on the next count is not inhibited in the EPSB because the value of the first chemistry must be subtracted from that of the second to arrive at the required results.
A kinetic test is different from the two end point tests in that the kinetic test is used to determine a net rate of change instead of taking a reading at only one interval of point in time. The kinetic test is such that three pairs of readings are taken to ensure that the reaction of the test chemistry was linear and was not affected by an environmental influence which would affect the test parameters. Each test chemistry is examined a total of six times. Since only two read signals are obtained for each complete cycle of the binary counter 572 in the programmer control, the 16th output line 595 of the decoder 594 is used, as previously explained, to recycle the counter 572 and decoder 578. The recycling continues until a counter set in and by the main machine control logic places a true signal on the inhibit line 707 to the recycling NOR gate 706. The time between the two readings taken in each pair of readings must be precisely controlled from the main machine control logic. In the kinetic mode, read pulses are applied the kinetic enable line is connected to the input of the NAND gate 539 to disable said gate from passing program read pulses from NOR gate 534 NOR gate 543 whose other input is from the output of the program read pulse NAND gate 543 which inverts its input from the kinetic program inhibit gate 544. The kinetic read pulse train is also applied to a NOR gate 716 which is gated ON by a false signal from the kinetic mode enable line from the card reader signifying a kinetic test has been programmed. This false kinetic mode signal is also inverted by a NOR gate 717 and used to inhibit the one-shot 538 output NOR gate 541 553.
Each of the kinetic read pulses occurring for a pair of readings are for a card programmed time interval, while the pairs of pulses are preferably four seconds apart. The kinetic read pulse train is applied by its read control NOR gate 545 556 to the input of the read control flip-flop 630 output NOR gate 634. The output signal of this NOR 634 is inverted by an inverter 636 and applied to the read command flip-flop 338.
The 16 line decoder 578 thereby recycles three times to complete a kinetic test of one test chemistry. At the conclusion of the test, the 16th output line 595 of this decoder 578 will go false to stop and reset the programmer as before explained.
The base kinetic test presupposes that the optical density of the test chemistry will increase over the time of the test interval. There are, however, some tests which are performed which rely on a decrease in optical density of a solution from a known standard as the test chemistry is allowed to react. The ninth and tenth output lines 588 and 589 of the 16 line decoder 578, when sequentially pulsed with a false signal, are used to initiate the special conditions for the optical density loss kinetic test. The output of the 9th line 588 is applied as an input to one of the NOR gates 648 which control the presetting of the optical density counter content 108 into the blank storage register 102. When this line 588 goes false, the true output on the NOR gate 648 is applied to a second NOR gate 642 for presetting the blank storage register 102 with the difference in the optical density of the test chemistry determined from the first pair of readings.
The 10th decoder output line 589 is used as an input to a NOR gate 652 which controls, by means of two other NOR gates 620 and 624 and an inverter 622, the presetting of the optical density counter 108. The false signal on the 10th output line 589 of the decoder causes the optical density counter 108 to be preset with the nines complement of the difference value previously preset into the blank storage register 102. This nines complemented value of the net change in optical density during the interval between readings is then used to alter the master counter output in the digital rate multiplier 124. The effect of this is to recognize the negative change in the optical density occurring between readings.
Each cycling of the 16 line decoder 578 causes a false signal to occur on the 14th output line 593 of the decoder. The false signal on this line is the print enabling signal which controls a NAND gate 458 to allow a five kilohertz oscillator output to be gated to the printer. The printer logic 132 is responsible for supplying the printer 134 with the proper signals delineating the correct column and the information to be placed in that column.
The preferred embodiment of the invention processes the output signals from the program card read specifying the number of the test under way, the patient-identification number corresponding to the test chemistry being analyzed at that moment and the test results from the percentage concentration counter 112. The printer used is a conventional drum printer having a master drum and a secondary control drum. The master drum has a capability of 16 different characters and may print in all or part of 21 columns. The master drum has a magnetic disk on its surface which is detected by a magnetic detector once each time the master drum makes one revolution. The secondary drum has two magnetic disks on its surface which are in close proximity to one another. The secondary drum makes 16 revolutions for each revolution of the master drum. The magnetic disk on the master drum and the first occurring such disk on the secondary drum are detected at the same time to initiate a master reset signal and so that the next 16 pairs of signals from the secondary drum will be in synchronization with the characters presented on the master drum.
The printer logic 132 is shown in detail in FIG. 19 through FIG. 25. The pulse originating from the master drum disk detector (not shown) is applied to a wave shaping circuit 720 for squaring the pulse and applying it to an output line 721. Similarly, the double pulses of the secondary drum are applied to a wave shaping circuit 722 and the resulting square pulses are applied to an output conductor 723. The output conductor 721 from the master drum pulse shaping circuit 720 is connected to the reset input 724 of a J-K flip-flop 725.
The occurrence of a master drum pulse resets this flip-flop 725 and places a false signal on its J output 726 and a true signal on its K output 727. The output line 723 from the secondary drum pulse shaping circuit 722 is connected to clock this J-K 725. The pulse coming from the master drum pulse shaping circuit 720 occurs at the same point in time as the first pulse in a pair of pulses coming from the secondary drum pulse shaping circuit 722. For this reason, the first such pulse from the secondary drum has no effect upon the J-K flip-flop 725 because the reset input 724 is held false by the pulse from the master drum pulse shaping circuit 720. The second and closely following second pulse from the secondary counter is applied, after shaping, to the clock input 728 of the flip-flop 725. The occurrence of this second pulse begins what will hereinafter be referred to as a window time. This window time extends until the occurrence of the first pulse from the secondary drum on its next revolution.
The first pulse from the secondary drum after the reset pulse, clocks the J-K flip-flop 725 to put a true output on its J output line 726 and a false on the K output line 727. The K output line 727 is connected to the input of a NAND gate 729 and an inverter 730. The NAND gate 729 inverts the true signal on the K output 727 and applies this false signal to the outputs of ten comparator output NAND gates 731 through 740 to remove an inhibit on these gates.
The output of the inverter 730 is applied through two NAND gates 741 and 742 to the reset input conductor 743 for a series of line storage flip-flops 744 through 750. The operation of these flip-flops will be described below.
The first in the pair of pulses from the secondary drum on its second revolution pulses the clock input 728 of the J-K flip-flop 725 to terminate the first window time. The resulting false going signal on the J output 726 clocks a window number counter 752 to put a one in that counter. The window number counter 752 is capable of storing a five bit binary number.
The first occurrence of the double secondary drum pulse signifies that the master drum has indexed to its first character position. This physical first position on the master drum contains the character zero in all 21 columns. A zero is looked for on all of the incoming lines from the standard units value counter 112, the patient-identification section of the control logic and the test number input from the card reader to determine if any zeros are to be printed. As will be described below, the presence of a zero on one of the input lines is detected by a series of comparator input NAND gates 753 through 757 whose outputs are compared with the outputs of the window number selector counter 752. If coincidence is ascertained, the output of a series of comparator output NAND gates 731 through 740 goes false. This false going signal is used to tell the remainder of the logic that one or more of the columns is to have a zero printed in it. A sweep register is then used to ascertain which column is to receive the zero character.
It has been found that to examine each of the 21 possible columns to see if that column is to get the character defined by the number of windows stored in the window counter 752 would require an inordinate amount of circuitry. For this reason, a time sharing of one group of seven general circuits is used thereby requiring the master drum to rotate three times instead of only once. To accomplish this, the occurrence of a master reset signal from the master drum shaping circuit 720 is applied to a conductor 760 which is connected to the reset input of a flip-flop 762, and to the reset inputs of three J-K flip-flops 763 through 765.
The K output 766 of the first of these J-K flip-flops 763 is connected to the inputs of two NAND gates 767 and 768. The J output 769 of this first flip-flop 763 is connected to the inputs of two more NAND gates 770 and 771. The J output 772 of the second J-K flip-flop 764 is connected to the clock input of the first J-K flip-flop 763 and to the second 767 and fourth 771 NAND gates. The K output 773 of the second flip-flop 764 serves as an input for the first 768 and third 770 of the NAND gates. The outputs of each of the first three NAND gates 768 through 770 is inverted by an inverting amplifier 774 through 776.
The output of the first inverter 774 is true during the first revolution of the master drum and then goes false as the second inverter 775 output goes true to signify the second revolution of the drum. Similarly, the third inverter 776 output goes true during the third revolution of the drum. These output signals are used to designate the three common groups of columns to be read on any given revolution of the master drum.
The two J-K flip-flops 764 and 763 are sequenced thro through the three common group designations I, II and III by a clocking conductor 777 leading from the two to the third output 778 of a recyclic four bit binary counter 779. The clocking for this binary counter 779 is provided through an inverter 780 and a NAND gate 781. The inputs for this NAND gate 781 come from the J output 726 of the J-K flip-flop 725 which clocks the window number counter 752. The other input to this NAND gate 781 is from the J output 782 of a J-K flip-flop 883. The J-K flip-flop 783 is set by an input from a NAND gate 784 whose inputs come from the K output 727 of the J-K flip-flop 725 which clocks the window selection counter 752. The other input to this NAND gate 784 is from the J output 785 of the J-K flip-flop 765 which resets the recyclable binary counter 778 779.
In operation, the J output 726 of the J-K flip-flop 725 clocking the window selection counter 752 goes false for every other input pulse it receives from the secondary drum. The true signal on the output of the NAND gate 781 is inverted in the inverter 780 and clocks the counter 779. The binary counter 779 continues to update until it has received its 16th clock pulse. At that time, the 23 weighted output line 777 goes false which clocks the three phase selector J-K flip-flop 764 and which causes the J output 772 of this flip-flop 764 to go true and the K output 773 to go false. This removes the true signal on the output of the common group I inverter 774. The true signal on the J output of the first flip-flop 764 also causes the common group II output inverter 775 to have a true signal, signifying that the second phase sweep is under way. The inversion of the signals on the outputs 772 and 773 of the first flip-flop 764 also cause the output of the pseudo setting NAND gate 771 to go true. This true signal is applied by a conductor 786 to the clocking input of the third J-K flip-flop 765. The flip-flop 765 is not clocked by the positive going signal since it requires a false going signal for clocking purposes.
The common group II sweep is thereby initiated to cause the appropriate characters to be printed in the columns, where selected, of the master drum control during phase II. The second revolution of the master drum takes place, as mentioned above, as the secondary drum rotates 16 times. The resulting clock pulses to the J-K flip-flop 725 which clocks the window number selector counter 752 thereby causes the J-726 and K-727 outputs to toggle back and forth. This toggling is detected by the input NAND gate 781 and inverter 780 to the recyclable binary counter 779 to clock that counter sixteen times during the second revolution of the master drum. The 16th clock pulse again clocks the second J-K flip-flop 764 which causes the output of the common group II output inverter 775 to go false and the common group III output inverter 776 to have a true output. The second clock pulse applied to the second phase controlling JK 764 also causes the clocking of the first JK 763. The resulting true signal on the input of the preset NAND gate 771 does not change the NAND gate output since the other input to this NAND gate 771 has gone false.
Once again the 16 clock pulses are obtained by the binary counter 779 before clocking the second control J-K flip-flop 764. The toggling of the outputs of this flip-flop 764 causes the output of the pseudo preset NAND gate 771 to go false, which clocks the J-K flip-flop 765 connected to its output. The toggling of the outputs of this J-K flip-flop 765 places a false signal on the K output 785 and a true signal on the J output 786 789. The J output 786 789 resets the NAND gate 784 to inhibit further setting pulses for the connected J-K flip-flop 783 from the K output 727 of the comparator control J-K flip-flop 725. The false K output 785 of the resetting flip-flop 765 resets the binary counter 779 and is inverted by two parallel inverters 788 and 790 to reset the digital comparator enabling gate latching flip-flop 783 and to enable the paper and ribbon advance in the printer (not shown).
The output of the pseudo preset NAND gate 771 is also applied to the resetting input of the control flip-flop 762 which it resets. The resulting signal on the output of this flip-flop 762 resets the first and second control J-K flip-flop 763 and 764 to return the output of the common group I inverter 774 to a true signal, which thereby is defined as the common group I condition.
The sequencing of the three printer common group signals I, II and III by the recyclic binary counter 779 is continuous because the master drum and the secondary drum in the printer are constantly rotating. This constant rotation applies pulses to the J-K flip-flop 725 which then accordingly clocks the window number selection counter 752. The recyclic counter 779 in the common group selection circuit is necessary to insure that all 16 indexes of the master drum are performed to permit all of the characters on the drum to be printed if they correspond to some printer logic character input. The print command from the programmer 98 is applied to the setting input of the binary counter control flip-flop 765. Until a print enable signal is received from the programmer this line remains true to hold a reset on the binary counter 779 and a reset on the flip-flop 783 with whose J output 782 is the digital comparator enabling signal applied to the NAND gate 741 in the comparator control.
The 5 kilohertz clocking input which is supplied to the printer from a gating NAND gate 548 and enabled by the calculation control flip-flop 545 454 as well as the print command NAND gate 703 704 is applied to a four bit binary counter 792. The output lines 793-796 of this counter 792 are then updated at a 5 kilohertz rate. The signals on these output lines 793 through 796 then pass through a four to ten line decoder 798. The first seven outputs 800 through 806 of this decoder 798 are inverted by inverters 807 through 813. The outputs of these inverters 807 through 813 change sequentially as the counter 792 counts from one to seven.
The inverter outputs are the seven column select scanning signals A through G. These signals, when gated with the I, II and III common group signals are used to scan through all twenty-one columns of the master drum during its three revolutions to initiate the printing of any character in any column. The common group I signal and the column scanning select signals A through G examine columns 1, 4, 7, 10, 13, 16 and 19. Common group II examines columns 2, 5, 8, 11, 14, 17 and 20 as the column select scanners scan from A to G. Common group III and the column select scanners together scan the remaining columns 3, 6, 9, 12, 15, 18 and 21. The preferred embodiment of the invention, however, uses only columns 3 to 6 for the test results. columns 9 and 10 for the patient-identification number and columns 12 and 13 for the test identification number. The combination of the A through G signals and the I through III signals are inhibited when any other columns are selected.
This inhibition is done by a series of 10 NAND gates 814 through 823. The operation of these NAND gates may be explained by way of example. As mentioned above, only columns 3 to 6, 9 to 10, and 12 to 13 are used by the printer logic so that, for instance, when column 8 is designated by the column select scanning signal output and the common group signal output, the digital comparator NAND gates 753 through 757 must be inhibited to prevent anything from being printed in that column. The column 8 signal is designated by the occurrence of the C columns select signal which occurs during the ON time of the common group II. These two signals are applied to one of the NAND gates 818 to make the output of the NAND gate 818 go true to inhibit the comparator input NAND gates 753 through 757. The last three output lines 824 through 826 of the 4 to 10 line decoders 798 are connected through a NAND gate 827 whose output signal is inverted by a NAND gate 814 to place an inhibit on the digital comparator NAND gates 753 through 757 whenever these last three lines go true.
The four place test results, as mentioned above, are printed in columns 3 through 6. Four input lines from each digit of the percentage concentration counter 112 where the test results are finally stored are applied to NAND gates 830 through 833, 834 through 837, 838 through 841 and 842 through 845. The four NAND gates 830 through 833 associated with the 1.0 digit of the percentage concentration counter 112 are all inhibited by the output of a NAND gate 846 which inverts the output of another NAND gate 847. The latter NAND gate 847 has two inputs, one from the column select A signal and one from the common group III signal. The occurrence of a false signal on both of these input lines signifies as explained above, that the number to be printed in column 3 is ready to be read. Both of these false signals on the input of the NAND gate 847 releases the inhibit on the input NAND gates 830-833 from the units digit of the standard units value counter 112. The true and false signals corresponding to that number from the units digits are then transferred to output lines 848 through 852 which are connected to the inputs of the comparator input NAND gates 753 through 757.
In a similar manner, common group I and column select signal B is applied to a NAND gate 853 whose output is inverted by an inverter 854 and used to release the inhibit on the NAND gates 834 through 837 which receive the true and false signals representing the number in the 10's digit of the percentage concentration counter 112. The outputs of these NAND gates are also applied to the common output lines 848 through 852. The 100's digit input from the percentage concentration counter 112 are inhibited by the signal from an inverter 855 and a NAND gate 856 until the occurrence of common group II and the B column selection signal. The last digit of the percentage concentration counter 112 is inhibited by the output signals from an inverter 857 and a NAND gate 858 until the occurrence of common group III and the B column selection signal. The three NAND gates 853, 856 and 858 also receive an input from the decimal point placement logic as will be described hereinafter.
In a manner similar to that in which the percentage concentration counter digits were applied to the printer logic, the patient-identification numbers to be printed in columns 9 and 10 are applied to two groups of four NAND gates each 860 and 861. Each of these groups of NAND gates 860 and 861 has four input lines which are weighted binarily from one to eight. The inhibit for the units digit NAND gate 860 is provided from an inverter 862 which inverts the output of a control NAND gate 863. The inputs to this NAND gate 863 are the common group I output line and the column selection D signal output line. The NAND gates associated with this digit 860 are inhibited until the concurrent occurrence of both of these signals.
In a similar manner the second group of NAND gates 861 is inhibited through an inverter 864 and a NAND gate 863 865 until the occurrence of the C column selection signal simultaneously with the common group III signal.
The comparator input from the test identification number which is to be printed in columns 12 and 13 is also provided by two groups of four NAND gates 866 and 867 which receive their numerical input from the test identification number from the program card reader and their inhibitor from an inverter and NAND gate 868 and 869. The output of the NAND gate grouping 866 corresponding to column 12 is inhibited until the occurrence of common group III and the column selection D signal while the NAND gate grouping 867 in column 13 is inhibited until the occurrence of the column selection E signal along with the common group I.
The common group numbers I, II and III are each present for a complete revolution of the master drum. During each revolution of the master drum, the magnetic disk on the surface of the secondary drum pass by their detector sixteen times so that the window number selection counter 752 counts from zero to 15 for each master drum revolution. The time interval between the detection of the second in the pair of magnetic disks on the secondary drum and the subsequent occurrence of the first such disk on the next revolution of the drum defines the window time. This is approximately 16 milliseconds. Concurrently with this, the column selection scanner signals A-G originate from a counter 792 which is being clocked at a 5 kilohertz rate. This results in the repetition of each of the column scanning signals A-G approximately five times during each window time.
The number of the particular window, i.e., zero to 15, corresponds to a character on the master drum. During the first window time only the character zero may be printed, during the second window time only the character one may be printed, only during the third window time may a character two be printed, etc. As mentioned previously in connection with the window number selection counter 752, this counter remains at zero during the first window time. At the conclusion of the first window time this counter 752 is clocked by the toggling of the outputs of its controlling J-K flip-flop 725 to increase its count by one. The output of the window number counter 752 is then one during the second window time which is the same as the character to be printed during that time, i.e., the character "I." The output of the window number counter 752 is always the character which may be printed by the master drum at that point in time. The sweeping of the column selection signals from A to G during the first window time and, assuming that this is the first rotation of the master drum so that the common group I signal is also false, will cause the tens digit of the standard units value counter 112 to be applied to the comparator input lines 848 through 852 upon occurrence of the D signal; will cause the second digit of the patient-identification number to be presented to the comparator lines 848 through 852 upon occurrence of the E signal. Since this is the first window, the window number selector counter 752 will have a zero output.
The presentation by any of these three information digits of the comparator input line 848 through 852 during their respective ON times, signifies that one or more of these digits is to receive a "O." The resulting true output on one of the comparator NAND gates 731 through 740 enables all the NAND gates 870 through 876 in the line storage section. The other inputs to these line storage NAND gates 871 thor through 876 are obtained from the G through A column scanning signals, respectively. The enablement of these NAND gates which occurs as a result of a zero being read during one of the column scanning signals A-G places a false output on the NAND 870 through 876 whose input is from that particular column signal A through G. The false signal sets the associated one of the line storage flip-flops 744 through 750. The outputs of these flip-flops are each applied to a transistor amplifier 877 through 883. When any of these line storage flip-flops 744 through 750 are set by the detection of coincidence between a character and a particular position of the master drum, the corresponding transistor amplifier 877 through 883 is activated to apply a ground to one side of printer hammer coils in the printer mechanism. The other side of these coils already has voltage applied to it from three other transistor amplifiers 884 through 886 which are turned ON by the common group signals I through III, respectively. Only one printer hammer may thereby be activated at any given time.
The secondary printer drum pulses the window number counter controlling flip-flop 725 each time it makes a revolution to increase the window number count by one. During each window interval, the column scanning signals are swept five times to ensure that the charactter corresponding to that window number will be printed in the correct column if such character is present on any of the input lines from the test identification number, the patient-identification number or the test results. The conclusion of the first 16 windows is noted by the recyclic binary counter 779 which controls the common group numbers I through III. This counter 779 then clocks its corresponding control J-K flip-flop 764 to initiate the common group II signal. Once again the system goes through 16 window times during which all of the inputs associated with common group II are examined for each of the characters. These too are printed under the control of the line storage flip-flops 744 through 750. The same process is again repeated for the common group III sweep.
The decimal point placement in the test results in column 3 through 6 is placed after the number in either column 4, 5, or 6. The decimal point is carried in the 11th row on the master drum so that when the window selection counter has reached a count of 11, the comparator input lines 848 through 852 are examined for that number. The decimal point placement is selected by the program card in the card reader. The card reader has three decimal point output lines 888, 889 and 890 corresponding to columns 4, 5, and 6, respectively. These become input lines 888 through 890 to the printer logic. Their respective signals are inverted in inverters 891 through 893 before application to three controlling NAND gates 894 through 896. These NAND gates 894 through 896 are sequentially gated ON and OFF by the occurrence of the common groups I, II and III during the column selection D signal. In a manner similar to that for a numerical character, the outputs of these NAND gates 894 through 896 are applied through another NAND gate 897 to a series of five NAND gates 898 through 902 which, when receiving a signal from the preceding NAND gate 897 automatically places the equivalent of the number 11 on the comparator input lines 848 through 852.
The placing of a decimal point in columns 4, 5 or 6 is in effect an offset double strike in that column since that column will also have a number in it. The inhibiting of the three NAND gates 853 through 858 associated with the test results to be printed in columns 4, 5 and 6 are inhibited by an input line 898 903 from the last digit of the window number counter 752. This line goes true when the window number counter 752 has counted to 16. The other output line 899 904 of the last digit in the counter 752 goes false at this time. This latter output line 899 904 is used to inhibit the three decimal point NAND gates 888 894 through 890 896 before the count of 16 is reached.
The present invention provides a calculation system and method susceptible of use with other photo-optical inspection apparatus. Various modifications and departures may be made from the preferred embodiment shown within the scope of the invention in its broader aspects. For example, the output device may be a digital display which is selectively energized by a modification of the printer logic just described.
Durkos, Larry George, Cole, Robert Wayne, Denney, Jerry William
Patent | Priority | Assignee | Title |
4482251, | Oct 19 1981 | SCHIAPPARELLI BIOSYSTEMS, INC | Clinical analyzer |
4669878, | Jun 29 1984 | American Monitor Corporation | Automatic monochromator-testing system |
4720788, | Jun 20 1984 | Helena Laboratories Corporation | Diagnostic densitometer |
4848904, | Feb 16 1988 | Applied Biosystems, LLC | Dual beam multichannel spectrophotometer with a unique logarithmic data converter |
4933844, | Sep 26 1988 | Siemens Medical Systems, Inc | Measurement of blood lipoprotein constituents by analysis of data acquired from an NMR spectrometer |
5138551, | Dec 17 1988 | Behringwerke Aktiengesellschaft | Process for improving the accuracy and reproducibility of data measured in immunometric tests |
8632730, | Nov 22 2005 | ALVERIX, INC | Assaying test strips having different capture reagents |
Patent | Priority | Assignee | Title |
3428796, | |||
3528749, | |||
3531202, | |||
3552863, | |||
3553444, | |||
3609047, | |||
3633012, | |||
3652850, | |||
3701601, |
Date | Maintenance Fee Events |
Date | Maintenance Schedule |
May 04 1979 | 4 years fee payment window open |
Nov 04 1979 | 6 months grace period start (w surcharge) |
May 04 1980 | patent expiry (for year 4) |
May 04 1982 | 2 years to revive unintentionally abandoned end. (for year 4) |
May 04 1983 | 8 years fee payment window open |
Nov 04 1983 | 6 months grace period start (w surcharge) |
May 04 1984 | patent expiry (for year 8) |
May 04 1986 | 2 years to revive unintentionally abandoned end. (for year 8) |
May 04 1987 | 12 years fee payment window open |
Nov 04 1987 | 6 months grace period start (w surcharge) |
May 04 1988 | patent expiry (for year 12) |
May 04 1990 | 2 years to revive unintentionally abandoned end. (for year 12) |