Field effect transistor memory cell

Abstract

A cross-coupled flip-flop stage, or memory cell, for a word oriented array of memory cells is developed from four insulated-gate field-effect transistors which perform storage, loading, and gating functions of the cell. The functions of the cell are controlled by three different voltage levels coupled by a word line to all cells of a memory word.

Associated with the array are bipolar transistor wordline-select and digit-write circuits used for achieving a low select-read-write cycle time for the memory cells.

Description

BACKGROUND OF THE INVENTION

PAC Field of the Invention

The invention is a memory cell that is more particularly described as an insulated-gate field-effect transistor (IGFET) flip-flop circuit.

Description of the Prior Art

In the prior art, the insulated-gate field-effect transistor has been arranged in various configurations of bistable stages, or cells, resembling bipolar transistor flip-flops. "Bipolar transistor" denotes a transistor, such as a conventional junction transistor, in which both majority and minority carriers are required for operation, whereas an IGFET is considered to be a unipolar transistor in which only majority carriers are required for operation. Conduction in an IGFET device is controlled by signals applied to a control electrode without current between that electrode and controlled electrodes because the control electrode in insulated from the controlled electrodes. In bipolar transistors, there are current paths connecting the control electrode to the controlled electrodes. IGFET memory cells are also known to consume significantly less power than bipolar transistor cells.

In the prior art, each IGFET memory cell generally requires at least four leads to the cell, a pair of cross-coupled IGFET devices, a pair of load devices, and two additional IGFET devices for gating information into and out of the cell.

The cost of an IGFET memory system includes the sum of the cost of peripheral circuits plus the product of the number of cells times the cost per cell. The number of cells per system usually is controlled by the job to be performed by the system and is therefore a constant. System cost can be reduced by utilizing inexpensive cells. To achieve a reduction of system cost, the overall decrease of cost in providing all of the cells must be greater than any resulting increase in the cost of peripheral equipment.

An IGFET memory cell can be constructed as an integrated-circuit which is built in a semiconductor substrate. The cost of each IGFET memory cell is largely dependent upon the amount of semiconductor substrate area required for the cell and therefore The cell is considered to be in an active state when information is being written into or is being read out of the cell. At other times the cell is in a quiescent, or standby, state. , and also described in the "1967 International Solid-State Circuits Conference Digest of Technical Papers," pages 74 and 75, FIG. 5(b). The detector there described can be used as a detector for signals from the herein disclosed invention when suitable well-known adjustments are made to coordinate impedances, signal levels and polarities.

The above detailed description is illustrative of one embodiment of the invention, and it is to be understood that additional embodiments thereof will be obvious to those skilled in the art. The embodiment described herein together with those additional embodiments are considered to be within the scope of the invention.

Claims

1. A memory cell comprising:

first and second unipolar conducting devices each having a gate electrode and first and second controlled electrodes,

a source of reference potential,

means applying the reference potential to the first controlled electrode of the first device and to the first controlled electrode of the second device,

means coupling the gate electrode of the first device to the second controlled electrode of the second device.

means coupling the gate electrode of the second device to the second controlled electrode of the first device,

third and fourth unipolar conducting devices each having a gate electrode, a controlled electrode, and a threshold voltage,

means coupling the controlled electrode of the third device to the second controlled electrode of the first device,

means coupling the controlled electrode of the fourth device to the second controlled electrode of the second device,

a source producing three different potential level signals, all of said level signals having a potential different from the reference potential by a magnitude exceeding the threshold voltage of the third and fourth devices, and

means coupling the three level source to the gate electrodes of the third and fourth devices,

2. A memory cell in accordance with claim 1 further comprising:

a source of reference potential coupled to the first controlled electrodes of the first and second devices, a digit-write circuit,

means coupling the digit-write circuit to a second controlled electrode of each of the third and fourth devices, and

a detector coupled to the second controlled electrode of each of the third and fourth devices.

3. A memory cell in accordance with claim 2 in which:

the first, second, third, and fourth unipolar conducting devices are enhancement-mode insulated-gate field-effect transistors.

4. A memory circuit comprising:

first, second, third, and fourth insulated-gate field-effect transistors,

means cross-coupling the first and second transistors,

impedance devices, and

means connecting in a circuit loop the impedance devices, a conducting channel of the third transistor, a conducting channel of the first transistor, a conducting channel of the second transistor, and a conducting channel of the fourth transistor.

5. A memory system comprising:

a source of reference potential,

first and second semiconductor devices cross-coupled for bistable operation and connected to the source of reference potential,

additional circuit means for conducting current,

third and fourth semiconductor devices connected in series between the first and second devices, respectively, and the additional circuit means, said third and fourth devices each having a threshold voltage, and

means applying three selectable level signals to control conductivity of the third and fourth devices, all of said three selectable signal levels being different from the reference potential by a voltage exceeding the threshold voltage, whereby coupling is controlled between the first and second devices and the additional circuit means.

6. A memory system in accordance with claim 5 in which:

the third and fourth devices hold a first of bistable operating states of the first and second devices in response to a first level signal,

the third and fourth devices enable change of the operating states of the first and second devices in response to a second level signal, and

the third and fourth devices enable detection of the operating state of the first and second devices in response to a third level signal.

7. A memory cell having an active and a quiescent state comprising:

a bistable circuit,

means electrically coupled to said bistable circuit for setting said bistable circuit in one of a first and second condition,

means electrically coupled to said bistable circuit for detecting said one of a first and second condition during said active state and

a pulsed source only electrically coupled to said bistable circuit for maintaining said bistable circuit in said one of a first and second condition during said quiescent state.

8. A memory cell according to claim 7 wherein said bistable circuit comprises:

first and second transistors connected in parallel, an electrode of said first transistor being cross-coupled to a different electrode on said second transistor and an electrode of said second transistor corresponding to said an electrode of said first transistor being cross-coupled to a different electrode of said first transistor said last mentioned electrode corresponding to said different electrode of said second transistor.

9. A memory cell according to claim 8 wherein said transistors are field effect transistors, said an electrode of said first and second transistors is a gate electrode and said different electrode of said first and second transistors is a drain electrode.

10. A memory cell according to claim 7 wherein said bistable circuit further includes, an actuable transistor connected in series with each of said first and second transistors, a corresponding electrode of each of said transistors being interconnected.

11. A memory cell according to claim 10 wherein said actuable transistors are field effect transistors the gate electrodes of which are interconnected.

12. A memory cell according to claim 7 wherein said means for setting said bistable circuit during an active state includes,

first and second bit lines connected to said bistable circuit,

a word line connected to said bistable circuit and

a plurality of pulsed sources one of which is connected to said word line and others of which are connected to said first and second bit lines, said pulsed source connected to said word line and one of said pulsed sources connected to said bit lines being energized simultaneously to set said bistable circuit.

13. A memory cell according to claim 7 wherein said means for maintaining said bistable circuit during said quiescent state includes a pulsed source operable during both said active and quiescent states, and means connected to said pulsed source for activating said pulsed source only during said quiescent state.

14. A memory cell according to claim 13 wherein said means for activating said pulsed source includes a timer.

15. A memory cell having an active and a quiescent state comprising:

four semiconductor devices only, two of which are connected in a bistable circuit configuration,

means including the remaining two semiconductor devices electrically coupled to said bistable circuit for setting the state of said circuit,

means electrically coupled to said bistable circuit for detecting the state of said bistable circuit, and

a pulsed source only connected to said bistable circuit for maintaining the state of said bistable circuit during said quiescent state.

16. A complete semiconductor memory cell circuit comprising:

first and second resistors having respective source and drain electrodes, a channel region located therebetween, a gate electrode overlying the channel region, and the resistive value of each resistor responsive to changes in the voltage level of signals applied to the electrodes thereof;

first and second transistors having respective source and drain electrodes, a channel region located therebetween, a gate electrode overlying the channel region, the drain of the first transistor responsively coupled to the source of the first resistor and to the gate of the second transistor, the drain of the second transistor responsively coupled to the source of the second resistor and to the gate of the first transistor; and

a plurality of terminals selectively coupled to the respective drain and gate electrodes of the first and second resistors, and to the source electrodes of the first and second transistors, whereby when signals in the form of differences in voltage levels are selectively applied to the terminals, logic information may be applied to, stored in, and at a later

time read out of the memory cell.

17. The circuit recited in claim 16 wherein the geometric gain is less than ten.

18. A complete semiconductor memory cell circuit comprising:

first and second four-electrode amplifying means capable of functioning as load resistors and gating elements, and having resistive values responsive to changes in the voltage level of signals applied to the electrodes thereof;

third and fourth four-electrode amplifying means capable of storing logic information applied to the electrodes thereof, the first and third means responsively coupled to each other, the second and fourth means responsively coupled to each other, the third and fourth means responsively cross-coupled to each other for stability;

a plurality of terminal means selectively coupled to the amplifying means, whereby when signals in the form of differences in voltage levels are selectively applied to the terminal means, logic information may be applied to, stored in, and at a later time read out of the memory cell.

19. A circuit in accordance with claim 16 wherein the relative ratio is greater than 4.

20. A circuit in accordance with claim 16 wherein the relative ratio is less than 10.