Programmable automatic controller

Abstract

A programmable automatic controller for operating machines having a plurality of components which operate in a timed or sequential relationship with one another. The controller includes a timing means for generating cycle clock pulses in synchronism with the operation of the machine, wherein the cycle clock pulses provide an instantaneous indication of the time elapsed in each cycle of operation of the machine. A COM/MOS running storage means stores the relative times during each cycle of machine operation when each of the plurality of machine components are to be enabled and/or inhibited. When the time elapsed in a cycle corresponds to a component actuating time stored in the running storage, an actuating signal is generated by a comparator. This signal is coupled to a machine component addressing arrangement which provides a component enable or inhibit command signal to the addressed component whose actuating time compared to the cycle time lapsed. Accordingly, in a cycle of operation a plurality of component operating command signals are generated which command the respective machine components to initiate and terminate operation at preselected time intervals.

An up-down counter is provided for selectively varying the component machine actuating times stored in the running means while the machine is in operation. In addition, means are provided for initiating a machine starting or stopping sequence at any time during the machine cycle. The machine starting and stopping sequences are predetermined and can be varied at any time before the operation of the machine.

Description

BACKGROUND OF THE INVENTION

This invention relates to a programmable automatic controller for operating one or more machines having a plurality of functional components which operate in a timed relationship with one another.

In the past there has been a great need for a programmable controller for operating complex machines having components which operate in timed relationship with one another. For example, in the glass forming technology, glass forming machines are typically comprised of a plurality of individual sections which are integrated into a single plural section machine fed by a single source of molten glass. The sections are operated in synchronism in such relative phase relationship as to permit the several sections to acquire gobs in ordered sequence from a single gob feeding means. Thus, as one of the sections is taking a gob from the feeding means, another section is delivering a finished article to an output conveyor and the other intermediate sections are engaged in various forming steps intermediate the taking of a gob controlretracted113 103. The input at terminal 143 is thereby enabled and is coupled to the select gate 135 and then to the jam input of the up-down counter. This member which is 000 is not entered into the up-down counter however until the count of the counter reaches 360 as will be more fully explained hereinbelow. If on the other hand the "sooner" push button is depressed, then the up-down counter must count down. Accordingly, a logical zero appears at the control input of gate 139 and the input 141, which is the BCD number 359, is coupled via select gate 135 to the jam input of the up-down counter. This number will not preset the up-down counter to 359 however until the counter counts downwardly through 0 to 999.

The "sooner" control signal is also coupled to the control input of gating circuits 127 and 129. Gating circuit 127 detects when the count has reached 360° and the gating circuit 129 detects when the count has reached 999 from the count of zero. When the "later" button is pressed, gating circuit 127 is enabled. The input to the gating circuits 127 and 129, derived from input terminal 125, is the binary coded decimal output of the up-down counter. The outputs of the detect gating circuits 127 and 129 are coupled to a gating and logic circuit 37 with the output of the gating-logic circuit being coupled to the enable preset input of the up-down counter to thereby enable the signal at the jam input thereof to appropriately reset the up-down counter.

In operation with the function select signal switch 87 actuated, a degree count associated with the function selected is coupled into the up-down counter via the jam input thereof in the following manner. The degree gating number is coupled to the input terminal 133 of select gate 135, and passes through select gate 135 to the jam input of the up-down counter. This signal is entered into the up-down counter and appropriately presets the up-down counter when an enabling signal is provided to the logic gating circuit 137 from the comparator 93.

Next assume that it is desired to have the component being controlled actuated at a sooner time. The "sooner" button is depressed and the up-down counter begins to count downward. At the same time the input binary coded decimal number 359 at terminal 141 is coupled via select gates 139 and 135 to the jam input of the up-down counter. At the same time, the detect gating circuit 129 is enabled. Then, as the up-down counter counts downward through zero to 999, the detect gating circuit 129 provides an output pulse to gating logic 137. In the meantime, the gating logic has been enabled by a signal on line 145, which signal exists whenever the "sooner" or "later" button is depressed. Accordingly when the detect gating circuit 129 detects the number 999, a preset enabling pulse is coupled to the preset input of the up-down counter to permit the up-down counter to enter the number 359 therein. Then the counter continues to count downwardly until such time as the operator releases the "sooner" button.

Refer now to FIG. 6 which is a more detailed drawing of the circuitry for controlling the up-down counter. The select gates 135 and 139, shown in FIG. 5, are each comprised of three RCA CD 4019 quad and/or select gates connected in parallel. One input, that is, the A input to the select gates 139, is the numeral 359 and the other input B is the numeral 000, each in binary coded decimal form. These signals are appropriately gated to the next select gate 135 via a signal from the "sooner" push button which signal is a logical one when the count is up and a logical zero when the count is down. Thus, when the counter is going up, the B input to select gate 135, that is 000, is coupled in BCD form to the B input of select gate 135. At the same time the degree number from the memory circuit 72 is coupled to the A input of select gate 135. A second control signal, which is generated when either the "sooner" or "later" button is closed, is coupled to the control input of the select gate 135 to enable passage therethrough of the B terminal input signal. Thus, when the input at terminal 151 is a logical zero, the input at the B terminal is coupled through the select gate 135 to the output thereof, which output is coupled to the jam input of the up-down counter. On the other hand, when the input is a logical 1, the A input is coupled to the jam input of the up-down counter.

The combination of inverters and NOR gates designated by the numerals 153-155 are the 360 and 999 detect gates 127 and 129, respectively. Thus, the output of the up-down counter is coupled respectively to the units, tens and hundreds inputs of the gates 155, 154 and 153, respectively. The NOR gates designated by the numerals 999 each provide a logical 1 output when the output of the up-down counter is 999. This signal is coupled to a NAND gate 157. The NOR gates designated by the numerals 360 provide a logical one signal at their outputs when the output of the up-down counter is 360. This output is coupled to the input of a second NAND gate 158. The other input of NAND gate 157 derived from the control input to gate 139 is a logical 1 when the up-down counter is counting down and a logical 0 when it is counting up. The other input to NAND gate 158 is a logical 1 when the up-down counter is counting up and 0 when it is counting down. Accordingly, the NAND gates 157, 158 each provide at their outputs a logical 0 when a number is to be jammed into the up-down counter. Hence, the output of NAND gate 159, which is normally 0, goes to a logical 1 when the output of the up-down counter is either 999 or 360. When a logical 1 output is generated by NAND gate 159, the output of set-reset flip-flop 160 goes high to a logical 1 which output is coupled to one input of NAND gate 161. The other input to the NAND gate 161 is the inverse of the signal appearing at terminal 151 of gate 135, and accordingly is a logical one when the up-down counter is being stepped and a logical 0 when the up-down counter is not in operation. Accordingly, the output of NAND gate 161, which is normally a logical 0, becomes a logical 1 when either the numeral 000 or 359 is to be jammed into the up-down counter. This signal is coupled to one input of another NAND gate 162. The other input to NAND gate 162 is derived from NAND gate 163 which has at one input thereof a signal derived from the comparator 93 and at the other input a signal derived from terminal 151. Thus, when a logical 1 signal from comparator 93 is provided at the input of NAND gate 163, an output jam enabling signal is provided under the following circumstances: (1) when the "sooner" or "later" buttons have not been depressed and hence the signal at terminal 151 is 1 and the output of NAND gate 161 is 1, in which case the A input to select gate 135 from the flip-flops 71 is read into the jam input of the up-down counter; (2) when the "sooner" or "later" button is depressed and the comparator 93 has generated a logical 1 signal, and the number 360 or 999 has been reached by the up-down counter. In this case the number 000 or 359 is read into the up-down counter. In each of these cases a logical 1 signal is provided at the output of NAND gate 162 to thereby cause the signal at the jam input of the up-down counter to preset the up-down counter.

Refer now to FIG. 7 where there is disclosed a simplified block diagram of the start-stop memory unit illustrated in FIG. 2 and designated in FIG. 3b by the numeral 68. The timing storage unit 171 includes the circulating memory comprising the set-reset flip-flops 71 and ten 64-section shift registers 72. The machine degree counter 172 includes the pulse generator and the degree counter 55, both illustrated in FIG. 3b. The outputs of the timing storage and the degree counter are each coupled to the comparator 69 which provides an appropriate output signal when a comparison exists. This signal is coupled via an inverter 74 and an OR gating circuit 73 to a decimal decoder 75. Each of these elements are illustrated in FIG. 3. The output of the comparator 69 is also coupled to a second comparator 173.

When a comparison is made in comparator 69, the particular memory address in the binary address counter 77 corresponding to the machine element to be controlled at that point in the cycle is coupled to the decimal decoder, decoded and then coupled to a latch circuit 76 which provides a command signal for energizing output driver 78 associated with the latch count. At the same time comparator 173 compares the address in the run memory binary address counter 77 with a corresponding address in the six random access memories (RAMS) in address memory 180. Each of the six random access memory units are capable of storing 64 bits. Accordingly, since the 6 RAMS are connected in parallel, 64 six-bit machine addresses can be stored therein. However, in the preferred embodiment wherein a glass forming machine is being controlled, only nine addresses are stored therein.

However, unless the start or stop switch is closed on its contacts, the comparator 173 will not provide an output since gate 177 is inhibited. When, for example, stop switch 175 is closed on its contacts, the set-reset flip-flop 176 provides a logical one output which is coupled to gate 177 and gate 178. Gate 177 is thereby enabled to couple the output of comparator 173 to a stepping counter 179. The stepping counter steps the next address in the 6 RAM address unit 180 so that it can be compared in comparator 173. The output of the counter 179 addresses sequentially each of the nine stored address words depending upon the count of the output of the counter. The output of the counter is also connected to a BCD to decimal decoder 181 which converts the binary output of counter 179 to a corresponding decimal output. Accordingly, the output of the decoder 181 is in the form of nine parallel outputs which are connected to an associated one of nine RAMS in function memory 183. Each RAM in memory 183 stores an inhibit or an enable signal for 64 outputs. Thus, each RAM provides an output for each storage section in the 64 word storage of the run memory 72 of FIG. 3. Thus, when counter 179 makes a first count, an output from the decoder 181 is coupled to the first RAM in storage 183 to enable the first RAM. The inhibit and enable signals in enabled RAM are gated through gate 178 and OR gate 73 to the decimal decoder 75. Decimal decoder 75 is inhibited or enabled depending upon the output of the enabled RAM of storage 183 to thereby selectively couple output signals to the latches 76 which in turn drive selected output drivers 78. The sequence in which the enabling and inhibiting signals are coupled to gate 178 from storage 183 is controlled by the output of run memory binary address counter 77 which addresses the 64 storage locations in the first RAM in a sequential manner. After the first RAM has been read out, the machine cycle continues until another compare exists in which case, the count of counter 179 increases and the second RAM in memory 183 is enabled, and so on.

The shutting down process continues with counter 179 progressively stepping the address memory 180 and the nine RAMS of the function storage 183 until the machine has been shut down. A similar operation with a second set of address function memories occurs when a machine is to be started up.

Refer now to FIGS. 8a and 8b for a more detailed discussion of the start-stop memory arrangement of the present invention. Two separate memories are provided, a starting memory which includes a six RAM address storage 180' and a 5-RAM function storage 183'. The stop memory includes a 6-RAM address storage 180 and a 9-RAM function memory 183.

The operation of the stop memory will now be discussed in detail. When the machine being controlled is to be stopped, the stop button 175 is closed to thereby set flip-flop 176 so that a logical 1 is coupled to gating circuit 177 to thereby enable the gating circuit. At the same time, a logical 0 is coupled from flip-flop 176 to gating circuit 185 to inhibit the gating circuit 185. In the meantime, the binary address counter 77 sequentially provides the address of each of the 64 machine functions to comparator 187. The other input to comparator 187 is from the 6-RAM address storage unit 180 which provides the address of the machine components to be inhibited during the shutting down process. When a stored degree number in the running memory 72 of FIG. 3 compares with the machine degree counter output, a strobe signal is applied to comparator 187. With comparator 187 enabled, the address output of counter 77 is coupled to one input of the comparator and the first address in the address memory 187 is coupled to the other input thereof. If a comparison exists, then an output from comparator 187 is coupled to BCD counter 179 via gating circuit 177, NOR gate 189 and an inverter 191. The BCD counter counts a pulse and steps the address storage unit 180 to the next address location. At the same time, the output of the BCD counter 179 is coupled to a BCD to decimal decoder 181. The output of the decoder 181 is in the form of ten parallel output circuits of which only nine are utilized in the present invention. The nine output circuits are each coupled to a separate RAM in the function storage unit 183. Thus, when BCD counter 179 receives a first pulse from comparator 187, the first output circuit of the BCD to decimal decoder 181 is energized to enable the first RAM. Under normal operating conditions, the first RAM reads out a plurality of enable and inhibit signals in a sequential order controlled by the binary addresses stored in counter 77. Thus binary address counter 77 provides a sequence of up to 64 addresses to the first enabled RAM so that the RAM reads out in sequential order up to 64 commands, the commands being either to enable or inhibit a corresponding component of the machine being controlled. The output of the function memory 183 is coupled to an OR gate 193, the output of which is coupled to the binary to decimal decoder 75, shown in FIG. 3a.

The next time a comparison is made between a stored degree number and the machine degree count, a strobe signal is coupled to comparator 187 to enable the comparator. The second address stored in address storage 180 is compared with the binary address of counter 77 and when a comparison exists, the BCD counter 179 is advanced a second step. Hence, the address stored in address storage means 180 is stepped one position and the second RAM is enabled. In accordance with the sequence dictated by the output of the binary address counter 77, a second sequence of enables and inhibits are generated by the memory unit 183 and coupled to the output via select gate 193 for controlling the shutting down of the machine being controlled. The aforementioned sequence repeats itself each time until the machine has been completely shut down. After nine cycles of operation have been completed, the BCD to decimal counter 181 provides an inhibitor output to NOR gate 189 which prohibits further stepping of the BCD counter 179. Thus, the shutting down function provided by the stop memory is completed.

The timing for reading out each of the RAMS is provided by a clock strobe signal on line 203 while the control of reading and writing commands out of and into the RAMS is provided by an appropriate signal on line 205. Hence the signal on line 205 dictates whether data is being read into the RAM or read out thereof. The particular machine control instructions written into each RAM are provided on line 207 from the preload shift register 25. Thus, if the first RAM is to be loaded with a selected number of enable signals and a selected number of inhibit signals, the select gate 209 is enabled by a control signal on line 211 to conduct a first pulse from the preload shift register 25 to the jam input of BCD counter 179. The output of the BCD counter 179 is converted to a decimal signal by decoder 181 which provides an enabling signal to the first RAM of the function memory 183. With the appropriate write signal on line 205, the selected enable and inhibit commands are read into the RAM in accordance with the sequence dictated by a signal from the preload shift register 75 via the select gate 197. The process repeats itself with a second input pulse coupled to select gate 209 to thereby step counter 179 to the second RAM. The inhibit and enable commands for the second RAM are then read into the memory 183. This process repeats itself until all nine RAMS are loaded and the system is ready for operation.

The stop memory arrangement is quite flexible since a machine having a plurality of movable components can be stopped in a single step or in a plurality of steps up to nine, as contemplated by the preferred embodiment. However, it should be understood that as many shut-down steps can be provided as desired by merely providing an extra RAM for each extra shutting down step. Further, the sequence of shutting down the machine can be varied by appropriately writing in new commands to the RAMS via line 207 from the preload shift register.

If, for example, the machine to be controlled is to be started up, the start button 210 is depressed to thereby provide an input signal to the reset input of the flip-flop 176. The flip-flop 176 provides an output in response thereto which turns off gating circuit 177 and turns on gating circuit 185. With gating circuit 185 enabled, comparator 211 compares the output of the binary address counter 77 with the storage address in the address storage memory 180'. If a comparison exists, comparator 211 provides an output which is coupled to the BCD counter 213 via NOR gate 215 and the inverter 217. The BCD counter provides a stepping signal to the address memory 180' to designate the next succeeding address to be read into the comparator 211. At the same time the output of the BCD counter is decoded by a BCD to decimal decoder 219. The decoder 219 utilizes only five of its ten output terminals which outputs are coupled to five random access memory units in the function storage 183'. As in the case with the stop memory unit, the output of the decoder sequentially enables the five random access memory units as the BCD counter 213 is stepped by pulses from comparator 211. Each of the random access memories includes enable and inhibit commands for each of the 64 storage units or addresses in the run memory. Thus, when the first random access memory is enabled by an output from the decoder 219, the commands in the random access memory are sequentially read out in a sequence dictated by the output of the binary address counter 77. The command signals are coupled to select gate 193 and then coupled to one input of OR gate 73 which is illustrated in FIG. 3b. The output of the OR gate 73, as aforementioned, is coupled to the inhibit input of the binary decimal decoder 75 for appropriately energizing selected flip-flop latches associated with the respective machine components. It should be understood that while only five RAMS are disclosed in the preferred embodiment, as many RAMS as desired could be utilized in keeping with the present invention provided there is one RAM for each starting up step.

The input data to the function memory 183' for initially storing the commands in the various random access memory units therein is controlled by a read-write command on line 221. Thus, when a write strobe is coupled to the read-write terminal of the function memory 183', input data is read into the five RAMS from the preload shift register 25 in locations which are dependent upon how many input pulses have been coupled to the BCD counter 213 via select gate 223 and the address location sequentially designated by the address pulses from the preload shift register 25 via the select gate 225.

From the aforementioned discussion of the start-stop program memory circuitry, it can be seen that the sequence of operation of the machine being controlled when being started or shut down can be selectively designated by appropriately entering commands into the preload shift register 25 from the central console. The starting and stopping commands can be quite complex, requiring a number of discrete steps wherein a number of machine components are actuated during each machine step. On the other hand, the starting and stopping process can be quite simple requiring only one machine step during which each of the components of the machine is either shut down or started up. In such a case, only one random access memory could be required in each of the function memories 183 and 183' and only one storage address would be stored in the address memory units 180 and 180'.

The control select gate 201 selectively controls when data is to be read into or out of the random access memory units in function memories 183 and 183'. In addtion, the control select gate controls the timing of when the RAM select gates 209 and 223 are to be enabled so that another RAM can be addressed. Finally, the control select gate enables select gates 197 and 225 to couple the address output of memory address counter 77 or the address output of the preload shift register to the RAM for addressing the storage elements in each RAM.

After the operation of a start and stop process, the specific instructions for starting and stopping the machine can be observed via gate 231. Thus by providing a control pulse output of control select gating circuit 201, gate 231 is enabled. With gate 231 enabled, inhibit and enable commands from the respective random access memory units in the function memories 183 and 183' are coupled in a serial train to the data accumulator shift register 39 illustrated in FIG. 2. The data accumulator shift register 39 couples the enable and inhibit commands to the central console where the commands are observed on a light emitting diode display.

From the foregoing it can be seen that applicants have provided a simplified, yet flexible, automatic control system which not only provides control of the operation of a variety of different machines but also provides for the control of a plurality of machines which are interdependent timewise with respect to one another and wherein a predetermined starting and stopping procedure must be followed in order to safely and efficiently start and stop the operation of the machine. While the aforementioned automatic programmable controller has been described in connection with the preferred embodiment, it should be understood that there are other embodiments which fall within the spirit and scope of the present invention as defined by the following claims.

Claims

1. A programmable automatic controller for controlling at least one machine, said at least one machine including a plurality of cyclically movable components which are actuated in a timed relationship with respect to one another, said movable components each being actuated at respective relative times in each of a plurality of machine cycles, and said at least one machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said at least one machine, said controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism with the movement of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said readout means for comparing the digital signal corresponding to the time elapsed in each cycle with the relative component actuating times stored in said storage means, said comparator providing an actuating signal when a favorable comparison results, and

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose component actuating time compared with the cycle time elapsed.

2. The programmable automatic controller of claim 1 further comprising means for initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequences being preselected to inhibit or enable machine components in a desired sequence.

3. The programmable automatic controller of claim 2 further comprising means for controlling a plurality of machines wherein each of said machines operates in a preselected interdependent timed relationship with respect to one another.

4. The programmable automatic controller of claim 2 wherein said storage means is a circulating storage comprising a sequential access memory means, a set-reset gating means for storing the output of said sequential access memory and for writing into said sequential access memory the data stored in said gating means, and

wherein said timing means further comprises means responsive to said machine cycle position indicating means for generating cycle clock pulses in synchronism with the movement of said cycle position indicating means, and

an internal clock pulse generating means for stepping said circulating storage means through one cycle of operation each time a machine cycle clock pulse is generated.

5. The programmable automatic controller of claim 4 wherein said sequential access storage means includes a plurality of COS/MOS shift registers connected in parallel to provide a plural bit storage means, said internal clock pulses stepping the data stored therein into said set-reset gating means and then back into the shift registers.

6. The programmable automatic controller of claim 4 wherein said means for selectively varying the component actuating times comprises:

an up-down counter,

means for presetting said up-down counter to the cycle actuating time of the selected machine component,

means for energizing said up-down counter to selectively count up or down, and

means for reading the count of said up-down counter into said sequential storage means when the desired cycle time for component actuation is reached.

7. The programmable automatic controller of claim 6 wherein said means for selectively varying the component actuating times further comprises:

a machine cycle preset enable circuit, said circuit comprising means for detecting when the count of said up-down counter reaches 360 when counting up, means for detecting when the count of said up-down counter reaches 999 when counting down, means for coupling the count of 000 to the jam input of said up-down counter when counting up, means for coupling the count of 359 into the jam input of said up-down counter when counting down, and means responsive to said detecting means for presetting said up-down counter to the count of 0 when the counter reaches the count of 360 when counting up and for presetting the up-down counter to the count of 359 when the count of said up-down counter reaches 999 when counting down, said cycle preset gating circuit thereby forcing said up-down counter to count continuously through 360 counts when the up-down counter is energized to count.

8. The programmable automatic controller of claim 2 wherein said means for initiating a machine starting or stopping sequence comprises:

a first start-stop address memory for storing the addresses of each of the machine components to be enabled or inhibited during the starting or stopping sequence,

address means for comparing the address stored in said first start-stop address memory means with the address stored in said addressing means when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited,

means in response to a compare by said address comparing means for enabling a selected one of a plurality of random access memory units, and

means for reading out the machine actuating commands stored in said random access memory units in sequence, said commends controlling the operation

of said machine components. 9. The programmable automatic controller of claim 8 23 wherein said means for initiating a machine starting or stopping sequence further comprises

means for sequentially enabling said random access memory units and for sequentially stepping the addresses stored in said start-stop address

memory means as each compare is made by said address comparing means. 10. The programmable automatic controller of claim 9 wherein said

start-stop address memory means is a random access memory. 11. The programmable automatic controller of claim 9 further comprising means for initially writing into said sequential storage means and said addressing means the order in which the respective machine components are to be

enabled and inhibited. 12. The programmable automatic controller of claim 11 further comprising means for writing into said random access storage means and said start-stop address memory means the order in which the

machine is to be started up or down. 13. The programmable automatic controller of claim 12 further comprising means for storing the respective

times with which the machine components are enabled and inhibited. 14. In a programmable automatic controller for controlling at least one machine, said at least one machine including a plurality of cyclically movable components which are actuated in a timed relationship with respect to one another, said movable components each being actuated at respective relative times in each of a plurality of machine cycles, and said at least one machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said at least one machine, a method of controlling said machine comprising the steps of:

generating a digital signal in synchronism with the movement of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

selectively varying the stored actuating times of selected components while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated,

comparing the digital signal corresponding to the time elapsed in each cycle with the stored relative component actuating times,

generating an actuating signal when a favorable comparison results, and

providing in response to said actuating signal a component operating command to the component whose component actuating time compared with the

cycle time elapsed. 15. The method of claim 14 further comprising the step of initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequences being preselected to inhibit and enable machine components in a desired

sequence. 16. The method of claim 15 further comprising the step of controlling a plurality of machines wherein each of said machines operates in a preselected interdependent timed relationship with respect to one

another. 17. The method of claim 14 wherein said selectively varying the component actuating times step comprises the steps of:

presetting an up-down counter to the cycle actuating time of the selected machine component,

energizing said up-down counter to selectively count up or down, and

reading the count of said up-down counter into said sequence storage means

when the desired cycle time for component actuation is reached. 18. The method of claim 17 wherein said selectively varying the component actuating times step further comprises the steps of:

detecting when the count of said up-down counter reaches 360 when counting up,

detecting when the count of said up-down counter reaches 999 when counting down,

coupling the count of 000 to the jam input of said up-down counter when counting up,

coupling the count of 359 into the jam input of said up-down counter when counting down,

presetting said up-down counter to the count of 0 when the counter reaches the count of 360 when counting up, and

presetting the up-down counter to the count of 359 when the count of said up-down counter reaches 999 when counting down.

19. The method of claim 18 wherein said step for initiating a machine starting or stopping sequence comprises the steps of:

storing the addresses of each of the machine components to be enabled during the starting or stopping sequence,

comparing the address stored with the address in an addressing means when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited,

enabling a selected one of a plurality of random access memory units when a compare is made, and

reading out the machine actuating comments stored in the random access memory units in sequence, the commands controlling the operation of the

machine component. 20. In a glassware forming machine having a plurality of sections, each of which includes a plurality of movable components which operate in timed relationship with respect to one another, means for feeding gobs of molten glass at a uniform rate from a predetermined location to each of said sections, said sections forming rigid glassware articles from the gobs taken from said feeding means, wherein said movable components are each actuated at respective relative times in each of a plurality of machine cycles, and said machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said machine, said a controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism with the movement of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said readout means for comparing the time elapsed in each cycle with the relative component actuating times stored in said storage means, said comparator providing an actuating signal when a favorable comparison results, and

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose

component actuating time compared with the cycle time elapsed. 21. In a glassware forming machine having a plurality of sections each of which includes a plurality of movable components which operate in timed relationship with respect to one another, means for feeding gobs of molten glass at a uniform rate from a predetermined location to each of said sections, said sections forming rigid glassware articles from the gobs taken from said feeding means, wherein said movable components are each actuated at respective relative times in each of a plurality of machine cycles, and a machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said machine, said a controller comprising:

timing means responsive to said machine cycle position indicating means for generating digital signals in synchronism with the movement of said cycle position indicating means, said digital signals providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said readout means for comparing the time elapsed in each cycle with the relative component actuating times stored in said storage means, said comparator providing an actuating signal when a favorable comparison results,

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose component actuating time compared with the cycle time elapsed, and

means for simultaneously controlling a plurality of machine sections wherein each of said machine sections operates in a preselected

interdependent timed relationship with respect to one another. 22. In a glassware forming machine having a plurality of sections each of which includes a plurality of movable components which operate in timed relationship with respect to one another, means for feeding gobs of molten glass at a uniform rate from a predetermined location to each of said sections, said sections forming rigid glassware articles from the gobs taken from said feeding means, wherein said movable components are each actuated at respective relative times in each of a plurality of machine cycles, and machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said machine, a programmable automatic controller method for controlling said machine comprising the steps of:

generating a digital signal in synchronism with the movement of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

selectively varying the stored actuating times of selected components while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated,

comparing the time elapsed in each cycle with the stored relative component actuating times,

generating an actuating signal when a favorable comparison results, and

generating in response to said actuating signal a component operating command to the component whose component actuating time compared with the cycle time elapsed.

23. A programmable automatic controller for controlling at least one machine, said at least one machine including a plurality of cyclically movable components which are actuated in a timed relationship with respect to one another, said movable components each being actuated at respective relative times in each of a plurality of machine cycles, and said at least one machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said at least one machine, said controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism with the movement of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said readout means for comparing the digital signal corresponding to the time elapsed in each cycle with the relative component actuating times stored in said storage means, said comparator providing an actuating signal when a favorable comparison results,

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose component actuating time compared with the cycle time elapsed, and

means for initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequences being preselected to inhibit or enable machine components in a desired sequence,

said means for initiating a machine starting or stopping sequence comprising:

a first start-stop address memory for storing the times when a start or stop sequence is to be initiated,

means for comparing the times stored in said first start-stop address memory with the address stored in said addressing means when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited,

means in response to a compare by said comparing means for enabling a selected one of a plurality of random access memory units, and

means for reading out the machine actuating commands stored in said random access memory units, said commands controlling the operation of said machine components.

24. A programmable automatic controller for controlling at least one machine, said at least one machine including a plurality of cyclically movable components which are actuated in a timed relationship with respect to one another, said movable components each being actuated at respective relative times in each of a plurality of machine cycles, and said at least one machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said at least one machine, said controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism with the movement of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said readout means for comparing the digital signal corresponding to the time elapsed in each cycle with a relative component actuating time stored in said storage means, said comparator providing an actuating signal when a favorable comparison results, and

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose component actuating time compared with the cycle time elapsed.

25. A programmable automatic controller for controlling at least one machine, said at least one machine including a plurality of cyclically movable components which are actuated in a timed relationship with respect to one another, said movable components each being actuated at respective relative times in each of a plurality of machine cycles, and said at least one machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said at least one machine, said controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism with the movement of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said readout means for comparing the digital signal corresponding to the time elapsed in each cycle with a relative component actuating time stored in said storage means, said comparator providing an actuating signal when a favorable comparison results,

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose component actuating time compared with the cycle time elapsed, and

means for initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequences being preselected to inhibit or enable machine components in a desired sequence,

said means for initiating a machine starting or stopping sequence comprising:

a first start-stop address memory for storing at least one time when a start-stop sequence is to be initiated,

means for comparing the at least one time stored in said first start-stop address memory with the address stored in said addressing means when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited,

means in response to a compare by said comparing means for enabling a selected one of a plurality of random access memory units, and

means for reading out the machine actuating commands stored in said random access memory units in sequence, said commands controlling the operation of said machine components.

26. In a glassware forming machine having a plurality of sections, each of which includes a plurality of movable components which operate in timed relationship with respect to one another, means for feeding gobs of molten glass at a uniform rate from a predetermined location to each of said sections, said sections forming rigid glassware articles from the gobs taken from said feeding means, wherein said movable components are each actuated at respective relative times in each of a plurality of machine cycles, and said machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said machine, a controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said read out means for comparing the times elapsed in each cycle with the relative component actuating times stored in said storage means,

said comparator providing an actuating signal when a favorable comparison results, and

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose component actuating time compared with the cycle time elapsed.

27. In a glassware forming machine having a plurality of sections, each of which includes a plurality of movable components which operate in timed relationship with respect to one another, means for feeding gobs of molten glass at a uniform rate from a predetermined location to each of said sections, said sections forming rigid glassware articles from the gobs taken from said feeding means, wherein said movable components are each actuated at respective relative times in each of a plurality of machine cycles, and said machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said machine, a controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said read out means for comparing the times elapsed in each cycle with the relative component actuating times stored in said storage means,

said comparator providing an actuating signal when a favorable comparison results,

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose component actuating time compared with the cycle time elapsed, and

means for initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequences being pre-selected to inhibit or enable machine components in a desired sequence,

said means for initiating a machine starting or stopping sequence including a first start-stop address memory for storing the times when a start or stop sequence is to be initiated,

means for comparing the time stored in said first start-stop address memory with the address stored in said addressing means when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited, and

means in response to a compare by said comparing means for generating machine actuating commands, said commands controlling the operation of

said machine components.

28. In a glassware forming machine having a plurality of sections, each of which includes a plurality of movable components which operate in timed relationship with respect to one another,

means for feeding gobs of molten glass at a uniform rate from a predetermined location to each of said sections, said sections forming rigid glassware articles from the gobs taken from said feeding means, wherein said movable components are each actuated at respective relative times and each have a plurality of machine cycles, and said machine including cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said machine,

a controller for controlling each of said sections of said machine comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism with the movement of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine;

a storage means for storing the relative times in a cycle of machine operation when each of a plurality of components is to be actuated;

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when said selected machine components are to be actuated, said selectively varying means including means for selecting a machine component the actuating time of which is to be varied, means for generating a signal corresponding to the new actuating time of said selected component, and means for reading said generated signal into said storage means;

means for cyclically reading out the contents of said storage means;

comparator means responsive to said timing means and said read out means for comparing the digital signal corresponding to the times elapsed in each cycle with the relative component actuating times stored in said storage means, said comparator providing an actuating signal when a favorable comparison results;

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose component actuating time compared with the cycle time elapsed; and

means for initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequences being pre-selected to inhibit or enable machine components in a desired

sequence.

29. The method of claim 18 wherein said step for initiating a machine starting or stopping sequence comprises the steps of:

storing at least one time when a start or stop sequence is to be initiated,

generating a machine component address for the component whose actuating time compares with the cycle time elapsed,

comparing said at least one stored start-stop sequence initiating time with the generated address when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited,

enabling a selected one of a plurality of random access memory units when a compare is made, and

reading out the machine starting commands stored in said random access memory units, said command controlling the operation of said machine components.

30. The method of claim 22 further comprising the steps of:

initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequences being preselected to inhibit and enable machine components in a desired sequence, said machine starting or stopping sequence step comprising the steps of:

storing at least one time when a start or stop sequence is to be initiated,

generating a machine component address for the component whose actuating time compares with the cycle time elapsed,

comparing said at least one stored start-stop sequence initiating time with the generated address when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited,

enabling at least one memory unit when a compare is made, and

reading out the machine actuating commands stored in said at least one memory unit, said commands controlling the operation of said machine

components.

31. The method of claim 22 further comprising the steps of:

initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequences being preselected to inhibit and enable machine components in a desired sequence, said machine starting or stopping sequence step comprising the steps of:

storing at least one time when a start or stop sequence is to be initiated,

generating a machine component address for the component whose actuating time compares with the cycle time elapsed,

comparing said at least one stored start-stop sequence initiating time with the generated address when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited,

enabling a selected one of a plurality of memory units when a compare is made, and

reading out the machine actuating commands stored in said selected memory units, said commands controlling the operation of said machine components.

32. In a glassware forming machine having a plurality of sections, each of which includes a plurality of movable components which operate in timed relationship with respect to one another, means for feeding gobs of molten glass at a uniform rate from a predetermined location to each of said sections, said sections forming rigid glassware articles from the gobs taken from said feeding means, wherein said movable components are each actuated at respective relative times in each of a plurality of machine cycles, and said machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said machine, a controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism of said cycle position indicating means, said digital signal providing an instantaneous indication of the time lapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when selected machine components are to be actuated,

means for cylically reading out the contents of said storage means,

comparator means responsive to said timing means and said read out means for comparing the times elapsed in each cycle with the relative component actuating times stored in said storage means,

said comparator providing an actuating signal when a favorable comparison results,

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose actuating time compared with the cycle time elapsed, and

means for initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequence being pre-selected to inhibit or enable machine components in a desired sequence,

said means for initiating a machine starting or stopping sequence including a first start-stop address memory for storing at least one time when a start or stop sequence is to be initiated,

means for comparing said at least one time stored in said first start-stop address memory with the address stored in said addressing means when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited, and

means in response to a compare by said comparing means for generating machine actuating commands, said commands controlling the operation of

said machine components.

33. In a glassware forming machine having a plurality of sections, each of which includes a plurality of movable components which operate in timed relationship with respect to one another, means for feeding gobs of molten glass at a uniform rate from a predetermined location to each of said sections, said sections forming rigid glassware articles from the gobs taken from said feeding means, wherein said movable components are each actuated at respective relative times in each of a plurality of machine cycles, and said machine including machine cycle position indicating means for cyclically moving in synchronism with the cyclic operation of said machine, a controller comprising:

timing means responsive to said machine cycle position indicating means for generating a digital signal in synchronism of said cycle position indicating means, said digital signal providing an instantaneous indication of the time elapsed in each cycle of operation of said machine,

a storage means for storing the sequential relative times in a cycle of machine operation when each of the plurality of components is to be actuated,

means coupled to said storage means for selectively varying the actuating times of selected components stored in said storage means while said machine is operating to thereby change the relative times in each machine cycle when selected machine components are to be actuated,

means for cyclically reading out the contents of said storage means,

comparator means responsive to said timing means and said read out means for comparing the times elapsed in each cycle with the relative component actuating times stored in said storage means,

said comparator providing an actuating signal when a favorable comparison results,

addressing means receiving said actuating signal from said comparator means for providing a component operating command to the component whose actuating time compared with the cycle time elapsed, and

means for initiating a machine starting or stopping sequence at any time during a machine cycle, said machine starting and stopping sequence being pre-selected to inhibit or enable machine components in a desired sequence,

said means for initiating a machine starting or stopping sequence including a first start-stop address memory for storing at least one time when a start or stop sequence is to be initiated,

means for comparing said at least one time stored in said first start-stop address memory with the address stored in said addressing means when the cycle time elapsed corresponds to the time a component is to be enabled or inhibited,

means for enabling at least one memory unit when a compare is made, and

means for reading out the machine actuating commands stored in said at least one memory unit, said commands controlling the operation of said machine components.