A plurality of resistance elements arranged in an n-row by n-column matrix are of substantially equal lengths and widths. The sides of the resistance elements which are in common rows and columns are colinear and first and second electrodes are provided at substantially the same location on each resistance element. The electrodes of the resistance elements are connected in a manner such that a series connection is formed between resistance elements belonging to different adjacent columns in the matrix between two sets of n external terminals.
|
6. a A combination comprising a plurality of substantially rectangular resistance elements each having first and second electrodes, said resistance elements each having first, second, third, and fourth sides, said resistance elements being substantially equal in width and in length to each other, said resistance elements being arranged in an n-row by n-column matrix (where n stands for an integer larger than 1), said first and second electrodes of each of said resistance elements being respectively provided at or near said first and second sides thereof, said first sides of said resistance elements belonging to the same row being colinear with a straight line, said second sides of said resistance elements of the same row being colinear with a straight line, said third sides of said resistance elements belonging to the same column being colinear with a straight line, and said fourth sides of said resistance elements of the same column being colinear with a straight line, n numbers of first terminals respectively electrically connected with the fist electrodes of said resistance elements of the first row, n numbers of second terminals respectively electrically connected with the second electrodes of said resistance elements of the n-th row, and means for connecting the second electrodes of each of said resistance elements belonging to an adjacent row but belonging to a different column, thereby to form a series connection of n resistance elements belonging to different columns between each of said first terminals and each of said second terminals.
1. An integrated circuit device comprising a plurality of substantially rectangular resistance elements each having first and second electrodes, said resistance elements being substantially equal both in width and in length to each other, said resistance elements being arranged in an n-row by n-column matrix (where n stands for an integer larger than 1), said first and second electrodes of each of said resistance elements being respectively provided at the same positions in each of said resistance elements, the upper sides of all of said resistance elements belonging to the same row of said matrix being colinear with a straight line, the lower sides of all of said resistance elements of the same row being colinear with a straight line, the right sides of all of said resistance elements belonging to the same column being colinear with a straight line, and the left sides of all of said resistance elements of the same column being colinear with a straight line, n numbers of first terminals respectively electrically connected with the first electrodes of the resistance elements of the first row, n numbers of second terminals respectively electrically connected with the second electrodes of the resistance elements of the n-th row, and means for respectively connecting the second electrodes of each of said resistance elements belonging to each row to the first electrodes of each of said resistance elements belonging to an adjacent row but belonging to a different column, thereby to form a series connection of n resistance elements belonging to different columns between each of said first terminals and each of said second terminals.
5. A combination comprising four substantially rectangular resistance elements each having first and second electrodes, said resistance elements being substantially equal in width and in length to each other, said resistance elements being arranged in a 2-row by 2-column matrix, said first and second electrodes of each of said resistance elements being respectively provided at the same portions in each of said resistance elements, the upper sides of said resistance elements belonging to the same row being colinear with a straight line, the lower sides of said resistance elements of the same row being colinear with a straight line, the right sides of said resistance elements belonging to the same column being colinear with a straight line, and the left sides of said resistance elements of the same column being colinear with a straight line, and first, second, third, and fourth terminals, said first terminal being connected to said first electrode of said resistance element of the first row and the first column, said second terminal being connected to said first electrode of said resistance element of the first row and the second column, said third terminal being connected to said second electrode of said resistance element of the second row and the first column, and said fourth terminal being connected to said second electrode of said resistance element of the second row and the second column, said second electrode of said resistance element of the first row and the first column being connected to said first electrode of said resistance element of the second row and the second column, and said second electrode of said resistance element of the first row and the second column being connected to said first electrode of said resistance element of the second row and the first column.
2. An integrated circuit device of
3. An integrated circuit device of
4. An integrated circuit device of
|
|||||||||||||||||
The present invention relates generally to resistors in an integrated circuit device, and more particularly to pairs of such resistors.
Recently integrated circuits have become larger in size and have necessitated sophisticated geometric alignment and characteristic matching in the fabrication of constituent elements such as, for example, a pair of resistors on a substrate. In a practical fabrication process, it is important to establish matching of the relative accuracy among resistance elements as well as thermal matching of those elements. Resistance elements that are thoroughly controlled with respect to such matching and alignment are used, for example, to constitute a resistor ladder network in a digital-to-analog converter or to set the gain of an operational amplifier.
Although it has been essential to achieve high relative accuracy in the fabrication of pairs of resistors on a substrate, the prior art approach has failed to realize substantial relative accuracy because deviation among resistance values has inevitably resulted because of such factors as misalignment in the cutting of the photomask art work, the aberration of lenses used in forming a set of reticles, difference in photomask alignment, and misalignment in the diffusion or vapor deposition process. Misalignment in the cutting of the photomask art work seriously and adversely affects the relative accuraccy with respect to resistance because a photomask is used when forming the diffusion region or deposition layer upon which the resistance values of the resistors fabricated depends.
Therefore, it is an object of the invention to provide pairs of resistors in an integrated circuit device having high relative accuracy with respect to resistance.
An integrated circuit device according to the present invention comprises nxn numbers of substantially rectangular resistance elements having first and second electrodes, the resistance elements being equal both in width and in length. The resistance elements are arranged in an n-row by n-column matrix (where n stands for an integer larger than 1), and the first and second electrodes of each resistance element are respectively provided at the same portions in each resistance element. The upper sides of all the resistance elements which belong to the same row, the lower sides of all the resistance elements of the same row, the right sides of all the resistance elements belonging to the same column and the left sides of all the resistance elements of the same column are each colinear. A number n of first terminals are each electrically connected with the first electrode of the resistance element of the first row, and a number n of second terminals are each electrically connected with the second electrode of the resistance element of the n-th row. The second electrode of each one resistance element belonging to each row is connected to the first electrode of each one resistance element belonging to an adjacent row but belonging to a different column, thereby to form a series connection of n resistance elements belonging to different columns between each one of the first terminals and each one of the second terminals.
The other objects, features and advantages of the invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings wherein:
FIGS. 1 and 2 are plan views showing a pair of resistors fabricated according to a prior art method;
FIG. 3 is a plan view showing an arrangement of resistors according to one embodiment of the invention;
FIG. FIG. 4F. After the photoresist 70 is thoroughly removed, an impurity is diffused thereinto and thereby a resistance layer 71 is formed as shown in FIG. 4(G). This resistance layer may be formed by ion implanation instead of impurity diffusion. In a known manner, aluminum electrodes are bonded respectively on the resistance element at both sides of the resistance layer and are connected by wirings as shown in FIG. 3, whereby a pair of resistors are fabricated with high relative accuracy.
Thus, all resistance elements are formed by selectively diffusing impurities into the same semiconductor substrate. When they are formed together with other active elements or passive elements in the same semiconductor substrate, all of these resistance elements are fabricated in the same region and are isolated from the other elements by a P-N junction in the substrate. Each of the resistance elements may be also formed in different regions and isolated from each other by a P-N junction in the substrate.
Moreover, these resistance elements may be formed of a thin film of resistive layer. A resistive film is deposited upon the entire surface of the same substrate, such as glass and ceramic, by sputtering or evaporation techniques. The film is selectively etched by utilizing the mask according to this invention in order to form resistance elements.
Another embodiment of the invention is schematically illustrated in FIG. 5. The aim of this embodiment is to achieve high relative accuracy in the fabrication of n pairs of resistors consisting of nxn numbers of resistance elements (where n ≧ 3). In FIG. 5, nxn numbers of resistance elements r 11, r12, . . . rn·n- 1, rn·n of rectangular shape with widths and lengths equal to each other are disposed on a substrate in an n-row by n-column matrix. The mask cutting on the photomask art work used in the fabrication process is carried out in such manner that, as described by referring to FIG. 4, the straight line colinear with the sides of the resistance elements in the X-axis on the same coordinate defines the coordinate of the X-axis scale, and the straight line colinear with the sides of the resistance elements in the Y-axis on the same coordinate defines the coordinate of the Y-axis scale.
The mask obtained from the photomask art work formed in the above manner is used to fabricate n×n numbers of resistance elements by ion implantation, impurity diffusion, vapor deposition, or other suitable techniques. These resistance elements are connected as shown in FIG. 5 to form n pairs of resistors r1, r2, . . . rn. More specifically, each of n numbers of terminals T1·1, T1·2, T1·3, . . . T1·n is respectively electrically connected with the first electrode of the resistance element of the first row, each n numbers of terminals T2·1, T2·2, T2·3, . . . T2·n is respectively electrically connected with the second electrode of the resistance element of the n-th row, and the second electrode of each one resistance element belonging to each row is respectively electrically connected to the first electrode of each resistance element belonging to the adjacent row but belonging to a different column thereby to form a series connection of n numbers of resistance elements belonging to different columns between each one of terminals T1·1, T1·2, T1·3, . . . T1·n and each one of terminals T2·1, T2·2, T2·3, . . . T2·n.
As shown in FIGS. 3 and 5, a pair of electrodes of each resistance element are formed at the same locations in each resistance element to provide substantially the same resistance value therebetween. Although electrodes are shown as points in these embodiments, they may have a striplike shape with a length near or equal to the width of the resistance element. Electrodes may be formed at or near the opposite side of the resistance element or at any locations in the resistance element, provided that their locations in the resistance element are the same.
According to the invention, the deviation in the mask cutting process is ideally compensated to make it possible to realize the highest relative accuracy in the fabrication of pairs of resistors on a substrate. At the same time, the deviation of resistance values ascribable to a temperature gradient on the semiconductor substrate is minimized.
In the above embodiment, n×n numbers of resistance elements are disposed in an n-row and n-column matrix. A plurality of such matrices may be disposed side by side or in cascade to form n pairs of resistors. In such structure, the deviations among values of each of n pairs of resistors are the sums of deviations among values of each of n pairs of resistors in each matrix, with the result that the relative accuracy is accordingly reduced as a whole.
While a few preferred embodiments of the invention have been described in detail, it is to be understood that this description is made only by way of example and not as a limitation on the scope of the invention.
| TABLE 1 |
| ______________________________________ |
| Example Example Example |
| in prior in prior in invention |
| art (FIG. 1) |
| art (FIG. 2) |
| (FIG. 3) |
| ______________________________________ |
| ΔR (α1 + β2)/2 |
| β2 /2 |
| α3 · β3 |
| /4 |
| ΔR max. |
| when 1% 0.5% 0.0025% |
| αβ ≦ 1% |
| ______________________________________ |
Hareyama, Kyuichi, Nakazawa, Shuzi
| Patent | Priority | Assignee | Title |
| 5293148, | Jul 13 1992 | Honeywell Inc. | High resolution resistor ladder network with reduced number of resistor elements |
| Patent | Priority | Assignee | Title |
| 3419767, | |||
| 3458847, | |||
| 3718780, | |||
| 3849757, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Oct 04 1976 | Nippon Electric Company, Limited | (assignment on the face of the patent) | / |
| Date | Maintenance Fee Events |
| Date | Maintenance Schedule |
| Jun 20 1981 | 4 years fee payment window open |
| Dec 20 1981 | 6 months grace period start (w surcharge) |
| Jun 20 1982 | patent expiry (for year 4) |
| Jun 20 1984 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Jun 20 1985 | 8 years fee payment window open |
| Dec 20 1985 | 6 months grace period start (w surcharge) |
| Jun 20 1986 | patent expiry (for year 8) |
| Jun 20 1988 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Jun 20 1989 | 12 years fee payment window open |
| Dec 20 1989 | 6 months grace period start (w surcharge) |
| Jun 20 1990 | patent expiry (for year 12) |
| Jun 20 1992 | 2 years to revive unintentionally abandoned end. (for year 12) |