A novel electronic control circuit which may be used in different types of electronic engine control systems is disclosed. Illustrative usage in various types of electronic spark timing control systems contemplates 4, 6, and 8 cylinder engine configurations as well as single or multiple pick-ups. The circuit is intended for fabrication as an integrated circuit device to provide a low-cost unit which is advantageous in mass production usage.
|
1. In an internal combustion engine, an electronic engine timing control circuit for providing control of an engine function comprising:
an output stage which is switched from one state to another state for producing an output signal; an output terminal connected with said output stage at which said output signal is given; a first input terminal receiving a variable frequency trigger signal representative of engine speed; a second input terminal receiving a variable frequency trigger signal representative of engine speed; a third input terminal receiving a desired timing signal derived from at least one parameter useful in controlling said engine function and representing desired timing of said output signal; and circuit means coupling said three input terminals and said output stage such that the trigger signal at said first input terminal always causes said output stage to produce said output signal so long as said output stage is in its one state at the time that the effect of the trigger signal received at said first input terminal is felt by said output stage, and when the trigger signal at said second input terminal has a frequency greater than a selected frequency, the desired timing signal controls, at least in part, the time at which said output stage produces said output signal; said circuit means comprising a frequency sensitive switch circuit having an input coupled with said second input terminal to receive the variable frequency trigger signal which is received at said second input terminal, said frequency sensitive switch circuit comprising means providing at an output thereof a logic signal having a first logic level when the frequency of the trigger signal received at said second input terminal is below said selected frequency and a second logic level when the frequency of the last-mentioned signal exceeds said selected frequency; said circuit means further comprising an OR logic gate having a pair of inputs and an output, means coupling said first input terminal with one input of said OR logic gate to always couple the variable frequency trigger signal received at said first input terminal to said one input of said OR logic gate regardless of the level of the logic signal of said frequency sensitive switch circuit, and means coupling the output of said frequency sensitive switch circuit and said third input terminal with the other input of said OR logic gate such that said desired timing signal is coupled to said other input of said OR logic gate only when the logic signal of said frequency sensitive switch circuit is at its second logic level; and utilization means coupled to said output terminal for providing control of said engine function by said output signal.
2. An electronic engine timing control circuit as claimed in
3. An electronic engine timing control circuit as claimed in
4. An electronic engine timing control circuit as claimed in
5. An electronic engine timing control circuit as claimed in
6. An electronic engine timing control circuit as claimed in
7. An electronic engine timing control circuit as claimed in
8. An electronic engine timing control circuit as claimed in
9. An electronic engine timing control circuit as claimed in
said frequency sensitive switch circuit comprising means providing at the output thereof a logic signal having a first logic level when the frequency of said second-mentioned variable frequency trigger signal is below said selected frequency and a second logic level when the frequency of said second-mentioned trigger signal exceeds said selected frequency; said circuit means including logic circuit means having three inputs and an output, means connecting the first of said three inputs to the output of said frequency sensitive switch circuit, means connecting the second of said three inputs to said first input terminal, means connecting the third of said three inputs to said third input terminal, and means connecting the output of said logic circuit means to said output stage; said logic circuit means comprising means for enabling said desired timing signal to control, at least in part, the time at which said output stage produces said output signal when the logic signal at the output of said frequency sensitive switch circuit is at its second logic level, means for preventing said desired timing signal from controlling the time at which said output stage produces said output signal when the logic signal at the output of said frequency sensitive switch circuit is at its first logic level, said logic circuit means comprising means for permitting each occurrence of said first-mentioned trigger signal to always cause said output stage to produce said output signal so long as said output stage is in its one state at the time that the effect of that trigger signal's occurrence has been transmitted through said logic means to said output
stage. 10. An In an internal combustion engine, an electronic engine timing control circuit as claimed in claim 9 for providing control of an engine function comprising: an output stage which is switched from one state to another state for producing an output signal; an output terminal connected with said output stage at which said output signal is given; a first input terminal receiving a variable frequency trigger signal representative of engine speed; a second input terminal receiving a variable frequency trigger signal representative of engine speed; a third input terminal receiving a desired timing signal derived from at least one parameter useful in controlling said engine function and representing desired timing of said output signal; and circuit means coupling said three input terminals and said output stage such that the trigger signal at said first input terminal always causes said output stage to produce said output signal so long as said output stage is in its one state at the time that the effect of the trigger signal received at said first input terminal is felt by said output stage, and when the trigger signal at said second input terminal has a frequency greater than a selected frequency, the desired timing signal controls, at least in part, the time at which said output stage produces said output signal; and utilization means coupled to said output terminal for providing control of said engine function by said output signal; wherein said circuit means comprises a frequency sensitive switch circuit having an input coupled to said second input terminal and having an output; said frequency sensitive switch circuit comprising means providing at the output thereof a logic signal having a first logic level when the frequency of said second-mentioned variable frequency trigger signal is below said selected frequency and a second logic level when the frequency of said second-mentioned trigger signal exceeds said selected frequency; said circuit means including logic circuit means having three inputs and an output, means connecting the first of said three inputs of said logic circuit means to the output of said frequency sensitive switch circuit, means connecting the second of said three inputs of said logic circuit means to said first input terminal, means connecting the third of said three inputs to said third input terminal, and means connecting the output of said logic circuit means to said output stage; said logic circuit means comprising means for enabling said desired timing signal to control, at least in part, the time at which said output stage produces said output signal when the logic signal at the output of said frequency sensitive switch circuit is at its second logic level, means for preventing said desired timing signal from controlling the time at which said output stage produces said output signal when the logic signal at the output of said frequency sensitive switch circuit is at its first logic level, said logic circuit means comprising means for permitting each occurrence of said first-mentioned trigger signal to always cause said output stage to produce said output signal so long as said output stage is in its one state at the time that the effect of that trigger signal's occurrence has been transmitted through said logic circuit means to said output stage; and wherein said logic circuit means comprises a first logic gate having a pair of inputs one of which corresponds to the first one of said three inputs of said logic circuit means and the other of which corresponds to the third of said three inputs of said logic circuit means, said first logic gate also having an output, said logic circuit means also comprising a second logic gate having a pair of inputs one of which corresponds to the second of said three inputs of said logic circuit means, said second logic gate also having an output, means connecting the other input of said second logic gate to the output of said first logic gate, the output of said second logic gate corresponding to the output of said logic circuit means. 11. An electronic engine timing control circuit as claimed in claim 10 wherein said first logic gate comprises an AND logic gate and said second logic gate comprises an OR logic gate having an inverting input terminal as said one input thereof which corresponds to the second of said three inputs of said logic circuit means. 12. An electronic engine timing control circuit as claimed in claim 9 1 wherein said frequency sensitive switch circuit comprises means endowing same with hysteresis in its switching characteristic between said first and second logic levels as a function of the frequency of said second-mentioned variable frequency trigger signal. 3. An electronic engine timing control circuit as claimed in claim 1 wherein said circuit means comprises means for generating a reference sawtooth waveform comprising a ramp generator having an input connected to said second input terminal and having an output at which said reference sawtooth waveform is given, said ramp generator being reset by said second-mentioned variable frequency trigger signal whereby said sawtooth waveform is generated; a comparator circuit having a pair of inputs and an output, means connecting the output of said ramp generator with one of said comparator circuit inputs, means coupling the other comparator circuit input to said third input terminal, said comparator circuit comparing said reference sawtooth waveform and said desired timing signal to provide a comparator output signal at the comparator circuit output each time that a predetermined relationship between said sawtooth waveform and said desired timing signal is attained; and means coupling the output of said comparator circuit, said first and second input terminals, and said output stage such that each occurrence of the trigger signal at said first input terminal always causes said output stage to produce its output signal so long as said output stage is in its one state at the time that the effect of that trigger signal's occurrence is felt by said output stage, and when the frequency of the trigger signal received at said second input terminal exceeds said selected frequency, the comparator output signal causes said output stage to produce its output signal so long as said output stage is in its one state at the time that the effect of the comparator output signal is felt by said output stage with said other input of said OR logic gate comprising an AND logic gate having a pair of inputs and an output, one input of said AND logic gate being coupled with the output of said comparator circuit, the other input of said AND logic gate being coupled with the output of said frequency sensitive switch circuit, and the output of said AND logic gate being coupled with said other input of said OR logic gate. . An electronic engine timing control circuit as claimed in claim 1 wherein the variable frequency trigger signals received at said first and second input terminals are derived from a conmmon common pick-up providing a rectangular waveform at a frequency representative of engine speed, said rectangular waveform being applied directly to one of said first and second input terminals, said rectangular waveform being coupled through a capacitor to the other of said first and second input terminals. 15. An electronic engine timing control circuit as claimed in claim 1 wherein the variable frequency trigger signals received at said first and second input terminals are derived from separate pick-ups which provide separate square wave signals which are displaced in phase relative to each other and wherein one of said square wave signals is applied directly to one of said first and second input terminals and the other of said square wave signals is coupled to the other of said first and second input terminals by a capacitor. 16. An In an internal combustion engine, an electronic engine timing control circuit as claimed in claim 1 for providing control of an engine function comprising: an output stage which is switched from one state to another state for producing an output signal; an output terminal connected with said output stage at which said output signal is given; a first input terminal receiving a variable frequency trigger signal representative of engine speed a second input terminal receiving a variable frequency trigger signal representative of engine speed; a third input terminal receiving a desired timing signal derived from at least one parameter useful in controlling said engine function and representing desired timing of said output signal; and circuit means coupling said three input terminals and said output stage such that the trigger signal at said first input terminal always causes said output stage to produce said output signal so long as said output stage is in its one state at the time that the effect of the trigger signal received at said first input terminal is felt by said output stage, and when the trigger signal at said second input terminal has a frequency greater than a selected frequency, the desired timing signal controls, at least in part, the time at which said output stage produces said output signal; and utilization means coupled to said output terminal for providing control of said engine function by said output signal; and wherein the variable frequency trigger signals received at said first and second input terminals are derived from a common pick-up providing a square wave signal whose frequency corresponds to engine speed and wherein pulses derived from both edges of said square wave signal are applied to said second input terminal and said square wave signal is applied directly to said first input terminal. 17. An electronic engine timing control circuit as claimed in claim 1 wherein said utilization means comprises the spark ignition system of the engine. |
|||||||||||||||||||||||
This invention pertains to a novel electronic circuit which is particularly useful in an electronic control system for an internal combustion engine.
The Chrysler Electronic Lean Burn system introduced during the 1976 model year on Chrysler Corporation vehicles is a milestone in the application of electronic technology to internal combustion engines used in automotive vehicles. The Chrysler Electronic Lean Burn system has been able to achieve compliance with Federal emission standards without the use of other emission control devices such as catalytic convertors, exhaust gas recirculation (EGR), air pumps, and like devices, and in so doing, has attained a modest but significant improvement in fuel economy.
The present invention is concerned in one respect with an improvement in the Chrysler Electronic Lean Burn system. One benefit of the invention is that the number of discrete electronic circuit components is dramatically reduced. This means that economy in assembly and parts costs is realized and reliability of the system is promoted. Moreover, the circuitry may be more compactly packaged which is important where the engine controls are mounted in the limited space of the engine compartment of a vehicle. With such economy the usage of the Chrysler Electronic Lean Burn system may be expanded to encompass many engine families and vehicle lines, and this means that the Electronic Lean Burn system can be made available to a much larger number of purchasers.
In another aspect, the invention relates to a unique electronic circuit which may be used in different types of electronic engine control systems. Because of this outstanding versatility and utility, a common device embodying this unique circuit can be employed in a number of different systems; this minimizes parts inventory and stocking complexities while serving to derive the maximum benefit of mass production techniques. The circuit is particularly well suited for fabrication as an integrated circuit device using existing integrated circuit manufacturing technologies. A circuit embodying principles of the invention is especially useful in an electronic spark timing system, and its versatility permits its use in either a single or dual pick-up system and in either four, six, or eight cylinder engines.
The foregoing features, advantages, and benefits of the invention, along with additional ones, will be seen in the ensuing description and claims which should be considered in conjunction with the accompanying drawings.
The drawings illustrate exemplary but preferred embodiments of electronic engine control systems embodying principles of the present invention and disclose the best mode presently contemplated in carrying out the invention.
FIG. 1 is an electronic schematic diagram partly in block diagram form of a circuit embodying principles of the present invention.
FIG. 2 is an electronic schematic diagram illustrating one of the blocks of FIG. 1 in somewhat greater detail.
FIG. 3 is an electronic schematic diagram illustrating another of the blocks of FIG. 1 in somewhat greater detail.
FIG. 4 is an electronic schematic diagram illustrating another of the blocks of FIG. 1 in somewhat greater detail.
FIG. 5 is an electronic schematic diagram of the circuit of FIG. 1 connected in a first type of electronic engine control system and includes a plurality of signal waveforms at selected points of the system which are useful in illustrating the system operation.
FIG. 6 is an electronic schematic diagram of the circuit of FIG. 1 connected in a second type of electronic engine control system and includes a plurality of signal waveforms at selected points of the system which are useful in explaining system operation.
FIG. 7 is an electronic schematic diagram illustrating the circuit of FIG. 1 connected in a third type of electronic engine control system and includes a plurality of signal waveforms taken at selected points of the system which are useful in explaining system operation.
FIG. 1 illustrates the novel electronic circuit 10 utilized in the preferred embodiments of the present invention. Circuit 10 is illustrated as preferably embodied in a single circuit device, for example an integrated circuit, and contains a plurality of sixteen terminals P1 through P16 inclusive via which it can be connected in an operative system. Circuit 10 comprises: an anti-dwell control monostable stage 12; a filter amplifier stage 14; a ramp generator stage 16; a frequency sensitive switch stage 18; a sum amplifier stage 20; a comparator stage 22; an "AND" logic gate 24; an "OR" logic gate 26 having one inverting input; and a pair of resistors 28 and 30. These components are arranged and organized as indicated schematically in FIG. 1. They are powered via an external power supply (not shown) which supplies a regulated DC potential across terminals P16 and P8. By way of illustration, in the example, the P8 terminal is intended to be connected to a ground potential while the P16 terminal is intended to be connected to a +Vcc potential relative to ground, (for example +10 VDC). The full potential and selected fractions thereof are supplied as required to selected points of the circuitry, and some of these are shown schematically in FIG. 1. For example, resistor 28 functions as a pull-up resistor for terminal P7 to the full +Vcc supply; 0.8 Vcc is supplied directly to the non-inverting input of sum stage 20; 0.4 Vcc is supplied directly to the non-inverting input of filter amplifier stage 14; and resistor 30 functions as a pull-up resistor for terminal P14 to the full +Vcc supply.
Tailoring of circuit 10 to the requirements of the different systems in which it may be used is accomplished in part by designing certain of the stages so that selected characteristics thereof may be established at least in part by external circuitry connected therewith. For anti-dwell control monostable stage 12, terminals P1 and P15 provide for connection of external circuitry (described in detail later) whereby the timing characteristic of this stage may be established. For filter amplifier stage 14, terminals P3 and P4 provide connection of external circuitry (to be described) to establish the frequency response filter characteristics of this stage. For ramp generator stage 16, terminals P5 and P6 provide for connection of external circuitry (to be described) to establish the ramp generating characteristics. For frequency sensitive switch stage 18, terminals P9 and P10 provide for connection of external circuitry (to be described) to establish the frequency sensing characteristics of this stage. Terminals P12 and P13 provide for connection of external circuitry (to be described) with sum stage 20 for establishing the gain of this stage.
In the preferred usage of circuit 10 in an electronic spark timing control circuit for an internal combustion engine, anti-dwell control monostable stage 12 provides at terminal P2 an output pulse which is used to fire the spark ignition system. The anti-dwell control monostable stage is triggered internally of circuit 10 via OR gate 26. Briefly, OR gate 26 is capable of triggering anti-dwell control monostable stage 12 by either a trigger signal received at terminal P14 or a Desired Spark Timing signal which is developed by sum amplifier stage 20 at its output (terminal P13) in a manner which will be explained in greater detail later. When the engine is running, the Desired Spark Timing signal will cause the anti-dwell control monostable stage to fire so that spark ignition advance is optimized according to engine operating conditions such as engine speed, engine load, etc. When the engine is being cranked during starting, the trigger signal at terminal P14 will cause the anti-dwell control monostable stage to fire the ignition at a fixed firing angle, for example, at or just slightly in advance of piston top dead center (possibly 10° BTDC). Frequency sensitive switch stage 18 distinguishes between engine cranking and engine running by sensing the frequency of an input trigger signal applied to terminal P7. The frequency sensitive switch stage supplies a logic "one", or "high", signal to input 24a of AND gate 24 when the frequency of the signal at terminal P7 exceeds a predetermined frequency which corresponds to an engine speed above engine cranking speed; this enables the Desired Spark Timing signal to fire the anti-dwell control monostable stage. When the frequency of the trigger signal at terminal P7 drops below this frequency to a speed below engine idle speed, then the frequency sensitive switch stage supplies a logic "zero", or "low", to input 24a of AND gate 24 thereby preventing the Desired Spark Timing signal from firing anti-dwell control monostable stage 12 so that the trigger signal at terminal P14 controls firing. It should be pointed out that in accordance with one feature of the present invention, the application of a trigger signal to terminal P14 will always cause anti-dwell control monostable stage 12 to switch from a stable to an unstable condition thereby firing the ignition system, provided that the monostable is in the stable condition when the effect of the trigger signal applied to terminal P14 is felt by the monostable. As will be more fully appreciated hereinafter in connection with the description of the later drawing figures, this feature enables anti-dwell control monostable stage 12 to fire the ignition system during running of the engine in the unusual event that the Desired Spark Timing signal is unable to fire the ignition in the customary manner.
It may be explained at this juncture that the trigger signals applied to terminals P7 and P14 are derived from pick-up circuitry associated with the engine for providing trigger signals at predetermined angular positions of the engine crankshaft, which as is understood in the art, correspond to given positions of the pistons in the respective cylinders. For example, in an eight cylinder engine, a trigger signal may be given at every 90° of engine crankshaft rotation. As will be seen in the detailed consideration of the ensuing drawing figures, the pick-up circuitry may be of various form including single and dual pick-up types and the engines with which these are used may be four, six, or eight cylinder engines. The trigger signal applied to terminal P14 is customarily referred to as the "start" trigger signal because it is used to fire the spark ignition at a fixed firing angle during cranking of the engine. The other trigger signal applied to terminal P7 is referred to customarily as the run "run" trigger signal. The run trigger signal is supplied internally of circuit 10 to both frequency sensitive switch stage 18, as explained above, and also to ramp generator stage 16. The ramp generator is thereby reset at predetermined engine crankshaft angles whereby a sawtooth waveform is produced at the ramp generator output and is supplied to the non-inverting input of comparator 22. The period of the sawtooth waveform supplied by ramp generator 16 to comparator 22 is proportional to the number of engine crankshaft degrees between times that the ramp generator is reset by the run trigger signal and hence corresponds to the number of crankshaft degrees between firings of the spark ignition system, assuming a constant spark advance. (For example, this would be 90° in an eight cylinder engine). For reasons which will be explained later, the sawtooth waveform has a constant peak-to-peak amplitude which is independent of the frequency at which the ramp generator is being reset and hence is independent of engine speed. Therefore, the magnitude of the sawtooth waveform at any instant of time is representative of a given angular position of the engine crankshaft. The Desired Spark Timing signal supplied by sum amplifier 20 to comparator 22 is an analog signal whose magnitude is representative of the engine crank angle at which spark ignition is desired. This magnitude will vary in accordance with the selected engine operating conditions which are being sensed to develop the desired amount of spark advance. Comparator 22 compares the Desired Spark Timing signal with the sawtooth signal from ramp generator 16. The comparator output signal switches from a logic zero to a logic one when the sawtooth and the Desired Spark Timing signals are equal. So long as AND gate 24 is enabled by a logic one signal at input 24a at the time that the output of comparator 22 switches from a logic zero to a logic one (and assuming that the input at terminal P14 is high), then the output of AND gate 24 switches from a logic zero to a logic one which is coupled through OR gate 26 to fire anti-dwell control monostable 12. Thus, it will be appreciated that during running, the time at which anti-dwell control monostable 12 fires the ignition system is established by the Desired Spark Timing signal. The development of the Desired Spark Timing signal can be in accordance with known techniques to produce the optimum firing angle in accordance with how the engine is being operated at any given instant of time. With this brief introductory description in mind, greater consideration can be focused upon the detail of the individual circuits.
FIG. 2 illustrates in greater detail a possible configuration for anti-dwell control monostable stage 12. Stage 12 may comprise a current mirror 32, a comparator 34, three transistors of NPN conductivity type 36, 38, and 40, a monostable 42, and a comparator 44 connected as illustrated. The emitter-collector circuit of transistor 36 connects in the input control branch of current mirror 32 and the emitter-collector of transistor 38 in the controlled output branch. The base of transistor 36 receives a signal Vspeed from the output of filter amplifier stage 14 and the non-inverting input of comparator 44 receives the trigger signal from the output of OR gate 26. In order to establish desired timing characteristics for the anti-dwell control monostable stage, external circuitry is connected with terminals P1 and P15 as illustrated. A resistor 46 is connected between ground and the emitter of transistor 36 at terminal P15. An RC series circuit comprising a resistor 48 and a capacitor 50 connects between +Vcc and ground with the junction thereof being connected to the collector of transistor 38 at terminal P1. The P2 terminal is at the open collector of transistor 40.
The circuit of FIG. 2 operates as follows. The signal Vspeed is a voltage whose magnitude is representative of the speed of the engine. (The manner in which the Vspeed signal is developed will be explained later.) If it is assumed that transistor 38 is not conducting and that capacitor 50 is fully charged to +Vcc volts, then current mirror 32 is out of range and no current flows in the output branch. When the output of OR gate 26 switches from a zero to a one, the output of comparator 44 goes high to fire monostable 42. In turn transistor 38 is switched into conduction for the duration of the monostable pulse from monostable 42. The duration of this pulse, and thus conduction of transistor 38, is just long enough to discharge capacitor 50. Accordingly, when this happens the voltage at the non-inverting input of comparator 34 falls to just above ground thereby causing the comparator output to go low and turn off transistor 40. When transistor 38 returns to its non-conducting condition, capacitor 50 immediately commences to recharge through resistor 48 from +Vcc and also from current mirror 32. The rate at which capacitor 50 charges is a function of the Vspeed signal. When the potential across the capacitor rises to a level sufficient to switch comparator 34 back to its original condition, transistor 40 once again turns on. The duration for which transistor 40 was cut off represents the anti-dwell time of the ignition. Transistor 40 remains conducting until the next time that OR gate 26 switches from a zero to a one. The duration for which transistor 40 is conducting represents the dwell time. The following equations describe the circuit operation. ##EQU1## Where Vc (t) is the voltage across capacitor 50; Ri is the resistance of resistor 48;
Vsp is the voltage Vspeed ;
Vbe is the base-emitter voltage of transistor 36;
Rd is the resistance of resistor 46; and
C is the capacitance of capacitor 50. Equation (2) holds for Vsp greater than Vbe. As can be seen from these equations, the dwell time is variable in accordance with the magnitude of the Vspeed signal. Accordingly, it will be appreciated that as the speed of the engine increases, the dwell time increases roughly in proportion thereto while there is a corresponding decrease in the anti-dwell time. The purpose of Ri is to set the anti-dwell time before there is any usable speed voltage, i.e. during cranking. Thus, for Vsp less than Vbe the equation reduces to:
T=Ri C 1n(2) Eq (3)
It will also be observed that by selection of the RC time constant of resistor 48 and capacitor 50 the dwell and anti-dwell characteristics may be tailored to the requirements of a given engine and its ignition system.
FIG. 3 illustrates one possible configuration for frequency sensitive switch stage 18. The circuit of FIG. 3 comprises a monostable 52, a delay circuit 54, a comparator 56, a data flip-flop 58, and a transistor 60 of NPN conductivity type. Also, operatively associated with the circuit are three external devices: a capacitor 62, and a pair of resistors 64, 66 which are connected as illustrated with terminals P9 and P10. Monostable 52 receives the pick-up trigger signal applied to terminal P7 and produces in response to the edge thereof an output pulse which is supplied to the C (clock) input of flip-flop 58. Delay circuit 54 delays slightly this pulse, and the slightly delayed pulse is applied to the base of transistor 60. The delayed pulse holds transistor 60 in conduction just long enough to discharge any charge on capacitor 62 so that a signal of just slightly above ground potential now exists at the inverting input of comparator 56. When the delayed pulse terminates and transistor 60 switches back to a non-conducting condition, capacitor 62 begins to charge through resistor 64 from +Vcc. The voltage at the Q output of flip-flop 58 is coupled through resistor 66 to capacitor 62 so that the rate of charge of capacitor 62 also depends upon the Q output voltage and the value of resistor 66. The following equation defines the time required to charge capacitor 62 to 0.5 Vcc which is the voltage required to switch the comparator output from a high to a low. ##EQU2## Where R=Rs Rh /Rs +Rh ; Rh is the resistance of resistor 66;
Vsw is the voltage at Q output of flip-flop 58;
Rs is the resistance of resistor 64; and
C1 is the capacitance of capacitor 62.
The circuit is designed so that flip-flop 58 always powers up to produce a logic one at terminal P9 when the ignition switch is actuated to energize the system for starting. Also the circuit is designed so that when the engine is being cranked, the low frequency of the trigger signal received at terminal P7 provides a sufficiently long duration between clockings of flip-flop 58 that capacitor 62 charges to beyond the 0.5 Vcc potential whereby the output signal at the Q output of flip-flop 58 remains high (e.g. near Vcc potential). Hence, the frequency sensitive switch provides a logic one at terminal P9 during cranking. When the engine begins to run under its own power and accelerate through a speed slightly above cranking speed, the corresponding increase in frequency of the trigger signal at terminal P7 reduces correspondingly the time interval between successive or of OR gate 26 is forced high during the alternate periods of the sawtooth waveform which are coincident with the P14 signal being high. With this arrangement it is impossible for comparator 22 to fire the anti-dwell control monostable stage during these alternate periods even though triggering of the monostable stage would otherwise occur because of the 90° sawtooth period. Therefore, when the engine is running, the Desired Spark Timing signal actually causes firing of the ignition system only on alternate periods of the sawtooth waveform wherein the P14 signal is concurrently low. When the engine is being cranked during starting, the P14 signal will trigger the anti-dwell control monostable stage at 180° intervals and because of the arrangement of circuit 10, firing by the Desired Spark Timing signal during cranking is precluded. Therefore it is desirable to phase the trigger signal such that the trailing edge of each negative-going pulse of the P14 signal, which causes these firings, is in a range somewhat before top dead center for example, at 10° BTDC.
The blanking feature: allows for better frequency response since twice as much information is supplied to the speed filter; limits advance range to 90° (it is not desirable to have more than 90° range anyway); and gives greater resolution since the ramp has twice as many volts per degree as it would have without blanking.
By providing terminals P13 and P12, as explained above, the value of resistor 76 may be selected to establish the gain of the sum amplifier stage. This calibrates the amount of spark advance for the various inputs from which the advance is derived. It is also possible to provide temperature compensation of the Desired Timing Signal by connecting a temperature responsive device such as a thermistor, with the sum amplifier stage. One way of doing this is by connecting a thermistor between terminals P12 and P13, preferably in series with a resistor to make the stage gain vs. temperature curve more linear. The thermistor is suitably disposed to monitor temperature and serves to attenuate the gain as temperature increases so as to alleviate possible detonation problems. When using this temperature compensation technique, a further advantage, useful for calibrating the temperature compensation characteristic, results from connecting the non-inverting input of sum amplifier 20 to the same potential as the peak of the sawtooth (i.e., 0.8 Vcc). By so connecting the non-inverting input, the potential at the inverting input is forced to essentially the same potential (i.e., 0.8 Vcc). Now if the Desired Spark Timing signal is adjusted so that ignition occurs at the peak of the sawtooth, the potential at the output of sum amplifier 20 is 0.8 Vcc. Resistor 86 may now be adjusted to set the basic timing without regard to actual temperature since there is no current flow through the thermistor. This simplifies the calibration procedure. There is also the advantage that the basic timing is independent of the ambient temperature.
In the foregoing description there have been disclosed a novel electronic circuit and systems containing said circuit which offer advantages not previously attainable in electronic engine controls. Reliability, versatility, and economy improvements are obtained which promote mass-production usage in commercial products to the benefit of the consumer and the public. This invention indeed marks a milepost in electronic engine controls.
| Patent | Priority | Assignee | Title |
| 4976247, | Apr 30 1986 | Robert Bosch GmbH | Ignition device for combustion engines |
| 6989694, | Feb 04 1999 | ST Wireless SA | Voltage ramp generator and current ramp generator including such a generator |
| Patent | Priority | Assignee | Title |
| 3756212, | |||
| 3874351, | |||
| 3916855, | |||
| 3923021, | |||
| 3923029, | |||
| 3978833, | Jun 13 1975 | Chrysler Corporation | Engine control circuit for providing a programmed control function |
| 3997801, | Mar 17 1975 | Chrysler Corporation | Transducer circuits for providing pulses whose widths are representative of mechanical input signals |
| 4138976, | Jun 19 1975 | Chrysler Corporation | Engine timing system with automatic selective utilization of first and second signals |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Apr 02 1979 | Chrysler Corporation | (assignment on the face of the patent) | / | |||
| Feb 09 1981 | Chrysler Corporation | FIDELITY UNION TRUST COMPANY, TRUSTEE | MORTGAGE SEE DOCUMENT FOR DETAILS | 003832 | /0358 | |
| Feb 17 1982 | FIDELITY UNION BANK | Chrysler Corporation | ASSIGNORS HEREBY REASSIGN, TRANSFER AND RELINQUISH THEIR ENTIRE INTEREST UNDER SAID INVENTIONS AND RELEASE THEIR SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 004063 | /0604 | |
| Feb 17 1982 | ARNEBECK, WILLIAM, INDIVIDUAL TRUSTEE | Chrysler Corporation | ASSIGNORS HEREBY REASSIGN, TRANSFER AND RELINQUISH THEIR ENTIRE INTEREST UNDER SAID INVENTIONS AND RELEASE THEIR SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 004063 | /0604 | |
| Sep 05 1984 | MANUFACTURERS NATIONAL BANK OF DETROIL CORPORATE TRUSTEE AND BLACK DONALD E , INDIVIDUAL TRUSTEE | Chrysler Corporation | PARTES REASSIGN, TRANSFER AND RELINQUISH THEIR ENTIRE INTEREST UNDER SAID PATENTS ALSO RELEASE THEIR SECURITY INTEREST SEE RECORD FOR DETAIL | 004355 | /0154 |
| Date | Maintenance Fee Events |
| Date | Maintenance Schedule |
| Sep 08 1984 | 4 years fee payment window open |
| Mar 08 1985 | 6 months grace period start (w surcharge) |
| Sep 08 1985 | patent expiry (for year 4) |
| Sep 08 1987 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Sep 08 1988 | 8 years fee payment window open |
| Mar 08 1989 | 6 months grace period start (w surcharge) |
| Sep 08 1989 | patent expiry (for year 8) |
| Sep 08 1991 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Sep 08 1992 | 12 years fee payment window open |
| Mar 08 1993 | 6 months grace period start (w surcharge) |
| Sep 08 1993 | patent expiry (for year 12) |
| Sep 08 1995 | 2 years to revive unintentionally abandoned end. (for year 12) |