DC Free encoding for data transmission system

Abstract

A method and apparatus provide for the elimination of any net dc component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed. The onset of a sequence of second bit states following a first bit state that might introduce a dc component into the transmitted signal with normal transmission is detected by producing a first indicating signal, and in response to the first indicating signal and the state of a current bit and the state of the next succeeding bit the transmission of signal transitions is modified to eliminate any dc component. Preferably, the end of a sequence of second bit states that would introduce a dc component is detected by producing a second indicating signal utilized to modify the signal transitions at the end of a troublesome sequence, as by suppressing the transition corresponding to the last second bit state in such a sequence.

Description

This invention relates to the transmission of data in binary form serially through an information channel. More particularly it relates to a method and system for transmitting signals that are self-clocking and still more particularly to such method and system for transmission through an information channel having no response at zero frequency. The invention relates to the encoding and decoding of particular binary codes. The invention finds particular application where the information channel comprises a magnetic tape recorder.

Data or information in binary form is comprised of data bits wherein the information in each bit is in the form of one or the other of two states. Such states are often referred to as logical 1 and logical 0. In operating with information in binary form it is necessary to recognize the respective logic states for each bit. Whether these bits are recorded on tape or are otherwise recorded or transmitted, each bit of information may be said to be maintained in a bit cell which represents an interval in time or space containing the responsive bit of information. The logic states may be recognized or referred to variously as "yes" or "no", "+" or "-", "up" or "down", and "true" or "not true", and the like. Where the information is recorded on a tape recorder, the states may be of opposite magnetic polarization. It is also common to have one state a reference level and the other state a different level, in which case indication of the second state may be provided by a recognizable signal while the first state is indicated by absence of such signal. There is positive logic and negative logic. Further it makes no difference for the purposes of this invention which of the two states is called 1 and which is called 0.

As noted, the present invention finds particular applicability to information channels such as magnetic recording channels which have no response at zero frequency; that is, they do not transmit at DC. In general it is desirable to record data bits as closely together as possible while producing errors so infrequently as to be tolerable. Various recording formats or binary data codes have been developed for recording binary data. Some codes desirably permit self-clocking; that is, the bit cell intervals may be identified in the recorded bit data without the need for separate timing pulses.

In information channels which do not transmit DC, binary wave forms suffer distortions of peak amplitude value and zero-crossing location which cannot be removed by means of linear response compensation networks unless the channel affords substantial response at frequencies at least as great as the bit rate. These distortions are commonly described as baseline wander and act to reduce the effective signal-to-noise ratio and thus degrade the reliability of detection of the recorded signals.

A common transmission format or data code is that utilized in the recording and reproducing system disclosed in Miller U.S. Pat. No. 3,108,261, issued Oct. 22, 1963 for Recording and/or Reproducing System. In the Miller code, logical 1's are represented by signal transitions at a particular location in the respective bit cells, specifically at mid-cell, and logical 0's are represented by signal transitions at a particular earlier location in the respective cells, specifically at the beginning or leading edge of each bit cell. The Miller format involves the suppression of any transition occurring at the beginning of one bit interval following an interval containing a transition at its center. The asymmetry of the waveform generated by these rules introduces DC into the information channel.

A code based upon the Miller code but with the DC component eliminated is described by A. M. Patel in "Zero-Modulation Encoding in Magnetic Recording", IBM J. Res. Develop., Vol. 19 No. 4, July, 1975. This format, commonly called ZM, is based upon the Miller format for most input sequences but sequences of the form 0111 - - - 110 having an even number of 1's are , (BI-L) , clock clocks the flip-flop 192. The Q outputs of the D flip-flops 190 and 192 are applied to a NOR gate 194 which produces on the path 44 a signal indicative of a back of synchronization when the count of the D flip-flops 190 and 192 reaches 3. The signal on the path 44 is applied to a pulse suppression circuit 196 in the clock output circuit 150. The circuit 196 comprises a pair of D flip-flop 198 and 200 and a NOR gate 202. The flip-flops 198 and 200 are clocked by the 2F clock pulses of waveform 9E to produce at the output of the NOR gate 202 a signal to the OR gate 158 to suppress the clock pulse to the D flip-flop 160, thus dropping one-half cycle from the output of the D flip-flop 160, placing the circuit in proper synchronization.

To assure proper synchronization it is desirable to start transmission with a lead-in series of pulses of characteristic transitions providing an easily recognizable signal if the system is out of synchronization. Such a series is 10101. This avoids losing data before the data themselves have provided a series of transitions that reveals the error in synchronization.

It may be noted that a similar synchronization circuit could be utilized with the decoder of FIG. 6.

While one specific encoding circuit has been shown and two different decoding circuits operating on the same code have been disclosed. It should be evident that other particular circuitry may be used for the same purposes. Further, other code formats may be used coming within the scope of the present invention. Broadly, the invention encompasses a method and system wherein a data stream in binary serial form is considered as the concatenation of a plurality of types of sequences of 1's, some of which may create a DC imbalance if the code format of Miller U.S. Pat. No. 3,103,261 were used. In accordance with the present invention, means are provided for indicating at the outset of any sequence of 1's whether or not the sequence is of the sort that could introduce DC imbalance. Means looking no more than one bit state ahead then notes the end of a particular sequence of 1's and indicates whether or not the particular sequence of 1's was of the sort that would introduce a DC component into the transmission signal with normal transmission. Means responsive to this last indication then provides remedial action at the end of the sequence appropriate for eliminating any DC component. Any modification of the signals is performed in a manner that may be recognized by corresponding decoding apparatus.

Claims

1. In a self-clocking transmission system for transmitting binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transitions transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, apparatus for modifying the transmitted signal to remove any net dc component, said apparatus comprising first indicating means responsive to bit states for producing at the onset of a sequence of second bit states following a first bit state a first indicating signal indicating any such sequence that might introduce a dc component into the transmitted signal with normal transmission, and means responsive to said first indicating signal, a current bit and but one next succeeding bit for modifying the transmission of signal transitions to eliminate any dc components component.

2. In a self-clocking transmission system for transmitting binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit-cell following a transition relatively late in the next preceding bit cell is suppressed, apparatus for modifying the transmitted signal to remove any net dc component, said apparatus comprising first indicating means responsive to bit states for producing at the onset of a sequence of second bit states following a first bit state a first indicating signal indicating any such sequence that might introduce a dc component into the transmitted signal with normal transmission, second indicating means responsive to said first signal and to but one bit next succeeding a current bit for producing a second indicating signal indicating the end of a sequence of second bit states that would introduce a dc component into the transmitted signal with normal transmission, and means responsive to said second indicating signal for modifying the transmission of signal transitions at the end of such a sequence to eliminate any dc component.

3. Apparatus in accordance with claim 2 wherein said means for modifying the transmission of signal transitions suppresses the transition corresponding to the last second bit state in such a sequence that would introduce a dc component into the transmitted signals with normal transmission.

4. Apparatus in accordance with claim 3 further including decoding means responsive to transmitted signal transitions for indicating the bit states of the binary data transmitted, said decoding means comprising synchronizing means responsive to transmitted signal transitions for providing timing signals for distinguishing relatively early transitions from relatively late transitions, detection means responsive to said transmitted signal transitions and said timing signals for indicating first bit states upon receipt of relatively early transitions and second bit states upon receipt of relatively late transitions, suppressed transition detection means responsive to said transmitted signal transitions and said timing signal for detecting the absence of a transition within 21/2 bit cells following a relatively late transition by producing a suppressed transition detection signal, and means responsive to said suppressed transition detection signal for indicating the bit following that corresponding to the transition preceding said 21/2 bit cells as in the second bit state, and means responsive to said timing signals for indicating any other bit as in the first bit state.

5. Apparatus in accordance with claim 2 wherein said first indicating means responds to first bit states following a suppressed second bit state transition to produce such a first indicating signal when the number of such first bit states following a suppressed second bit state transition is odd, said second indicating means being enabled by such a first indicating signal to respond to second bit states following an odd number of first bit states to produce such a second indicating signal when the number of second bit states at the end of the sequence of second bit states is even, and said means responsive to said second indicating signals is enabled by such a second indicating signal to suppress any signal transition in the transmitted signal corresponding to the last second bit state in a respective sequence of second bit states.

6. Apparatus in accordance with claim 2 further including decoding means responsive to transmitted signal transitions for indicating the bit state of the binary data transmitted, said decoding means comprising synchronizing means responsive to transmitted signal transitions for providing timing signals for distinguishing relatively early transitions from relatively late transitions, first detection means responsive to said transmitted signal transitions and said timing signals for indicating first bit states upon receipt of relatively early transitions and second bit states upon receipt of relatively late transitions, second detection means responsive to said transmitted signal transitions and said timing signals for detecting the modification of normal transmission by producing a modification signal and means responsive to said modification signal for reconstituting the original data, and means responsive to said timing signals for indicating any other bit as in the first bit state.

7. In a self-clocking transmission system for transmitting binary data sequentially in successive clock clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in respective bit cells, logical second bit states are normally transmitted at signal transitions relatively late in the respective bit cells, any transition corresponding to a first bit state following a second bit state is suppressed, and certain transitions corresponding to second bit states preceding the first bit states are suppressed, decoding apparatus responsive to transmited signal transitions for indicating the bit state of the binary data transmitted, said decoding apparatus comprising synchronizing means responsive to transmitted signal transitions for providing timing signals for distinguishing relatively early transitions from relatively late transitions, detection means responsive to said transmitted signal transitions and said timing signals for indicating first bit states upon receipt of relatively early transitions and second bit states upon receipt of relatively late transitions, suppressed transition detection means responsive to said transmitted signal transitions and said timing signals for detecting the absence of a transition within 21/2 bit cells following a relatively late transition by producing a suppressed transition detection signal and means responsive to said suppressed transition detection signal for indicating the bit following that corresponding to the transition preceding said 21/2 bit cells as in the second bit state, and means responsive to said timing signals for indicating any other bit as in the first bit state.

8. A self-clocking method for transmitting binary data sequentially in successive clock clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted by as signal transitions relatively early in respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, said method comprising detecting the onset of a sequence of second bit states following a first bit state that might introduce a dc component to the transmitted signal with normal transmission by producing a first indicating signal indicating any such sequence, and in response to said first indicating signal and the state of a current bit and the state of the next succeeding bit modifying the transmission of signal transitions to eliminate any dc component.

9. A self-clocking method for transmitting binary data sequentially in successive clock clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, said method comprising detecting the onset of a sequence of second bit states following a first bit state that might introduce a dc component into the transmitted signal with normal transmission by producing a first indicating signal indicating any such sequence, and in response to said first indicating signal and to the state of the next succeeding bit detecting the end of a sequence of second bit states that would introduce a dc component into the transmitted signal with normal transmission by producing a second indicating signal indicating any such sequence that would introduce a dc component, and in response to said second indicating signal modifying the transmission of signal transitions at the end of such a sequence to eliminate any dc component.

10. A method according to claim 9 wherein the transmission of signals signal transitions is modified by suppressing the transition corresponding to the last second bit state in such a sequence that would introduce a dc component in normal transmission.

11. A method in accordance with claim 10 wherein the transmitted signal is decoded by deriving a timing signal from the transmitted data signal transitions for distinguishing relatively early and relatively late transitions, indicating first bit states upon relatively early transitions and second bit states upon relatively late transitions, detecting a suppressed relatively late transition by the absence of a transition within 2 and a fraction bit cells subsequent to a relatively late transition, and indicating a second bit state upon the detection of a suppressed relatively late transition, and indicating a first bit state in the absence of a transition in any other respective bit cell.

12. A method in accordance with claim 9 wherein such a first in indicating signal is produced when the number of such first bit states following a suppressed second bit state transition is odd, such a second indicating signal is produced when the number of second bit states at the end of the sequence of second bit states is even, and the transmission of signal transitions is modified by suppressing any signal transition signal corresponding to the last second bit state in a respective sequence of second bit states when the first indicating signal indicates an odd number of first bit states and the second indicating signal indicates an even number of second bit states.

13. A method in accordance with claim 9 wherein the transmitted signal is decoded by deriving a timing signal from the transmitted data signal transitions for distinguishing relatively early and relatively late transitions, indicating first bit states upon relatively early transitions and second bit states upon relatively late transitions, detecting modification of normal transmission, and indicating a second bit state upon the detection of such modification, and indicating a first bit state in the absence of a transition in any other respective bit cell.

14. In a self-clocking method for transmitting binary data sequentially in successive clock clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in respective bit cells, logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells, any transitions corresponding to a first bit state following a second bit state is suppressed, and certain transitions corresponding to second bit states preceding first bit states are suppressed, a method of decoding the transmitted signal comprising deriving a timing signal from the transmitted data signal transitions for distinguishing relatively early and relatively late transitions, indicating first bit states upon relatively early transitions and second bit states upon relatively late transitions, detecting a suppressed relatively late transition by the absence of a transition within 2 and a fraction bit cells subsequent to a relatively late transition, and indicating a second bit state upon the detection of a suppressed relatively late transition, and indicating a first bit state in the absence of a transition in any other respective bit cell.