Row grabbing system

Abstract

A real time frame grabbing system for substantially instantaneously providing a continuous video display of a selectably predetermined video frame of information on a video display means from continuously transmittable video information which is transmitted as a plurality of pseudo video scan lines wherein the selected frame being grabbed is updateable on a displayable-row-by-displayable-row basis. Each of the pseudo video scan lines has a television scan line format and comprises a complete self-contained packet of digital information sufficient to provide an entire displayable row of video data characters, the pseudo video scan line having an associated transmission time equivalent to that of a television video scan line. The packet of digital information comprises at least address information for a displayable row and data information for the displayable characters in the row. Each of these pseudo video scan lines further comprises a horizontal sync signal at the beginning thereof and a start bit pulse between the horizontal sync signal and the packet of digital information. The start bit pulse provides a unique synchronizing pulse for each transmitted pseudo video scan line for enabling precise determination of a sampling time for the received distributed pseudo video scan line to enable accurate determination of the binary state of the bits comprising the digital information packet, with the receiver being responsive to the occurrence of the start bit for each distributed pseudo video scan line for providing a reset signal for resetting the signal processing means in response to detection of the start bit to provide enhanced noise immunity and accurate signal information. The pseudo video scan lines are both transmitted and received through a conventional television distribution system. If desired, a local micro-processor may be utilized to control the functions of the receiver terminal and may be used in conjunction with a printer interface to enable both continuous high speed video display and real time pick off for hard copy printing.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is an improvement on the row grabbing system described in our previous U.S. Pat. No. 3,889,054, issued June 10, 1975 and is related to the commonly assigned copending U.S. patent application of Robert H. Nagel, entitled "Information Retrievable System Having Selectable Purpose Variable Function Terminal", filed Sept. 10, 1975, and bearing U.S. Ser. No. 611,927, datenow U.S. Pat. No. 4,064,490, additional keys such as program may be provided when the system is utilized to retrieve programs or sets of instructions as opposed to or in addition to data. As shown and preferred in FIG. 26, if a group key is depressed and preceded by a number, terminal 8000 will be informed of the new group via the group address and page address line GAD/PAD and LEN lines, with the page number preferably reset to zero. If the group is not preceded by a number, preferably the only action taken would be to release directed messages by setting and clearing the KAC line and to erase the screen via a pulse on the ERA line, all functions which change the group/page accomplishing this such as call, back, up and group. The inputs from the terminal 8000 to the microprocessor 6000 are preferably the row enable line REN, the row address read line RAR, the row address write line REW, the special character line SCH, and the permission line PER. The output to the keyboard is preferably the clear or keyboard latch reset line 6007 which is pulsed when a key has been completely processed so that the key will then be reset to the idle state. The outputs to the terminal 8000 from the microprocessor 6000 preferably comprise the erase line which erases the video display 2013, the keyboard active line KAC which is set while a group/page number is being sent to the terminal 8000 so that the terminal 8000 will take no action on it until the number is completely received, the group address/page address line GAD/PAD which informs the terminal 8000 of a new page to grab, the latch enable line LEN and the row length line RWL. Suffice it to say that the microprocessor 6000 performs all data handling and execution of the permanently stored program in the read only memory 603 with the random access memory 605 preferably functioning to store data in order to accomplish the row grabbing function, the data being taken out of the random access memory 605 and provided to the input/output buffer 607 for subsequent display on the video display 2013.

Referring now to FIG. 24, the output of microprocessor 6000 preferably includes four general purpose address bits or lines 715 and five lines of enable pulses 717. Lines 717 specify which one of the plurality of latches 701, 703, 705, 707 and 709, collectively referred to by reference numeral 699, with latches 701, 703 and 705 being the page address latches, and latches 707 and 709 being the group address latches, the address bits 715 are designated for. By utilizing the four data lines 715 and five enable lines 717, up to 20 different bits of address, which is equivalent to 1,048,576 addresses, can be established. The page address output bits collectively referred to by reference numeral 504 and the group address output bits collectively referred to by reference numeral 502 are employed in the memory input control portion of the receiver 28 illustrated in FIG. 11 preferably in the same manner as described in our previous U.S. Pat. No. 3,889,054 with respect to the outputs of the keyboard counter 500 of the system described in U.S. Pat. No. 3,889,054 and will not be described in greater detail hereinafter since such description is specifically incorporated by reference herein.

Referring to the aforementioned exemplary program written in PPS-4 Assembler language, as was previously mentioned, a typical microprocessor 6000 arrangement which is controlled by the aforementioned program is illustrated in FIG. 28 with the various pin number designations utilized by Rockwell International for the read only memory, random access memory, CPU or microcomputer, and input/buffer chips 605, 603, 601, and 607a and 607b, respectively being utilized in FIG. 28 for clarity. Furthermore, and as shown and preferred in FIG. 26, if desired, the receiver terminal 28 may additionally have a computer/printer or cathode ray tube display interface for use with a CRT character generator so as to provide a "hard copy" printout of the information being displayed on video display 2013 as well as the video display thereof. However, this is optional to the improved video display terminal of the present invention and need not be included unless such "hard copy" printout is desired. In such an instance, a printer interface 8004 and conventional printer 8006 would be required and would preferably be controlled by the microprocessor 6000 in a manner to be described in greater detail hereinafter. It should be noted that if such printing function is not desired then the functions of the terminal 28 and microprocessor 6000 relating thereto may be omitted; however, for purposes of completeness the programmed terminal will be described, as illustrated in the aforementioned program, assuming such printer and printing function is included.

Referring once again to FIGS. 26 and 28 and the aforementioned program, in order to facilitate the understanding of the functioning of the illustrative conventional program in the system of the present invention, the following detailed description of the inputs from the keyboard 5000, the inputs from the printer interface 8004, the inputs from the terminal 8000, the outputs to the keyboard 5000, the outputs to the printer interface 8004, the outputs to the terminal 8000, the input/output buffer assignments, the random access memory or RAM allocations, the register allocations, and the read only memory or ROM may be provided by way of example below.

Inputs (from keyboard 5000)

PAC a. Keybard entry KEY 4 lines

Set when a key is pressed and latched. Reset to the idle state only when a pulse sent on KLR. Settings are as follows:

0-9: for numeral key. Consecutive numeral keys pressed will build a number (leading zeros automatically provided). Leading digits which cause the number to become too big for the function will be ignored - e.g., if 255 is the biggest number allowed for a group, and the number 256 is inserted, when the GROUP key is pressed, this will be truncated to 56.

A₁6 : for GROUP key. If this is preceded by a number, the terminal will be informed of the new group via GAD/PAD and LEN lines, with page number reset to zero. If not preceded by a number, the only action taken will be to release directed messages by setting and clearing KAC and to erase the screen via a pulse on the ERA line (all functions which change the group/page do this - i.e., CALL, BACK, UP and GROUP). Biggest numbers are 127 for 6-bit characters, 1023 for 7-bit characters.

B₁6 : for PRINT key. There are two print modes - mode A is initiated by pressing the PRINT key preceded by a number between 1 and 16 (when truncated to=16), or by pressing the print key with no preceding number when not already in mode A or B. The former will cause the specified row of the displayed page to be printed, preceded and terminated by a line feed, carriage return.

The latter will cause the complete page to be printed, preceded by a line feed, carriage return, and each row terminated by a line feed, carriage return. Several rows can be marked for printing before the first has been fully printed by repeating the row print command.

Mode A is terminated by the printing initiated above being completed, or by pressing the PRINT key with no preceding number when already in Mode A or B (this also terminates Mode B), or by doing an operation which sends a new GAD/PAD identifier pulse (i.e., pressing valid GROUP, CALL, UP, BACK) or by starting Mode B.

Mode B is initiated by pressing the PRINT key preceded by the number 0 (when truncated). This prints certain information on receipt of certain SCH's (see below). It is terminated by pressing the PRINT key preceded by a non-zero number (which initiates Mode A), or by pressing the PRINT key with no preceding number when already in Mode A or B (this also terminates Mode A).

C₁6 : for UP key. Any preceding number is ignored. The page number is incremented and the terminal informed via GAD/PAD and LEN lines with the group number unchanged. The screen is first cleared by an ERA pulse. If the page number is already at its highest limit (1023 for 6-bit characters, 4095 for 7-bit characters) the key pressing is ignored except for the screen being cleared, and KAC being set and cleared to release directed messages.

D₁6 : for BACK key. As UP except the page number is decremented, and no action is taken if the page number is already zero.

E₁6 : for CALL key. If this is not preceded by a number, zero is assumed. Else, the number is truncated to ≦1023 if the central computer is transmitting 6-bit characters (determined by SCH values - see below), or ≦4095 if 7-bit characters are transmitted. The page number is reset to this and the terminal informed in GAD/PAD and LEN lines, with the group number unchanged. The screen is first cleared by an ERA pulse.

F₁6 : when in idle state. When any key is pressed that key is not processed unless it is held constant for a minimum of 1 millisecond, to provide bounce protection.

As KEY is not reset to idle state unless the key has been released and KLR has been pulsed, KEY is not processed unless it is different from the last KEY processed, although KLR will be periodically pulsed.

Inputs (from printer interface 8004)

PAC b. Printer character clock PCC 1 line

Runs at the printer rate (10 cps). High for 27 milliseconds (3-bit times) during which stop and idle bits are sent to printer and when interface can receive a pulse (SPA, LFD, CAR or PRT) from the PPS. Low for 73 milliseconds during which a character is sent to the printer. Used to determine when to send one of the above pulses to the interface, and also as a count after a PRT pulse is issued to determine when a row has been printed.

Inputs (from terminal 8000)

PAC c. Row enable REN 1 line

Runs at the row rate of the terminal. 1 row = 13 scan lines = 13*63 microseconds (except during vertical retrace ≡ 5 milliseconds). Low while RAR changing and therefore invalid (especially during vertical retrace). High when RAR valid.

d. Row address (read) RAR 4 lines

When REN is high, contains the address (O→ 15) of the row currently being read from memory and displayed on the screen, and available for transmission to the printer interface. The printer interface must be told to accept the row, if it is the correct one, within 3 scan lines (= 3*63 microseconds) of RAR changing, by a PWR pulse.

e. Row address (write) RAW 4 lines

Contains the address 80→ 15) of the last row written to memory after being grabbed from the cable. It is latched onto this and will not change until a new row is read. As rows can preferably only be written during the 3 blank scan lines at the end of a row, this will only change 2 scan lines (110μsec = 22 cycles) before RAR changes. RAW will therefore be constant for a minimum of 10 scan lines after RAR changes.

f. Special character SCH 7 lines

Each row written (see RAW) has an SCH attached to it. This is changed at the same time as RAW and latched. Characters transmitted by the central computer are either 6 or 7 bits. To enable the PPS to known which, at least one row on Group 0, Page 0 will be transmitted with an SCH indicating which by its most significant bit (= 0= > 6-bit chars, = 1= > 7-bit). As group and page are automatically set to zero on power up, the PPS will known, from the very first page grabbed, what limits to set for page and group. Apart from this SCH, at the moment all other SCH's have individual meanings as follows:

0: Reset. Set to 0 by the terminal on power up. Real SCH's are zero when no action is to be taken, or when action started by an SCH is to be repeated. To ensure that action on any SCH is taken, the central computer will repeat it on the particular row several times. So to ensure a desired single operation is not repeated, the PPS will only act on an SCH which has changed on that row. Therefore, to repeat a similar operation, the central computer must send a zero SCH on the row before repeating the non-zero SCH. When a new page is selected, the PPS will act on the first SCH on each row, and then only when an SCH for a row changes.

1: Row print (select). The row specified by RAW is printed only if in print mode B.

2: Page print (select). The page displayed is printed only if in print mode B.

3: Row print override. The row specified by RAW is printed regardless of print mode.

4: Page start. Not used for any specific PSS function.

8: 64character row. The row specified by RAW is a 64 character row. If this row is printed later on, the PPS will wait for 64 clock pulses after issuing a PRT pulse before it sends the terminating LFD, CAR pulses. Receipt of this SCH sets RWL to 1.

10₁6 : 32 character row. The row specified by RAW is a 32 character row. If this row is printed later on, the PPS will send 16 SPA pulses (to space the row in the middle of the page), then a PRT pulse. After 3 clock pulses, it sends the terminating LFD, CAR pulses. Receipt of this SCH sets RWL to 0.

18₁6 : Erase. The PPS sends an ERA pulse to the terminal.

g. Permission PER 1 line

After a new group number is sent to the terminal this line is tested. If low, the terminal is not allowed to receive that group, so the group number is reset to zero (the page number will already be zero), and reset to the terminal. The line is valid at any time, even when KAC is still set.

Outputs (to keyboard 5000)

PAC a. Keyboard latch reset KLR 1 line

Pulsed when a key has been completely processed. KEY will then be reset to the idle state.

Outputs (to printer interface 8004)

PAC b. Printer write PWR 1 line

When a print is initiated, RAR is sampled until it equals the next row to be printed. PWR is pulsed within 189 microseconds of it changing, so the interface can write the row into its memory for printing on the PRT pulse.

c. Space SPA 1 line

On a 32 character row print, 16 leading spaces are printed, by sending this pulse once during each clock cycle when PCC is high for 16 times.

d. Line feed LFD 1 line

To print line feed, send LFD pulse while PCC high.

3. Carriage return CAR 1 line

To print carriage return, send CAR pulse while PCC high.

f. Print PRT 1 line

To print the row currently held in the printer interface buffer, send PRT pulse while PCC high and wait 32 or 64 clock times before issuing any other pulse to the interface.

Outputs (to terminal 8000)

PAC g. Erase ERA 1 line

Erases screen. Pulse when SCH 18₈ received, or when a group/page number is sent to the terminal, or when GROUP key is pressed with no preceding number.

h. Keyboard active KAC 1 line

Set while a group/page number is being sent to the terminal, so the terminal takes no action on it until the number is completely received. Will always be preceded by an ERA pulse. Also ensures directed messages are released, so set and cleared for any pressing of GROUP, CALL, BACK or UP, even if no new group/page number is sent.

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I/O Assignments (bit 0 = LSB, bit 3 = MSB)
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I/O 0(607a)
GRP A    (A) READ  SCH bits 0-3
(E) SET   SPA (bit 0), PRT 1,
1), LFD (bit 2), CAR (bit 3)
GRP B    (9) READ  KBD
(D) SET   PWR (bit 0), KLR (bit 1),
ERA (bit 2), LEN bit 4 (bit 3)
(Only used for pulse via TM
PLSB.)
GRP C    (3) READ  RAW
(7) SET   LEN bits 0-3
I/O 1(607a)
GRP A    (1A) READ SCH bits 4-6 (bits 0-2). Ex. 3
always 1. 0.
(1E) SET  GAD/PAD
GRP B    (19) READ RAR
(10) SET  RWL (bit 0)
(Any change of bits 1-3 must
leave RWL unaltered).
GRP C    (13) READ PER (bit 1), PCC (bit 2), REN
(bit 3)
(17) SET  KAC (bit 1)
(Any bit set excludes others
from being set).
______________________________________

Group address/Page address GAD/PAD 4 lines

To inform the terminal of a new page to grab, the page's identifier is sent in 5 pulses of 4 lines each. Afer the identifier is assembled in the PPS, the first 4 bits will reset on these lines, and LEN line 1 is pushed. Then the second 4 bits are set, and LEN line 2 is pulsed, and so on until all 20 bits are sent. The identifier is constructed from the group/page number as follows:

i. using 6-bit characters

bits 0→9=page number

bits 10/11=0

bits 12→18=group number

bit 19=0

ii. using 7-bit characters

bits 0→9=page number

bits 12→19=group number bits 0→7

bits 10/11=group number bits 8/9

j. Latch enable LEN 5 lines

Only 1 line pulsed at any one time. If line n is pulsed, the terminal will take the 4 GAD/PAD lines as the nth 4 bits of the new group/page identifier (20 bits).

k. Row length RWL 1 line

Latched on 1 for 64 character rows, 0 for 32 character rows. Set according to the last SCH of 8 or 10₁6.

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RAM (605) allocation (RxDY = RAM address xy)
(all initially zero unless otherwise stated)
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R0    D0/1/2   Group # [3rd digit - bits 8/9 - only used as tem-
porary storage as bits 8/9 group # normally held
in page #]
Also  D0/1/2   Page # [bits 10/11 = bits 8/9 group #]
used for binary # during decimal to binary
conversion
R3    D0/1/2/3 Keyboard # (decimal) R3D0 = F14 = > no
number yet/ R3D0 = most significant digit
R4    D0/1/2/3 Workspace. Used for current high limit and
during decimal to binary conversion.
R8    D0/1/2/3 Group # high limit (decimal). Initially 0, 1, 2, 7.
R9    D0/1/2/3 Page # high limit (decimal). Initially 1, 0, 2, 3.
R6    D0/1/2   KBD routine suspend address - used by STORE
S/R. Initally complement of address of
KBYX (C, F, F).
R1/R2          Complement of last SCH on each row. (R1 =
bits 0-3, R2 = bits 4-7)
R5             Row status for each row:
Bit 3 set = > print this row
Bit 2 set = > print leading CRLF
R3    D5       Current row - set to row being searched for,
or row being printed.
R6    D5       Row count # of rows searched for without being
printed.
R4    D5       Searching for row
= 0 = > yes
= 1 = > no Initially 1
R3/R4 D6       6-bit count for printing. Used when printer pulse
occurs and printing in progress.
If = 0, next o/p is shifted left and if ≠ 0, that
pulse is sent (if = 2 when shifted, new count is
set also).
If when shifted, next o/p = 0, then next row to
print is searched for.
If ≠ 0, next o/p is masked with mask and that
pulse sent after the count is decremented.
R0    D7       Row length = F = > 64 char rows = E =
> 32 char rows. Set by last SCH of 8 or 1014.
R3    D7       Next o/p
= 1 = >SPA] ≠ 0 = > printing in progress
= 2 = >PRT] = 0 = > no printing
= 4 = >LFD]
= 8 = >CAR]
This digit is sent on I/O 0 group A as a pulse
after being masked or shifted as above.
R4    D7       Mask
= 0 = > Do not send SPA or PRT pulse unless
count = 0 (then no mask takes place).
64 character rows (set when row to
be printed)
= 1 = > Do not send PRT pulse unless count
= 0. 32 character rows
[Remember when count = 0, shift left of next o/p
occurs before pulse.]
R3    D8       Last PCC valve (in bit 2).
R4    D8       4 (constant mask for above). Initially 4
R0    D9       Current KBD character.
Register Allocation
FF1             = 1 = > Print mode A (KBD printing)
FF2             = 1 = > Print mode B (SCH printing)
X               Temporary working space
R3    D9        KBD count
= 0 = > KBD character can be processed
≠ 0 = > No. of program loops to go before
KBD character is accepted (bounce
protection)
R4    D9        Complement of last KBD character
R3    D10       Complement of last RAR
R4    D15       Workspace used to access each digit in
binary to decimal conversion
______________________________________

__________________________________________________________________________
ROM (608) Map
Page    Description               Spare Words
__________________________________________________________________________
0   (00)        Initialization (63)
1
1   (40)        Check RAR/SCH/RAW
(43)
Check RAR      (17)
5
2   (80)
Scheduler
Check PCC      (61)
Go to KBD check
(1)
Return to start of scheduler
(2)
0
3   (C0)        RAM addresses (1st 16 words)
(16)
0
S/R addresses (last 48 words)
(26)
22
4   (100)       Go to SCH decoder
(2)
Switch S/R     (7)
Binary shift left S/R
(7)
Stop printing S/R
(7)
Pulse I/O 0 group B S/R
(6)
Suspend S/R    (6)
KBD decoder S/R
(23)
6
5   (140)       Get row S/R    (35)
SCH row print [3 S/R's]
(27)
2
6   (180)       SCH page print [2 S/R's]
(19)
SCH erase [2 S/R's]
(8)
SCH row length [2 S/R's]
(10)
SCH character length S/R
(10)
Clear 3 digits S/R
(7)
2
Reset special characters
(8)
7   (1C0)       KBD numeral S/R
(7)
KBD up S/R     (28)
KBD back S/R   (21)
Go to KBD call (2)
Go to KBD group
(2)
Go to KBD print
(2)
2
8   (200)       SCH decoder switch jump
(1)
63
(240)       SCH decoder table
(128)
0
10
11  (2C0)       KBD print S/R  (56)
8
12  (300)       Check KBD      (23)
RAR check - print row
(36)
RAR check - get row
(2)
3
13  (340)       KBD group S/R  (11)
KBD call S/R (Pt 1)
(50)
3
14  (380)       KBD call S/R (Pt 2)
(57)
7
15  (3C0)       KBD call S/R (Pt 3)
(60)
4
__________________________________________________________________________

It is of course understood that the above program and program description is merely provided by way of example and other programs and program arrangements could be utilized to accomplish the row grabbing video display function of the present invention without departing from the spirit and scope thereof. In addition, as previously mentioned, if desired a conventional keyboard control system such as described in our previous U.S. Pat. No. 3,889,054 could be utilized in the improved row grabbing system of the present invention in which instance the microprocessor 6000 and the associated programming required therefor would be omitted. It should be noted that with respect to FIG. 10 which illustrates the keyboard 5000, the keyboard key switches 823 and associated lines 823a through 823d with their respective associated flip-flop latches 824, 825, 826 and 827, respectively, which are cleared by the signal present on path 6007, are preferably indentical in operation with that previously described in our previous U.S. Pat. No. 3,889,054 which description is specifically incorporated by reference herein.

Similarly, referring to FIG. 13 which illustrates a portion of the improved memory output processor portion of the receiver 28 of the present invention, this portion is preferably identical with that described in our previous U.S. Pat. No. 3,889,054 with the exception of the erase circuit and the special character latching functions utilized with 32-or 64 character selection, to be described in greater detail hereinafter with reference to FIG. 13. Identical reference numerals are utilized for identically functioning components in FIG. 13 with those previously described in our previous U.S. Pat. No. 3,889,054 with reference to FIG. 12 of that patent which description was specifically incorporated by reference herein and will not be repeated. It should be noted that reference numeral 901 represents a special character latch, with the fifth character preferably being the special character, and, accordingly, latch 901 is strobed via path 903 during the fifth character. Any time a new valid pseudo video scan line s received, the special character, which is as previously mentioned preferably the fifth character, of that pseudo scan line is entered into latch 901. The output of latch 901 is preferably provided to microprocessor 6000, as represented by the symbol "SCH" to provide an input thereto. Preferably, microprocessor 6000 does not act on all special characters such as for example not acting with respect to 32-or-64 character selection, although, if desired, the microprocessor could also be programmed to accomplish this.

ERASE CIRCUIT

Now considering the improved erase circuit portion 905 of the memory and output processor portion illustrated in FIG. 13, the erase circuit 905 provides a means for making the screen of the video display device 2013 go blank. This is desirable at initial turn on at which time the main memory would come on with a random bit pattern which in turn would display a random assortment of characters which would be meaningless and, perhaps, confusing to the viewer. Erase is accomplished by loading all character locations in memory which comprises stages 1030 through 1042 preferably with an octal 40 value which is the value which corresponds to a "space" in ASCII code. The erase cycle can be initiated also by the microprocessor 6000 in response to the appropriate special character assigned for the erase function or whenever a keyboard cycle takes place, if desired. The erase cycle is preferably initiated by a conventional flip-flop 907 which gets set initially when power is on as a result of an RC charging network 909 through inverters 911 connected to the preset input of flip-flop 907. Flip-flop 907 can also preferably get set by microprocessor 6000 via the clock input provided via path 913 from microprocessor 6000. Once set, flip-flop 907 preferably enables a conventional two input NAND gate 925 which also receives the vertical sync pulse via path 923. Therefore, the first vertical sync pulse that occurs after flip-flop 907 is set appears as a negative pulse at the clock input of a second flip-flop 915 to which the output of gate 925 is connected. Flip-flop 915 is clocked to its set state preferably at the trailing edge of the vertical sync pulse. When set, the output of flip-flop 915 preferably switches a conventional multiplexer 917 such as a Texas Instruments SN 74157N, which accomplishes the switching necessary to load the memory octal 40 values; specifically, switch 917a and 917b illustratively shown separate in FIG. 13 actually comprise the multiplexer 917 with switch 917a of multiplexer 917 loading a logic one into the correct bit position of character latch register 468 whose operation is described in detail in our previous U.S. Pat. No. 3,889,054, to obtain octal 40 therefrom. All of the other bits are preferably set to 0 via path 919 which is connected to the inverted output of flip-flop 915 with the signal present thereon turning off the input to shift register 466 previously described in detail in our previous U.S. Pat. No. 3,889,054, via a conventional two input NAND gate 921 whose inputs are the output of shift register 457, which is also previously described in our U.S. Pat. No. 3,889,054, and the inverted output of flip-flop 915. As a result, all logic zeros are present at the outputs of shift register 466 which logic zeros are provided to the inputs of character latch register 468 except for the previously mentioned single bit. Switch 917b of multiplexer 917 switches multiplexer 1020, which is described in detail in U.S. Pat. No. 3,889,054, so that the read row addresses are applied to the memory stages 1030 through 1042 even though the memory stages 1030 through 1042 are in the write mode during the erase cycle. This insures that all memory locations are addressed during erase. Termination of the erase cycle is preferably accomplished by the second vertical sync pulse that occurs after flip-flop 907 has been set. The second vertical sync pulse clocks flip-flop 915 back to its original state and also clears flip-flop 907 via another conventional two input NAND gate 927 whose output is provided to the clear input of flip-flop 907 through an inverter 929. Thus, both flip-flops 907 and 915 are returned to their original state. The period of the erase cycle is thus preferably one vertical field period, this time being adequate to insure that all memory stage locations 1030 through 1042 have been addressed. As was previously mentioned the balance of the circuitry illustrated in FIG. 13 is adequately described in detail in our previous U.S. Pat. No. 3,889,054 which was specifically incorporated by reference herein.

PERMISSION MEMORY CIRCUITRY

Referring now to FIG. 12, the improved permission memory circuitry utilized in the preferred improved row grabbing terminal 28 of the present invention shall be described in greater detail. Except where otherwise specifically noted, the portions of the circuit in FIG. 12 are preferably identical with the permission memory circuitry described in our previous U.S. Pat. No. 3,889,054 with reference to FIG. 11 of that patent and identical reference numerals are utilized therefor. Thus, this description which is incorporated by reference herein will not be repeated and the following discussion of the improved permission memory circuitry will primarily be directed to the differences over the permission memory circuitry described in U.S. Pat. No. 3,889,054. In the previous permission memory circuit of U.S. Pat. No. 3,889,054, counters 974 and 976 were initially cleared to zero rather than being preloaded to a predetermined number such as 254. Thus, this previous system could possible provide a couple of extraneous clock pulses before the first permission bit was received so that the counter was at a value of one when the first permission arrived and, accordingly, group 0 would not be available. In the improved permission memory circuit shown in FIG. 12, counters 974 and 976, which are four bit counters, constitute a 256 bit counter, although if desired a 128 bit counter could be utilized instead. This counter, which is comprised of counters 974 and 976, is preferably utilized for addressing the permission memory 462 during the permission write cycle. Counters 974 and 976 are preferably initially loaded to a predetermined value, such as preferably 254, which is accomplished by utilizing the load input 931 of counter 976 in conjunction with the preset inputs 933a and 933b of counters 974 and 976, respectively. As a result of the preload via path 931, at the beginning of a permission write cycle, the first two clock pulses advance the counter 974-976 to 0. The second clock pulse occurs just prior to the availability of the first permission bit. This timing sequence makes it possible for the first permission bit to represent group 0. Thus it is possible to insure permission for groups 0 through 127 on one pseudo video scan line. As shown and preferred in FIG. 12, 128 groups are provided via the connection of permission memory 462; however, as will be described in greater detail hereinafter, if desired, additional counters may be provided in conjunction with permission memory 462 so as to provide up to 1000 groups.

The improved permission memory circuit illustrated in FIG. 12 also enables self-termination of permission write to return the system to the normal mode of a permission line occurs at the end of a field. This is accomplished in the following manner. An inverter and NAND gate constitute a decoder 935 that generates a pulse preferably at a count, such as 192, which is greater than the number of groups, which were previously mentioned as being 128 by way of example in the arrangement illustrated in FIG. 12, and less than the number of bits in a data line to permission memory, which number of bits preferably constitutes 238 by way of example. The number 192 is preferably chosen for ease of decoding although it could be any number between 128 and 238, the criteria for these limits being defined as being greater than the number of groups and less than the number of bits in a data line to permission memory. This pulse is provided through an inverter 937 to an input of a conventional two input NOR gate 939 whose other input is the keyboard active line 941 and whose output is utilized to reset the permission flip-flop 960. The flip-flop 960 is guaranteed to get reset even if the completion of permission write occurs during vertical blanking. In such a case, flip-flop 960 would not otherwise get reset because the decoded character 41 pulse present on path 413 is not normally generated during vertical blanking. During a keyboard cycle, the group address is preferably not a valid signal. Therefore, the output of the permission memory 462 would not be valid. Accordingly, in order to prevent an erroneous authorization, flip-flop 960 is held in a reset state during the keyboard cycle. This is accomplished by the keyboard active line or KAC 941 which is generated by microprocessor 6000 which, as was previously described, is applied to the other input to NOR gate 939. Preferably, the improved permission memory of FIG. 12 provides permission initialization when the power is turned on, the permission memory circuit automatically selecting group 0, page 0 at such time. When the first permission line is received by receiver 28, the permission memory circuit of FIG. 12 will then preferably revert to normal operation. THis initial mode, group 0, page 0 on turn on, is preferably established by flip-flop 953 which is initially preset by line 955 (FIG. 13) when power is turned on. The output of flip-flop 953 is preferably applied to a conventional NOR gate 957 via line 959 and sets the permission O.K. line 556 through an inverter 961. This asserts permission. Line or path 959, which is also preferably connected to gate 963 of the page address circuit (FIG. 11), and is termed pre-permission, also sets line 508 low. This simulates an address of page zero, group zero.

Referring now to FIG. 14, the improved permission memory update circuitry for updating the permission memory 462 (FIG. 12) is shown and will be described. As will be described in greater detail hereinafter, the purpose of the improved permission memory update circuitry is to avoid any flicker which might otherwise occur in the video display on display device 2013 during update of the permission memory as a result of such update. In the improved circuitry of FIG. 14, the previously considered clock B signal is replaced by the prime clock provided via path 401 from the voltage controlled oscillator 130 (FIG. 3). This prime clock input provided via path 401 to the permission memory update circuitry is inverted by an inverter 965 and applied to a conventional single-shot 967. Preferably, the purpose of single-shot or one-shot 967 is to generate a symmetrical square wave which is required by the conventional frequency double circuitry comprising inverters 1074 and 1076 and exclusive OR gate 1078. As described in our previous U.S. Pat. No. 3,889,054, inverters 1074 and 1076 provide a predetermined delay, such as 100 nanoseconds in the prime clock signal provided via path 401, this delay time preferably representing a fraction of the clock period. It is this delayed prime clock signal which is preferably supplied to one input of the two input exclusive OR gate 1078 whose other input is directly connected to the prime clock input provided at the output of single-shot 967. Exclusive OR gate 1078 preferably provides an output only during the period of time that the delayed prime clock signal overlaps the undelayed prime clock signal, which occurs twice per clock period and, as a result, two output pulses are available from gate 1078 for each input pulse. As shown and preferred in FIG. 14, the output of exclusive OR gate 1078 is fed to a conventional switch 1079 which selects between the 32 character position and the 64 character position depending on the desired character display, with the exclusive OR gate 1078 output being connected to the 64 character position and the non-doubled or direct prime clock signal being connected directly to the 32 character position of switch 1079. The output of switch 1079 is provided to the clock input of a conventional divide-by-eight counter 1080 previously described in our U.S. Pat. No. 3,889,054, such as the type manufactured by Texas Instruments under the designation SN74161N, which is a four bit binary counter connected as a divide-by-eight counter, although, if desired, a conventional divide-by-eight counter could be utilized. Thus, the frequency doubled clock signal is preferably utilized as the clock for counter 1080 only during 64 character operation while, during 32 character operation, that is 32 characters per video row versus 64 characters per video row, counter 1080 is clocked directly by the prime clock signal. The prime clock signal provided via path 401 is preferably unaffected by the permission write mode (FIG. 8). The normal horizontal sync signal provided via path 969 is preferably utilized for the horizontal timing of all of the display circuits including the memory read circuit. The horizontal sync on path 969 is also unaffected by the permission write mode as it is the normal sync during the permission write mode.

The clear signal for counter 1080 is preferably developed as follows. Counter 971 in conjunction with flip-flop 973 establishes the start of a display video row. During horizontal sync, counter 971 is preloaded to a count which depends on whether the terminal 28 is operating as a 32 or 64 characters per row terminal. When the terminal 28 is operating as a 32 character per row terminal, the perload condition for counter 971 is preferably selected as one value, such as preferably 15, and when the terminal 28 is operating in the 64 characters per row mode the preload for counter 971 is preferably selected as another value, such as preferably 11. Whichever value is selected, that value is selected so as to obtain the correct starting position on the display screen. A different perload condition is preferably required for the 32 and 64 characters per row modes because preferably a different clock frequency is required for these two modes.

At the conclusion of the horizontal sync pulse, counter 971 preferably starts counting at the prime clock rate which prime clock is provided to the clock input of counter 971 from single-shot 967. At the completion of the count, the output of the two input NAND gate 975, which has one input connected to the noninverted output of flip-flop 973 and the other input connected in parallel to the clock input to flip-flop 973 prior to inversion thereof, goes low and stops the counting using the P inhibit input of counter 971. Preferably a predetermined count value, such as preferably a value of 31, terminates the count cycle. The negative level present at the output of gate 975 is also provided in parallel through an inverter 977 and applied to the clear input of counter 1080 which enables counter 1080 by removing the clear state and counter 1080 starts its count sequence. Thus, by utilizing the prime clock for row one and the normal horizontal sync 969 together with the improved circuitry for enabling counter 1000, the display circuits are preferably independent of the permission memory update and, thus, any flicker which might otherwise occur in the display during such update as a result thereof is minimized and preferably avoided. The balance of the circuitry associated with FIG. 14 is preferably identical with that described in our previous U.S. Pat. No. 3,889,054 with reference to FIG. 13 thereof.

MAIN MEMORY UPDATE

Referring again now to FIG. 12, the improved main memory update circuitry shall be described in detail hereinafter. Preferably, under normal conditions when the main memory whih comprises stages 1030 through 1042 (FIG. 13), is in the write mode, the outputs of these stages 1030 through 1042 are not valid. Thus, as shown and preferred in FIG. 12, update control circuitry 979 is provided to prevent the main memory updating or writing if a valid pseudo video scan line is received while a row is being displayed. If a valid pseudo video scan line is received while a row is being displayed, other than during the occurrence of dead space on the screen, this line will perferably be stored in shift register 457 (FIG. 13) until completion of that displayed row and the line then would be written into memory 1030 through 1042 during the dead space following the row. When a valid pseudo video scan line is received, path 981, which is connected to the output of NAND gate 986, goes low and sets a flip-flop 983 which remains set preferably until the display sweep completes the 12th line counted of a row which is equivalent to line 11 which is a preferably dead line of a row with lines 1 through 9 of the row preferably being considered active lines for a row. The information corresponding to line 11 is provided to a three input NAND gate 985 which decodes the count of 11 provided from the output of line counter 1056 (FIG. 14) and provides a negative pulse to the clock input of flip-flop 983. Flip-flop 983 is then preferably reset at the end of that pulse; that is, at the completion of the 12th line counted which is equivalent to line 11. In this regard, it should be noted that the zero line is the first line counted and, therefore, the 11th line or a count of 11 is the 12th line counted. The time during which flip-flop 983 is set preferably establishes the time during which the input data must be stored in the one line shift register 457 (FIG. 13) which preferably stores this information as long as flip-flop 983 is set plus one more line to enable for shifting out and writing into memory 1030 through 1042. Update control circuit 979 also preferably includes a two input NAND gate 987 which has one input connected in parallel to the Q or non-inverted output of flip-flop 983 and the other input connected to the output of NAND gate 983. The output of gate 987 is preferably provided through an inverter 989 to one input of another gate 991 whose other inut is the data gate signal provided via path 993 from flip-flop 696 (FIG. 8). The output of gate 991 is the gate hold signal which is provided via path 997 to flip-flop 1002 (FIG. 13) and is the control line which stops the clocking of shift register 457 (FIG. 13) during the period that flip-flop 983 is set excluding the 12th line counted; in other words, the output of gate 991 via path 997 goes low when a valid pseudo video scan line is received and goes high at the beginning of the 12th line counted, which is equivalent to line 11. The output of gate 991 preferably cannot go high until the inverted data gate line 993 goes low. This continues to hold data in the serial shift register 457 (FIG. 13) preferably until the fourth character. Thus, the clocking of shift register 457 is preferably enabled at the beginning of the fourth character of the transmitted pseudo video scan line after the 12th line counted (line 11) of the displayed row is started. As was previously mentioned, the output of gate 991 is preferably applied to the preset input of flip-flop 1002 via path 997 (FIG. 3). The Q output of flip-flop 983 is also preferably connected in parallel to one input of another two input NAND gate 999 whose other input is connected through an inverter to the output of gate 985. Gate 999 preferably produces a negative level during the 12th line counted (line 11) which terminates a hold period. This 12th line counted is the time during which data is preferably written into the main memory 1030 through 1042 (FIG. 13). The low level at the output of gate 999 is preferably applied to the main memory control (read) line 446 via a two input NOR gate 1001, whose other input is the inverted erase signal, through an inverter 1003. Gate 1001 preferably causes the memory control read line 446 to also go low during an erase cycle as a result of the inverted erase input applied thereto. As was described in out previous U.S. Pat. No. 3,889,054, the output of gate 994 which is provided through an inverter 996 preferably generates the memory pulse R/W via path 995 which is provided to the memory 1030 through 1042 through inverter 1047 and gate 1046 via path 1044 (FIG. 13). Thus, the operation of the update control circuit 979 preferably prevents any possible flicker in the display during the main memory write mode. The balance of the circuit of FIG. 12 is preferably identical with that described with reference to FIG. 11 of our previous U.S. Pat. No. 3,889,054 with the exception of the differences previously noted above.

COMPUTER/PRINTER CRT DISPLAY INTERFACE

Referring now to FIGS. 24 and 25, the computer/printer CRT display interface 8004 which was generally referred to with reference to FIG. 26 with respect to the option of utilizing a printer to provide hard copy text in addition to the video display of information shall be described in greater detail. As was previously mentioned, the above described system will function as an improved row grabbing terminal 28 without the additional computer/printer CRT display interface 8004 and printer 8006, if such hard copy text material is not desired, without departing from the spirit and scope of the present invention. However, assuming such hard copy text is desired, the computer/printer interface 8004 shall now be described with reference to FIGS. 24 and 25. As will be described in greater detail hereinafter, the interface 8004 preferably utilizes character information when available at a high speed rate so as to enable continuous high speed video display of the information which is normally preferably provided with the improved row grabbing terminal 28 of the present invention, as well as with out previously described row grabbing terminal described in U.S. Pat. No. 3,889,054, while also enabling real time pick off of this information for printing. The printer 8006 is preferably a conventional matrix printer, such as an Extel Model No. AF11, whose operations are preferably controlled by the microprocessor 6000. The following functions are preferably commanded by the microprocessor 6000: PRINTER WRITE, PRINT, LINE FEED, CARRIAGE RETURN, SPACE COMMAND, and the 32/64 CHARACTER COMMAND, as indicated by the control lines illustrated in FIGS. 24 and 26. The PRINTER WRITE COMMAND from the microprocessor, provided via path 1007 from microprocessor 6000, preferably causes the printer interface 8004 to write a row of characters into a buffer memory 1011 from the terminal main memory 1030 through 1042 as will be described in greater detail hereinafter. The PRINT COMMAND, provided via path 1013 from microprocessor 6000, causes the interface 8004 to output the row of characters to the printer 8006 at the proper baud rate for the printer 8006, such as at 110 baud, in serieal EIA standard format including start and stop bits for the printer 8006. The LINE FEED COMMAND, provided via path 1015 from microprocessor 6000, preferably causes the interface 8004 to issue an ASCII line feed character to the printer 8006 in the same format as the characters; that is, in serial EIA standard format at the same rate, such as the 110 baud rate. The CARRIAGE RETURN COMMAND, provided via path 1017 from microprocessor 6000, preferably causes the interface 8004 to issue an ASCII carriage return character to the printer 8006 in the same format as the characters. The SPACE COMMAND, provided via path 1019 from the microprocessor 6000, preferably causes the interface 8004 to issue an ASCII space character to the printer 8006 in the same format as the characters. The 32/64 CHARACTER COMMAND, provided via path 1021 from microprocessor 6000 to interface 8004, preferably causes the interface 8004 to write into its memory 1011 the correct number of characters. Thus, as will be described in greater detail hereinafter, the microprocessor 6000 can establish each printed page format.

Now describing the memory write mode for the interface 8004. When the interface 8004 receives a PRINTER WRITE COMMAND via path 1007, this signal is provided to the clock input of a flip-flop 1023 which is clocked to a set state. This causes a second fip-flop 1025 to subsequently be clocked to its set state by the first horizontal sync pulse occurring after flip-flop 1023 is clocked to its set state. When flip-flop 1025 is set, its Q or inverted output preferably resets or clears flip-flop 1023 via path 1023a. The set output of flip-flop 1025 preferably operates a conventional multiplexer 1027, such as a Texas Instruments SN74157N which is illustratively represented in FIG. 25 by further illustrating its various sections 1027a, 1027b, 1027c and 1027d as switches which are located in FIG. 25 in their appropriate functional positions for purposes of clarity. Thus, the operation of multiplexer 1027 preferably puts the interface 8004 into the write mode. Multiplexer section 1027d connects the horizontal sync pulse to the clock input of a conventional bit counter 1029 which will therefore advance one count for each TV line after the start of the write cycle. The write cycle preferably lasts for eight horizontal lines. During each of the eight horizontal lines, one bit from the main memory 1030 through 1042 of each character is preferably written into the buffer memory 1011. Thus, for example, for line one, no bit is selected; for line two, bit 7 for every character in line two is selected; for line three, bit 6 for every character in line three is selected; for line four, bit 5 for every character in line four is selected; for line five, bit 4 for every character in line five is selected; for line six, bit 3 for every character in line six is selected; for line seven, bit 2 for every character in line seven is selected; and for line eight, bit 2 for every character in line seven is again selected; however, it is inverted. A conventional bit select multiplexer 1031 preferably selects the appropriate main memory stage 1030 through 1042 line for each of the eight counts. During the first count, no line is selected if there are only 7 bits per character. During the second count, the memory line corresponding to the 7th bit is selected. This process continues for each line with the memory line for the second bit being selected on the seventh count. As was previously mentioned, on the eighth count the memory line for the second bit is again selected, but it is applied to multiplexer 1031 through an inverter 1033. The purpose of the above procedure is to preferably convert the standard 6 bit ASCII code from the main memory 1030 through 1042 into a 7 bit standard ASCII code which is used by the printer 8006, such conversion preferably being conventional. The output of multiplexer 1031 is preferably applied to the D input of a flip-flop 1035 which is clocked by the PRINTER LATCH CLOCK provided via path 1037 from gate 1094 (FIG. 14) and is preferably the same waveform that operates the character generator 570 (FIG. 14). Flip-flop 1035, as was previously mentioned, is a D flip-flop and, thus, the output follows the input but is delayed by an amount determined by the PRINTER LATCH CLOCK 1037. The purpose of flip-flop 1035 is to preferably provide a logic level which is stable for the full character period to the buffer memory 1011. The clocking of memory 1011 is preferably accomplished via R/W line 1039 through multiplexer section 1027a which is shown in the write position in FIG. 25, this signal being a clock signal provided by multiplexer 1041. The select inputs of multiplexer 1041 which are 1043a, 1043b and 1043c, peferably select either a low or high level to provide a clock waveform via path 1039 with a period equal to a character period. The timing of the clock waveform 1039 is preferably such that data is clocked in memory 1011 after the data has been loaded into the flip-flop 1035. Memory 1011 is preferably a one-by-1024 bit static random access memory. Thus, it preferably has one data input line and ten address lines with three of the address lines preferably being used for the bit address, allowing 8 bits per character, and six of the address lines preferably being used for the character address, allowing for up to 64 characters, one of these character address lines not being utilized when 32 character lines are to be printed as opposed to 64 character lines. The tenth address lines is preferably not utilized. The bit address for memory 1011 preferably comes from the same bit counter that operates the bit select multiplexer 1031, while the character address preferably comes from a pair of conventional character counters 1045 and 1047. During the write mode of operation, the character counters 1045 and 1047 are preferably utilized simply as latches to store the character address for the main memory 1030 through 1042 and to apply it to the buffer memory 1011. The character address is strobed into the character counters 1045 and 1047 by the PRINTER LATCH CLOCK 1037. The load inut to counters 1045 and 1047 is preferably held low during the write mode by flip-flop 1025. It should be noted that the bits need only be selected at the character rate not at the bit rate since a given bit number for each line in the character contains the same information to the character generator input for that character; therefore, for example, bit 1 provides the same bit 1 information for all nine lines; similarly bit 2 provides the same bit 2 information for all nine lines, etc., thus enabling the use of a lower speed circuit thereby slowing things down so that the printer can be operated at normal speed. Thus, the preferred system takes advantage of the eight-to-one differential between the bit and character rates such as, by way of example, in the 64 character mode the bit rate being 10.2 megahertz and the character rate being approximately 1.28 megahertz, while in the 32 character mode the bit rate being 5.1 megahertz and the character rate being approximately 0.64 megahertz. Summarizing the above described memory write cycle, this cycle starts with the bit counter 1029 preferably set for bit 1 which corresponds to count 0, the character counters 1045 an 1047 addressing characters 1 through 32 or 1 through 64 and writing all zeros into memory 1011. At the start of the next TV line, the bit address out of counter 1029 is advanced by one and the character counters 1045 and 1047 again address characters 1 through 32 or 1 through 64 depending on whether it is in a 32 character mode or a 64 character mode and write bit 7 into memory 1011. This preferably continues through eight counts or bits of the bit counter 1029, writing bits 6, 5, 4, 3, and 2 into memory 1011 as the line changes. At the beginning of the ninth TV line, the D output of bit counter 1029 preferably goes high to the K input of flip-flop 1025 causing flip-flop 1025 to be reset at the trailing edge of the horizontal sync pulse. The resetting of flip-flop 1025 thereby terminates the write mode with flip-flop 1023 having previously been reset after flip-flop 1025 was set.

Now describing the output mode, which with reference to FIG. 25 is a mode in which all multiplexer sections or switches are set at the R or read position, all of these sections or switches being at the W or write position in the write mode. The output mode preferably comprises the print mode, the line feed mode, the carriage return mode and the space mode. During the output mode, the bit clock is preferably generated by a conventional oscillator 1049 which preferably comprises a conventional integrated circuit oscillator such as an NE555V, which is set at a frequency of preferably 110 hertz for the 110 baud rate described above by way of example. This corresponds to a print rate of 10 characters per second using an 11 bit per character format. It should be noted, however, that the printer rate can be set at any desired value merely by changing the oscillator 1049 rate, although the presently preferred printer rate is 110 baud. An 11 bit format preferably consists of one start bit, 7 character bits, one parity bit, which is preferably not utilized, and 2 stop bits. During the output mode, multiplexer 1027 is preferably not activated and the output of oscillator 1049 is preferably applied through multiplexer section 1027d to the clock input of bit counter 1029, which counter can preferably count up to 16 for the example given, although counter 1029 preferably operates in a count 11 mode. Thus, preferably when the output of counter 1029 is equal to binary 10, a gate 1051 connected thereto acts as a decoder and applies a negative level to the clear input of counter 1029 through a two input NOR gate 1053 whose other input is connected to the J output of J-K flip-flop 1025. Preferably, counter 1029 has a synchronous clear so that it is cleared to zero on the next clock following count 11. In addition, during the output mode, counter 1029 preferably establishes the bit sequence of the serial line to the printer 8006 with the counter 1029 count value 0, corresponding to count one, establishing the printer start bit and with counter values 1 through 7, corresponding to counts two through eight, establishing the data bits, count values 9 and 10, corresponding to counts 10 and 11, establishing the printer stop bits, and with count value 8, corresponding to count 9, preferably not being utilized.

With reference to the print mode, microprocessor 6000 preferably initiates a print cycle, as was previously mentioned, by pulsing line 1013. This pulse, provided via path 1013, is the PRINT COMMAND and clocks a flip-flop 1055 to its state. The set output of flip-flop 1055 is preferably applied to the enable inputs P and T of character counter 1045 which then advances when clocked by the D output of bit counter 1029. Thus, character counter 1045 advances at count value 8 of the bit counter 1029 which is the D output of counter 1029. As a result, the memory 1011 is addressed sequentially through the bit and character values that constitute one row. Thus, the output of memory 1011 is a serial bit stream when bits 1 through 8 of character 1 first appear with bits 1 through 8 of subsequent characters following. In each case, bit 1 is a zero level and bits 2 through 8 are the bit values of the character retrieved from memory 1011. The output of memory 1011 is preferably applied to one input of a two input NOR gate 1057, the other input thereto preferably being provided from the reset output of flip-flop 1055 which is low during the print mode. Thus the output of gate 1057 is the inverted bit stream from memory 1011, this inverted bit stream preferably being applied to one input of a negative NAND gate 1059, the other input thereto being low during this print mode so that the non-inverted bit stream is present at the outputof gate 1059. The output of gate 1059 is provided as one input to a two input NOR gate 1061, the other input thereto being the D output of bit couner 1029 which is preferably high during bits 9, 10 and 11. Thus, the output of gate 1061 is inverted data including the printer start bit during bits 1 through 8, but is a steady low level during bits 9, 10 and 11. The output of gate 1061 is preferably inverted by an inverter 1063 to provide the final serial output through a level changer 1065 to the printer 8006. The output of inverter 1063 preferably has a high level during bit 1, which is the printer start bit, and follows the data during bits 2 through 8, with this output being low during bits 9, 10 and 11. This corresponds to the prescribed preferred EIA format for a 0 start bit and two 1 stop bits. Level changer 1065, which is also a line driver, preferably generates an output signal such as, by way of example, with +12 volts representing binary 0 and -12 volts representing binary 1, these levels being prescribed by the EIA serial line interface standard. At the end of the row, a decoder 1067 preferably provides a negative level to reset flip-flop 1055 with the decoder 1067 preferably being programmed via line or path 1021 from the microprocessor 6000 be setting the appropriate input levels to provide a negative output in the case of a 64 character format at count value 64, which is at the beginning of count 65 of the character counter 1047, and to provide a negative output in the 32 character ode at count value 32, which is at the beginning of count 33 of character counter 1047. This resetting of flip-flop 1055 preferably terminates the print mode.

The microprocessor 6000 can also preferably command a single special function character such as for example LINE FEED, CARRIAGE RETURN or SPACE. Preferably, if the microprocessor 6000 wants a repeated special function character, it must recommand the character after adequate time, such as for example, 0.1 seconds for a 110 baud rate, has elapsed for the first special function character to have been isued to the printer 8006. A multiplexer 1069, such as a Texas Instruments SN74151AN, is provided which preferably functions as a programmable character generator to provide the proper bit sequence that corresponds to the special character which has been requested. The microprocessor 6000 commands a line feed preferably by pulsing line 1015 with the LINE FEED COMMAND. This clears flip-flop 1071 which is normally in a set state with flip-flop 1071 setting a low level at bit input 2 of multiplexer 1069 via path 1071a, and also sets bit input 4 low via NOR gate 1072, all other bit inputs to multiplexer 1069 preferably being high. Multiplexer 1069 preferably sequentially switches the bit inputs 0 through 7 to the output Y under control of the inputs A, B, C from bit counter 1029. As a result, a serial output is applied from multiplexer 1069 to one input of gate 1059. At this time, the other input to gate 1059 is preferably a steady low level so that the single character bit stream is provided to the NOR gate 1061. This bit stream is preferably combined with the stop bits and is applied to the output line to printer 8006 from level changer and line driver 1065 in th same manner as previously described with respect to the print mode. At the completion of one special character, flip-flop 1071 is preferably reset by the D output of bit counter 1029 via multiplexer section or switch 1027c, NAND gate 1073 and inverter 1075, with the output of inverter 1075 preferably being connected in parallel to also provide the character clock for the microprocessor 6000. This preferably completes a line feed cycle.

When a CARRIAGE RETURN COMMAND is requested by the microprocessor 6000, it pulses line 1017 and clears flip-flop 1077 which then sets bit input numbers 1, 3 and 4 low to multiplexer 1069, multiplexer 1069 then generating a single character return ASCII code in the manner as previously described with respect to the LINE FEED code. Flip-flop 1077 is also preferably reset in the same manner as previously described with respect to the LINE FEED by the next character clock from inverter 1075.

When the microprocessor 6000 commands a space by providing the SPACE COMMAND by pulsing line 1019, flip-flop 1079 is cleared which then sets bit input number 6 low to multiplexer 1069 causing multiplexer 1069 to then generate a single space ASCII code in the same manner as previously described with respect to LINE FEED. Flip-flop 1079 is also preferably reset in the same manner as previously described with respect to LINE FEED by the next character clock provided from inverter 1075.

It should be noted that preferably the character counters 1045 and 1047 are cleared during either a line feed or carriage return by the low level from NOR gate 1072. Thus, one row connot follow another to printer 8006 unless a LINE FEED or CARRIAGE RETURN is issued. However, normally microprocessor 6000 will generate such a CARRIAGE RETURN and LINE FEED between each row. Thus, the interface 8004 enables the microprocessor 6000 to make the following types of decisions: what row to be printed, how many rows, whether to print a 32 or 64 character row, how much marginal space for the row and whether or not extra spaces are to be placed between rows. These decisions are based on keyboard inputs from the operator provided to the microprocessor 6000, and inputs from the transmitted data in the form of special characters, directed messages or override messages provided to the microprocessor 6000. Due to all of the above, the computer/printer interface 8004 enables a system to have the following capabilities: the operator can print a complete page of displayed information or any selected row or group of rows of displayed information; it provides the capability to print an override message, such as an emergency message, without operator involvement as is also true with respect to a directed message; it permits the operator to select a special print mode wherein a row or page which he has selected will be reprinted whenever data on the selected row or page is changed with operator involvement not being required after initial selection of the mode, this operation being activated by a one time per update special character on the updated row; and special messages such as override messages can be emphasized by using extra line feeds between rows.

Lastly, referring now to FIGS. 29 and 30, with FIG. 30 being a modification to a portion of FIG. 13, a preferred circuit 9000 for providing a row-by-row determination of 64 character or 32 character display of a row in the system of the present invention shall be described. This circuit 9000 may be omitted without departing from the spirit and scope of the present invention if such row-by-row determination of 64 or 32 character display is not desired. As shown and preferred in FIG. 29, assuming such a 64 or 32 character row-by-row determination is desired, the display screen for the display device 2013 is preferably considered as comprising two half screen widths with the left hand half of the screen preferably displaying even rows which are rows 0 through 62, and with the right hand half of the screen preferably displaying odd rows, which are rows 1 through 63. It should be noted that during normal display as previously described, a row is defined as being contained in the full screen width; however, in the instance of a row-by-row determination of 64 or 32 character display, it is preferable to consider half of the screen as comprising a row with each row in this instance comprising half a message for the pseudo video scan line. Preferably, in determining whether to provide a 32 or 64 character display for a given row, if 32 characters are contained in the even row, that is rows 0, 2, 4, 6, etc., up to row 62, then only the even rows is displayed for the full screen width irrespective of the presence of an odd row in memory. If, however, there are 64 characters contained in the even row, then both the odd and the even row are displayed. In the preferred circuit arrangement 9000, no weight is given to the presence of a 64 or 32 character bit in the odd row, only the presence of this bit in the even row being considered. As will further be explained in greater detail, the control of the clock rate determines whether a 32 character or 64 character row is displayed, the memory being read twice as fast for display of a 64 character row as for a normal 32 character row, although the write speed for both a 32 and a 64 character row is the same because of the same speed of transmission in the preferred system of the present invention which receives row-by-row or pseudo video scan line-by-pseudo video scan line. In the system described in our previous U.S. Pat. No. 3,889,054, the 32 or 64 character determination was based on a page-by-page basis and of each row had to have a 32 character or 64 character bit according to the page sent or the display screen would flash between 32 character and a 64 character display effecting the readability of the display. As shown and preferred in FIG. 30, the memory 1030 through 1042 preferably includes another memory stage 2000 for the purposes of determining whether the row is to be a 64 or 32 character row display, memory 2000 only looking at the row position and not at the character position. Preferably, the even row message which is contained in row 0, 2, etc., through row 62, includes the 64/32 character bit. When the characters are loaded into memory 1030 through 1042 for the even row, from shift register 466 (FIG. 13), a decoder latch 2002 preferably decodes the 64/32 character bit which is then loaded or written into memory stage 2000. The row position in memory stage 2000 is determined by row latch 470 through multiplexer 1020. The character position of memory stage 2000 is preferably ignored. On read out, the 64/32 character bit from memory stage 2000 is then preferably read into multiplexer 2004 which then makes a switch connection to gate 1090 (FIG. 14) via path 2004a (FIG. 14) and to divide-by-eight counter 1080 via path 1079 (FIG. 14) to double the clock frequency of the prime clock to provide for the 64 character row by proper timing. For a 32 character row, multiplexer switch 2004 is left in the normal position with no output being provided via 2004a and 1079 which, as shown in FIG. 14, are in the 32 character position, so that only the prime clock non-doubled output is provided for 32 character row timing.

Now describing the adjacent odd row message gating although, if desired, the odd row gating can be omitted if the odd row is not transmitted with a 32/64 character bit. Furthermore, the 32/64 character bit in the odd row message can be discarded in other conventional ways than to be described hereinafter if desired. As shown and preferred, when the odd bit of row latch 470 through multiplexer 1020 is on, indicating the presence of an odd row, which information is provided via path 2006a to a two input NAND gate 2006, and the system is loading or writing into memory 1030 through 1042 and stage 2000, as indicated by the presence of a write signal via path 2006b to gate 2006, the memory location for the odd row in memory stage 2000 is preferably changed to an unused memory location and the output of memory stage 2000 to multiplexer switch 2004 remains the same as for the previous even row message in that line. The ignoring of the first bit in the digital output of multiplexer 1020 (FIG. 13) will always provide the even row input to memory stage 2000. This is accomplished by preferably grounding the first bit row input to memory stage 2000 from multiplexer 1020. In order to ignore the 64/32 character bit when reading the odd row, then when writing the odd row, the 32/64 character bit is referably put in an unused location by enabling this unused location in memory stage 2000 through gate 2006 whose input is the first bit position from row latch register 470, which is always preferably a 1 for the odd numbers and a 0 for the even numbers. Therefore, gate 2006 is enabled only when the input provided via path 2006a is a 1 and the write mode, also indicated by a 1, is provided via 2006b or, in other words, only for an odd row.

Lastly, discussing erase of memory stage 2000, when the normal erase is provided to the memory 1030 through 1042, preferably a common space character is put in all positions of the memory. When the 64 character row is erased, in order to insure that this row remains a 64 character row or, similarly, for a 32 character row, in order to insure it remains a 32 character row, in erasing the memory location in memory stage 2000 this memory location is positioned to an unused location without erasing the previously loaded memory bit 2010 from memory stage 2000, the erase signal via path 2008 together with the row input determining the location in memory 2000.

It should be noted that the description of the balance of the circuitry disclosed herein relating to the row grabbing system 10 which is common to our previous U.S. Pat. No. 3,889,054, and which has not been repeated herein, is specifically incorporated by reference herein and the identical reference numerals therefor are utilized herein for clarity. Furthermore, any other disclosed circuitry not specifically described in detail herein is conventional and readily understandable by one of ordinary skill in the art without further explanation and, accordingly, will not be described in further detail. In addition, it is to be understood that all logic described herein is conventional unless otherwise specified.

By utilizing the improved row grabbing system of the present invention in which grabbed frames may be updated on a row-to-row basis, conventional television transmission techniques and distribution equipment can be utilized for transmission and reception of data which has been packed into pseudo video scan lines which look like a conventional TV scan line to television equipment but contain a complete packet of information suitable for display of an entire row of video information with enhanced noise immunity to any jitter or noise present on each received pseudo video scan line being processed as well as clock phase correction for the receiver terminal on every data transition of the received pseudo video scan line whereby the received information will be essentially noise insensitive.

It is to be understood that the above described embodiments of the invention are merely illustrative of the principles thereof and that numerous modifications and embodiments of the invention may be derived within the spirit and scope thereof.

Claims

1. A real time frame grabbing system for substantially instantaneously providing a continuous video display of a selectable predetermined video frame of information on a video display means from continuously transmittable video information comprising means for transmitting said video information as a plurality of pseudo video scan lines, each of said pseudo video scan lines having a television video scan line format and capable of comprising a complete self-contained packet of digital information sufficient to provide an entire displayable row of video data characters, said pseudo video scan line having an associated transmission time equivalent to said television video scanline, said packet of digital information comprising at least address information for said displayable row and data information for said displayable characters in said displayable row, each of said pseudo video scan lines further comprising a horizontal sync signal at the beginning thereof and a start bit pulse between said horizontal sync signal and said packet of digital information, said horizontal sync signal providing a record separator between adjacent psuedo video scan lines, said transmitting means further comprising means for providing a vertical sync signal signal after a predetermined plurality of pseudo video scan lines have been transmitted, said pseudo video scan line being a composite video signal, said system further comprising television signal distribution means for distributing said transmitted composite pseudo video scan line signals to said video display means for providing said continuous video display and receiver means operatively connected between said television signal distribution means and said video display means for processing said distributed composite pseudo video scan line signals and capable of providing a displayable video row signal to said video display means from each of said pseudo video scan line signals pertaining to said selected frame for providing said containing continuous video display, a predetermined plurality of displayable video rows comprising a displayable video frame of information, said start bit pulse providing a unique synchronizing pulse for each transmitted pseudo video scan line for enabling precise determination of a sampling time for the received distributed pseudo video scan line to enable accurate determination of the binary state of the bits comprising said digital information packet, said receiver signal processing means comprising means responsive to the occurrence of said bit and said horizontal sync signal for each distributed pseudo video scan line for providing a reset signal for resetting said processing means in response to detection of said start bit for enhancing immunity of said system to any noise or jitter present in said horizontal sync signal, whereby noise immunity and accurate signal information detection are enhanced.

2. A real time frame grabbing system in accordance with claim 1 wherein said processing means start bit responsive means comprise means responsive to the occurrence of said horizontal sync signal and said start bit for each distributed pseudo video scan line comprises means for delaying said horizontal sync signal a predetermined time inverval determined by the occurrence of the trailing edge of said horizontal sync signal and the leading edge of said start bit, said delayed horizontal sync signal comprising said reset signal, whereby immunity of said system to any noise or jitter present in said horizontal sync signal is enhanced.

3. A real time frame grabbing system in accordance with claim 1 wherein said receiver signal processing means comprises means for providing a master clock signal output in accordance with said start bit pulse, and decoder means operatively connected to said master clock signal output for providing timing control signals for said receiver signal processing means indicative of predetermined character positions within said pseudo video scan line signal and predetermined bit positions with a character for processing said distributed pseudo video scan line to provide said displayable video row signal therefrom.

4. A real time frame grabbing system in accordance with claim 1 wherein said receiver means comprises means for updating said continuously video displayable selectable frame on a displayable video row-by-row basis dependent on the real time data information content of said received pseudo video scan lines.

5. A real time frame grabbing system in accordance with claim 4 wherein said updating means comprises memory means for retrievably storing said continuously distributed pseudo video scan line data portion for providing said displayable video row therefrom, said memory means retrievably stored data portion being continuously updateable as said data portion of said pseudo video scan line signal associated therewith is updated.

6. A real time frame grabbing system in accordance with claim 1 wherein said composite pseudo video scan line signal provided by said transmitting means comprises a three level signal having first, second and third signal levels with said digital data information and said start bit pulse varying between said second and third signal levels, and said horizontal sync signal information being provided between said first and second signal levels.

7. A real time frame grabbing system in accordance with claim 1 wherein each of said packets of digital information further cmprises an error check information content based on said data information content for said displayable characters of an associated pseudo video scan line, said receiver signal processing means comprising error check means for obtaining an error check indication from said distributed associated pseudo video scan line and comparing said error check indication with said error check information content of said associated pseudo video scan line in accordance with a predetermined error check condition for providing a predetermined output condition signal when said error check condition is satisfied, said receiver signal processing means further comprising condition responsive means operatively connected to said error check means to receive said predetermined output condition signal therefrom when provided, said condition responsive means inhibiting the provision of said displayable video row from said associated pseudo video scan line signal when said predetermined output cooling signal is not provided thereto.

8. A real time frame grabbing system in accordance with claim 7 wherein said error check means comprises means for serially adding said displayable characters on a word-by-word basis for providing said error check condition.

9. A real time frame grabbing system in accordance with claim 7 wherein said receiver means comprises programmable microprocessor means for controlling the operation thereof, said microprocessor means comprising means for testing said address information portion of said distributed pseudo video scan line signal for satisfaction of at least one predetermined signal reception condition, said microprocessor means providing a predetermined output condition when said reception condition is satisfied; said microprocessor means further comprising memory means for retrievably storing said pseudo video scan line data portion for providing said displayable video row therefrom, delay means for delaying the storing of said distributed pseudo video scan line signal data portion for a sufficient interval to enable testing for said error check condition and testing of said address information prior to storing of said pseudo video scan line data portion and said condition responsive means, said condition responsive means being further operatively connected to said address information testing means for inhibiting the storage of said data portion in said memory means when said predetermined output condition signals from said testing means are not provided thereto, whereby the provision of said displayable video tow from said associated pseudo video scan line signal is inhibited.

10. A real time frame grabbing system in accordance with claim 9 wherein said receiver means further comprises keyboard means operatively connected to said microprocessor means for selecting said predetermined video frame to be continuously displayed said address information comprising information corresponding to the frame associated with said distributed pseudo video scan line, said address information testing means comprising means for testing said frame information, said reception condition being correspondence between said frame information and said selected frame.

11. A real time frame grabbing system in accordance with claim 9 wherein a predetermined pseudo video scan line signal contains permission information representative of predetermined frames which a video display means is authorized to receive for video display thereof, said receiver means comprising means for storing said authorized frames, said address information comprising information corresponding to the frame associated with said distributed pseudo video scan line, said address information testing means comprising means for testing said frame information, said reception condition being correspondence between said frame information and stored authorized frame.

12. A real time frame grabbing system in accordance with claim 1 wherein said system further comprises programmable means for receiving said continuously transmittable video information, retrievably storing said information, reformatting said stored information into a desired psuedo video scan line format and continuously providing this reformatted information to said transmitting means a word at a time, said word comprising a pair of displayable characters.

13. A real time frame grabbing system in accordance with claim 12 wherein said programmable means includes means for interleaving said reformatted pseudo video scan line information to provide pseudo video scan line information corresponding to a common assigned row for a plurality of frames to said transmitting means before providing pseudo video scan line information corresponding to a subsequent different common assigned row for said plurality of frames to said transmitting means.

14. A real time frame grabbing system in accordance with claim 3 wherein said processing means further comprises means responsive to each transition in said digital data content of each pseudo video scan line for continuously correcting the phase of said master clock signal.

15. A real time frame grabbing system for substantially instantaneously providing a continuous video display of a selectable predetermined video frame of information on a video display means from a plurality of pseudo video scan lines, each of said pseudo video scan lines having a television video scan line format and capable of comprising a complete self-contained packet of digital information sufficient to provide an entire displayable row of video data characters, said pseudo video scan line having an associated transmission time equivalent to said televison video scan line, said packet of digital information comprising at least address information for said displayable row and data information for said displayable characters in said displayable row, each of said pseudo video scan lines further comprising a horizontal sync signal at the beginning thereof and a start bit pulse between said horizontal sync signal and said packet of digital information, said horizontal sync signal providing a record separator between adjacent pseudo video scan lines, said pseudo video scan line being a composite video signal, said system comprising means for selecting said predetermined video frame to be continuously displayed and means operatively connected to said video display means and said frame selection means for processing said composite pseudo video scan line signals and capable of providing a displayable video row signal to said video display means from each of said pseudo video scan line signals pertaining to said selected frame for providing said continuous video display, a predetermined plurality of displayable video rows comprising a displayable video frame of information,+ said start bit pulse providing a unique synchronization pulse for each pseudo video scan line for enabling precise determination of a sampling time for each pseudo video scan line to enable accurate determination of the binary state of the bits comprising said digital information packet, said processing means comprising means responsive to the occurrence of said start bit and said horizontal sync signal for each pseudo video scan line for providing a reset signal for resetting said processing means in response to detection of said start bit for enhancing immunity of said system to any noise or jitter present in said horizontal sync signal, whereby noise immunity and accurate signal information detection are enhanced.

16. A real time frame grabbing system in accordance with claim 15 wherein said processing means start bit responsive means comprises means responsive to the occurrence of said horizontal sync signal and said start bit for each pseudo video scan line comprises means for delaying said horizontal sync signal a predetermined time interval determined by the occurrence of the trailing edge of said horizontal sync signal and the leading edge of said start bit, said delayed horizontal sync signal comprising said reset signal, whereby immunity of said system to any noise or jitter present in the said horizontal sync signal is enhanced.

17. A real time frame grabbing system in accordance with claim 15 wherein said processing means comprises means for providing a master clock signal output in accordance with said start bit pulse, and decoder means operatively connected to said master clock signal output for providing timing control signals for said processing means indicative of predetermined character position within said pseudo video scan line signal and predetermined bit positions within a character for processing said pseudo video scan line to provide said displayable video row signal therefrom.

18. A real time frame grabbing system in accordance with claim 15 wherein said processing means comprises means for updating said continuously video displayable selectable frame on a displayable video row-by-row basis dependent on the real time data information content of said video scan lines.

19. A real time frame grabbing system in accordance with claim 18 wherein said updating means comprises memory means for retrievably storing said pseudo video scan line data portion for providing said displaying video row therefrom, said memory means retrievably stored data portion being continuously updateable as said data portion of said pseudo video scan line signal associated therewith is updated.

20. A real time frame grabbing system in accordance with claim 15 wherein each of said packets of digital information further comprises an error clock information content based on said data information content for said displayable characters of an associated pseudo video scan line, said processing means comprising error check means for obtaining an error check indication from said associated pseudo video scan line and comparing said error check indication with said error check information content of said associated pseudo video scan line in accordance with a predetermined error check condition for providing a predetermined output condition signal when said error check condition is satisified, said processing means further comprising condition responsive means operatively connected to said error check means to receive said predetermined output condition signal therefrom when provided, said condition responsive means inhibiting the provision of said displayable video row from said associated pseudo video scan line signal when said predetermined output condition signal is not provided thereto.

21. A real time frame grabbing system in accordance with claim 20 wherein said error check means comprises means for serially adding said displayable characters on a word-by-word basis for providing said error check condition.

22. A real time frame grabbing system in accordance with claim 20 wherein said processing means comprises programmable microprocessor means for controlling the operation thereof, said microprocessor means comprising means for testing said address information portion of said pseudo video scan line signal for satisfaction of at least one predetermined signal reception condition, said microprocessor means providing a predetermined output condition when said reception condition is satisfied; said microprocessor means further comprising memory means for retrievably storing said pseudo video scan line data portion for providing said displayable video row therefrom, delay means for delaying the storing of said pseudo video scan line signal data portion for a sufficient interval to enable testing for said error check condition and testing of said address information prior to storing of said pseudo video scan line data portion and said condition responsive means, said condition responsive means being further operatively connected to said address information testing means for inhibiting the storage of said data portion in said memory means when said predetermined output condition signals from said testing means are not provided thereto, whereby the provision of said displayable video row from said associated pseudo video scan line signal is inhibited.

23. A real time frame grabbing system in accordance with claim 22 wherein said processing means further comprises keyboard means operatively connected to said microprocessor means for selecting said predetermined video frame to be continuously displayed, said address information comprising information corresponding to the frame associated with said pseudo video scan line, said address information testing means comprising means for testing said frame information, said reception condition being correspondence between said frame information and said selected frame.

24. A real time frame grabbing system in accordance with claim 22 wherein a predetermined pseudo video scan line signal contains permission information representative of predetermined frames which a video display means is authorized to receive for video display thereof, said processing meeans comprising means for storing said authorized frames, said address information comprising information corresponding to the frame associated with said pseudo video scan line, said address information testing means comprising means for testing said frame information, said reception conditions being correspondence between said frame information and stored authorized frame.

25. A real time frame grabbing system in accordance with claim 17 wherein said processing means further comprises means responsive to each transition in said digital data content of each pseudo video scan line for continuously correcting the phase of said master clock signal.

26. A real time frame grabbing system in accordance with claim 12 wherein said programmable means comprises means for continuously providing said reformatted information to said transmitting means a word at a time, said word comprising a pair of displayable characters. 27. A real time frame grabbing system in accordance with claim 1 wherein said receiver means comprises means for updating said continuously video displayable selectable frame on a displayable video row-by-row basis as said data portion of any of said displayable distributed pseudo video scan line signals pertaining to said selected frame is updated. 28. A real time frame grabbing system in accordance with claim 15 wherein said receiver means comprises means for updating said continuously video displayable selectable frame on a displayable video row-by-row basis as said data portion of any of said displayable distributed pseudo video scan line signals pertaining to said selected frame is updated. 29. A real time frame grabbing system in accordance with claim 1 wherein said receiver means comprises means for providing a displayable frame of information to said video display means from a predetermined plurality of displayable video rows. 30. A real time frame grabbing system in accordance with claim 15 wherein said processing means comprises means for providing a displayable frame of information to said video display means from a predetermined plurality of displayable video rows. 31. A real time frame grabbing system in accordance with claim 1 wherein said start bit pulse comprises a single bit pulse. 32. A real time frame grabbing system in accordance with claim 31 wherein said receiver signal processing means comprises means for providing a master clock signal output in accordance with said start bit pulse, and decoder means operatively connected to said master clock signal output for providing timing control signals for said receiver signal processing means indicative of predetermined character positions within said pseudo video scan line signal and predetermined bit positions within a character for processing said distributed pseudo video scan line to provide said displayable video row signal therefrom. 33. A real time frame grabbing system in accordance with claim 32 wherein said processing means further comprises means responsive to each transition in said digital data content of each pseudo video scan line for continuously correcting the phase of said master clock signal.