Computer responsive postage meter

Abstract

A high volume mailing installation is disclosed in which the output of a programmable high speed electronic digital computer provides destination and postage amount information, a high speed chain printer driven by the computer prints the destination information on address labels, and an authorized postage printing meter is mounted piggy-back fashion on the chain printer and responds to the same computer for automatic printing of authorized postage impressions of the calculated amount on the same mailing labels. The meter includes a fast, rugged solenoid-actuated segmented flat bed postage printer unit and fixed-program electronic digital postal accounting circuitry, with appropriate security features to prevent or detect postal fraud.

Description

RELATED APPLICATIONS

This application is a continuation-in-part of the previously filed parent application Ser. No. 195,694 now abandoned.

FIELD OF THE INVENTION

This invention relates generally to postage metering, and particularly concerns secured electronic calculating and postage printing equipment for achieving postage metering security in a computer-controlled high volume mailing operation.

BACKGROUND AND SUMMARY OF THE INVENTION

It is conventional for high volume mailers to avail themselves of the high speeds offered by modern electronic digital computers and chain printers, in order to reduce costs and increase their output. A typical prior art installation includes a computer which receives information as to the weight and destination of a package, and is programmed to calculate the required postage. A high speed computer output printer is slaved to the computer to print out the destination information on an address label which is subsequently affixed to the package.

The computer also provides the calculated postage amount information to shipping department employees in some form which enables them to affix the proper amount of postage to the package. The most common way of accomplishing this is for the high speed printer to receive the postage amount information from the computer, and print it directly on the address label for the information of the employees who subsequently affix postage. This printing is not an actual government-authorized postage impression of the kind provided by a postage meter. The print impression made in a prior art installation as described above includes only the postage amount without any authorized postage validation symbols, and is provided for information only. Thereafter authorized postage of like amount must be affixed by an employee by affixing postage stamps or using a conventional manually controlled mechanical postage meter.

The intervention of a human being, or of a mechanical postage metering device, slows down a high volume mailing operation of the kind described. Therefore it is desirable to have the authorized postage impression printed automatically in response to the computer-generated postage calculation. It is not enough, however, simply to connect the data output lines of the computer to the input of some insecurely housed apparatus capable of printing authorized postage impressions, as suggested by U.S. Pat. No. 3,225,439 of L. G. Simjian. In accordance with applicable postal security regulations, there must be some secure means of accounting which assures postal officials that all the postage used is paid for. Normally a descending register is filled with a pre-paid postage credit balance, the register is decremented by the amount of postage dispensed, and the postage dispenser is locked when the postage balance falls too low. Subsequently the register can be recharged under secured conditions. It is also possible to extend postage credit to the user, keeping track of a debit balance which increases by the amount of the postage used, and billing the user subsequently. Those skilled in the computer arts will readily appreciate that it is possible to program the computer itself to take care of either type of bookkeeping described above. Such a solution is unsatisfactory, however, because digital computers are so easily re-programmed that an unscrupulous individual could thereby accomplish postal fraud.

This invention contemplates, therefore, that the desired computer control of postage printing be achieved in conjunction with some form of secure, fixed-program postal accounting equipment. One approach which is within the contemplation of this invention is to use a mechanical postage meter which comprises a secure housing containing authorized postage printing means, a mechanical descending register for storing the postal credit balance, and mechanical solenoidactuated 807 of the computer status register 800. That register in turn sends a printer signal to the control logic 842 over a lead 866. The control logic then issues an enter postage command over a lead 868 which causes the variable print modules 528 to be set to number positions representing the postage amount then contained in the print buffer 804. A data feedback line 870 carries back a signal from the variable modules 528 to convey print module status information to an interrupt and status indications section 872 of the meter status register 802, so that the computer will know when the print wheels 526 are properly set. If they are not properly set, that fact is reported back to the computer by the meter status register 802 and interface hardware 798. As a result, the computer does not issue a print command until the problem is resolved. But if the computer receives an indication that the variable print modules 528 are set to the proper numerical values, then it issues a print command which is transmitted through the interface hardware 798 and the command section 807 of the computer status register 800, and then over lead 874 to the first priority section of the polling circuit 838.

The polling circuit enters the first priority printing mode, and sends a print mode command over the lead 840 to the control logic 842, which then issues print instructions over a lead 876. If a NAND gate 878 is not disabled, the print command passes through the gate and traverses leads 879 and 881 to the selenoid sequencing circuit 805. The latter then fires the solenoid 801 to unlock the print segments 500, and also fires the print solenoids 238 or 338 in sequential relationship (for a disclosure of the sequencing circuit 805, refer to the Lupkas, et al application cited above). The signal on lead 879 is also conveyed over lead 880 to the arithmetic unit 816 and causes it to perform a subtraction operation deducting the amount of postage from the descending register balance.

In order to perform this operation, the arithmetic unit buffers 818 receive the postage amount information over a cable 882 from the print buffer, and they also receive the contents of the descending register 810 over a memory fetch cable 884. The necessary memory addressing operation to access the descending register is carried out by the memory address decoder 814 in response to address information received over a cable 886 via a data gate 905 and counter 828. The control logic circuit enables the gate 905 and arithmetic unit 816 by means of leads 904 and 894, respectively.

The arithmetic unit 816 carries out its calculation and reloads the decremented postage balance back into the descending register section 810 of the memory 806 over a cable 895. Once again, the memory address decoder 814 performs the addressing function during loading, responding to the address information on the cable 886, while control signals arrive over leads 904 and 894 from control logic 842.

In similar fashion, the amount of postage is added to the ascending register 808. The piece counter 812 is incremented each time the "enter postage" mode is initiated.

Summarizing the printing operation, the computer command for setting the variable number wheels goes directly over lead 866 to the control logic 842, so that the setting function is carried out off-line with respect to the polling circuit 838. Then there is a feedback output over lead 870 to the computer to verify correct number wheel setting. Subsequently a print command goes over lead 874 to the polling circuit 838. When there is no higher priority operating mode requested, the print mode is entered and the control logic 842 issues a command which simultaneously fires the print solenoids 238 or 338, initiates the postage subtraction operation of arithmetic unit 816, increments the piece counter 812 and adds the postage amount to the ascending register.

These operations cannot be carried out, however, unless the insufficient postage decoder 820 detects an adequate postage balance remaining in the descending register 810, and therefore enables the NAND gate 878. If the postal credit balance is insufficient, the output from the decoder 820 inhibits the NAND gate 878. As a result, the print solenoids are not fired, the postage balance is not decremented, the ascending register is not incremented and the piece counter is not incremented. In addition, the decoder output goes over a lead 896 to turn on the insufficient postage panel indicator light, and goes over a lead 898 to convey an insufficient postage indication back to the interrupt and status indication section 872 of the meter status register 802. The computer programmer can then use this indication to initiate any desired program routine.

In a preferred embodiment of the postage printer, the print segments 500.1-500.8 are normally locked, for additional postage security, by the locking mechanism controlled by solenoid 801. The latter is unlocked only at the time that postage printing is initiated, and then locked again after printing. The switches 803 serve to sense the locked and unlocked condition of the lock mechanism, and also sense when print segments 500.1-500.8 respectively advance to print impact position upon energization of the print solenoids 238 or 338. For a complete disclosure of the locking mechanism, the solenoid 801 and the switches 803, refer to the Lupkas, et al application cited hereinbefore.

When the print mechanism is unlocked by solenoid 801, switches 803 issue a signal on a lead 940 to set a lock mechanism flip-flop 942. The set output of that flip-flop then resets each one of a group of print segment flip-flops 944.1-944.8, associated with the print segments 500.1-500.8 respectively. Then the print segment flip-flops 944 wait to detect the movement of the print segments 500 to their print impact positions. At each print segment 500 advances to print impact position, a respective lead 946.1-946.8 is energized by the associated print confirmation switch 803 to set the associated print segment flipflop 944. All the set outputs of these flip-flops 944 lead to an eight-input NAND gate 948. The output of the NAND gate passes through a delay circuit 950 and is controlled by a coincidence gate 952 952A. After printing the solenoid 801 is de-energized, and thus the locking mechanism is relocked, causing one of the sensing switches 803 to issue another signal on a lead 952 which resets the flip-flop 942. The reset output of that flip-flop then enables coincidence gate 952 952A

Upon the enabling of gate 952 952A, the print confirmation circuit 711 can determine whether all the print segments 500.1-500.8 were successfully driven to print impact position during the preceding print operation. If all the print segments 500 have been driven to print impact position, the print confirmation switches 803 will have set all the flip-flops 944, and there will be no output from the NAND gate 948. Accordingly there will be no output from the print confirmation circuit 711 on its print segment status output lead 954. On the other hand, if any one or more of the print segments 500 fail to advance to print impact position, the corresponding flip-flops 944 will not be set. Consequently there will be an output from the NAND gate 948. This output, delayed by circuit 950, will pass through coincidence gate 952 952A when the latter is enabled at the end of the print operation, resulting in an output on lead 954 by which the print confirmation circuit 711 advises the interrupt and status indication section 872 of the meter status register 802 that postage printing has not been successfully carried out as ordered by the computer. The computer can then carry out any appropriate alarm subroutine dictated by the programmer.

The next higher priority operating mode of the polling circuit 838 is the addition of funds to recharge the descending register 810 when an insufficient postage condition occurs. In order to avoid the need for carrying the postage printing mechanism and the accounting circuitry to a Post Office for recharging recharging contemplates the use of the selfscrambling combination lock switch 860. Such locks were previously developed for remote recharging of conventional postage meters. A mechanical combination lock of this type, which employs mutilated gears for scrambling, is disclosed in U.S. Pat. No. 3,034,329 of R. C. Pitney, and is suitable for use in the switch 860 of this circuit. As a preferable alternative, however, one might employ a keyboard-operated self-scrambling combination lock device as described in U.S. Pat. No. 3,664,231 issued May 23, 1972 by Walter J. Hanson, and assigned to the same assignee as the present application. Briefly, the Hanson device matches a hole pattern punched in a movable tape with a keyboardentered keyboard-entered combination. If the combination is correct, the lock is released once, permitting the switch 860 to operate one time. Thereafter the tape is advanced to a new position, and consequently the switch cannot be operated without obtaining the next lock combination from postal officials.

The result of each lock opening operation is to close the combination switch 860, sending a signal over a lead 900 to the second priority section of the polling circuit 838. This causes an add funds mode signal to be transmitted to the control logic 842 over the lead 840. An add funds signal is then transmitted from the control logic 842 over a lead 902 to the arithmetic unit 816. The effect of that signal is to cause a predetermined increment of postage, equal in amount to the payment made to the postal authorities in order to obtain the lock combination, to be added to the descending register balance. The descending register portion 810 of the memory 806 is accessed and then reloaded with the new postage balance by the memory address decoder 814 in response to an addressing control signal arriving over a lead 904 from the control logic 842. The addressing control signal enables gate 905 during the memory addressing count sequence of circuit 828.

The third priority operating mode of the polling circuit 838 is the reading out of information into the panel display 610. This operating mode is entered in response to one of the manually operated panel switches 612-618, which determine whether the display is to show the contents of the ascending register, descending register or piece counter sections of the memory 806, or to light up a test display which energizes all read-out elements. Any of these switches generates a signal (represented by arrow 619) which causes the polling circuit 838 to enter mode No. 1 No. 3. The switch 620 cancels the read-out operating mode entirely.

In response to a read-out mode signal on the lead 840 coming from the polling circuit 838, the control logic 842 sends a signal over address control lead 904 which enables gate 905 during the memory addressing count sequence. Memory contents are sequentially read out on cable 884. The signal on lead 906 from the control logic 842 strobes the selected information into the read-out 610.

The preferred form of display for this circuit is a lightemitting diode array with built-in integrated circuit decoding logic 854.

The computer can also access the memory contents at will, and fetch data therefrom to use for any purpose that the programmer desires. In order to accomplish this, the computer inserts the desired memory address into the data section 862, and also sends a memory reading instruction to command section 807 of the computer status register 800, which in turn sends a read memory signal over a lead 912 directly to the control logic 842, bypassing the polling circuit 838. The control logic 842 in turn sends a signal over the lead 892 to enable the data gate 888, admitting the computer-generated memory address arriving over cable 889 to the memory address decoder 814. This results in fetching the requested ascending register, descending register, or piece counter data from the memory 806 over cable 884, and inserting it into a data portion 914 of the meter status register 802. Then a computer can obtain the desired information from the meter status register.

There is a possibility of arithmetic error if postage computations are performed when the logic voltage levels supplied by the main power supply circuits 856 are not within tolerance. In order to make sure that all arithmetic computations take place under proper voltage conditions, and thus avoid postal accounting errors, the start-up program section 846 of the initialization circuit 844 does not turn on until it gets a signal over a lead 915 from the voltage sensor circuit 858 indicating that all logic levels are within tolerance. The initialization circuit 844 produces a start signal on a lead 916 which turns on the memory address decoder 814 and also makes sure that the gate controlling flip-flop 834 is initially reset.

In the event of a power failure, low voltage condition or shut-down of the meter, the voltage sensor 858 indicates a power-off situation to the shut-down program section 848 of the initialization circuit 844. At that time, the initialization circuit sends a stop signal on a lead 918 to a NAND gate 920. The NAND gate inhibits the stop signal if the polling circuit 838 signals over a lead 922 that an arithmetic calculation is currently in progress; i.e. the meter is in mode No. 1 or 2. Under those circumstances, calculation is allowed to proceed to completion. The power supplies 856 are designed with enough capacitance to allow operation at proper voltage levels for sufficient time to complete any arithmetic operation that may be in progress, even after total power failure. But after the present calculation is concluded, the polling circuit 838 and lead 922 cause NAND gate 920 to pass the stop signal out over line 921 in order to turn off the memory address decoder 814 and thereby preserve the memory contents unchanged for the duration of the power failure or other abnormal condition.

An additional lead 924 coming from the voltage sensor 858 lights up the meter-ready panel indicator light 606 when the logic voltages come up to required levels, and another lead 926 conveys the same meter-ready indication to the interrupt and status indication section 872 of the meter status register 802, thus advising the computer that the electronic postage meter is in condition for operation. When the voltage sensor circuit 858 senses a low voltage condition, the meter-ready-panel light 606 goes out and the meter-ready status indication in register 802 turns off, advising both the human operator and the computer of the problem.

The operation of this postage system will be further described with reference to FIGS. 14 through 34. FIG. 14 shows the sequence of operation of the system including a plot of the clock 824, the gray code counter 826, and the polling signals with respect to time. The clock 824 as used in this inventive system is a standard module (Model M401-0-1, Digital Equipment Corporation, Maynard, Mass.) set to operate at a 4 MHz rate as shown in FIG. 14a. The electrical logic elements illustrated in the drawings are 7400 series TTL (transistor-transistor logic) components, such as are available from Texas Instruments, Inc., unless otherwise indicated herein. The internal control of the metering system is governed by the clock frequency, which is divided into eight timing periods (FIG. 14g) for each machine cycle, by the 3-bit binary Gray Code Counter 826 of FIG. 17. This free-running gray code counter 826 comprises 3 "J-K" flip-flops 1000, 1001 and 1002, respectively, providing outputs A', A'; B', B'; and C', C' through buffers 1004, 1005; 1006, 1007; and 1008, , 1009 respectively. The gray code counter outputs A', B', C', respectively (FIG. 14d, 14e and 14f, respectively), are repetitive every eight periods so as to establish a machine cycle (FIG. 14g). The flip-flops 1000, 1001 and 1002, change state one at a time. This has the advantage that the output is certain, and there is no no timing (race condition) problem between the outputs. In other words, questionable outputs cannot occur because one output may be generated slightly out of phase with another output. These "clean pulses" are used for controlling the system, for gating purposes and polling.

The gray code counter is used to drive a memory addressing counter 828 as shown in FIG. 17. The memory addressing counter is a 5-bit synchronous counter comprising 5 "J-K" flip-flops 1010, 1011, 1012, 1013 and 1014 wired as shown, and providing outputs A, A; B, B;, C, C;, D, D; and E, E; respectively, Outputs A, B, C, D, and E are plotted in FIG. 15 with respect to time. The outputs A, B, C, D, and E are used to form 32 addresses as shown in FIG. 16. The synchronous counter counts in a straight binary sequence generating these addresses, but these addresses could also be supplied directly by the computer controlling the meter.

The memory addressing lines are enabled through period 2 through 7. The memory addressing counter changes between periods 8 through 1, so that the addressing lines are enable only when no addressing changes are taking place. As indicated on FIG. 15, there must be at least one machine cycle before the address enable signal becomes high again. This allows a polling sequence to take place which then provides the highest priority mode awaiting service to be entered.

The meter cycle is generated by any of three controls (1) Enter postage, (2) Add funds, and (3) Cycle. These modes are sequentially checked by the polling circuitry 838 shown in FIG. 18. The polling circuit 838 is dependent upon the clock pulses for determining the polling sequence. The "enter postage" mode circuitry has the highest priority and is fed clock pulse 2 over line 1040; the "Enter funds" mode is fed pulse 4 over line 1041; and the "cycle" mode has the lowest priority, because this mode is generally only for the purposes of readout (accessing the contents of the memory for display purposes). The cycle mode circuitry is fed clock pulse 6 over line 1042. (See FIG. 14h).

The three flip-flops 1015, 1016 and 1017, respectively provide a signal to the control logic 842 over lines 1018, 1019 and 1020, respectively. These lines, for the sake of convenience, are represented by line 840 in FIG. 13. Flip-flops 1015, 1016 and 1017 are mutually exclusive. When one of these flip-flops goes "high" it disables the other two flip-flops by feeding a complementary signal back through the AND-gates 1021, 1022 or 1023 respectively, as the case may be. The AND-gates 1201, 1022 and 1023 feed their respective flip-flops 1015, 1016 and 1017. These AND-gates receive the signal from NOR-gate 1025, which feeds line 1024. The NOR-gate 1025 is tapped into lines 1018, 1019 and 1020, at points 1026, 1027 and 1028, respective, as shown.

Flip-flops 1034, 1035, 1036, respectively, store externally added information, such as enter postage, operate display, enter funds, over lines 619, 874 and 900, respectively. This externally applied stored information infuences the operation of flip-flops 1015, 1016 and 1017, respectively, and may be present while any of the flip-flops 1015, 1016 and 1017 are inoperative or in a mode feeding capacity.

FIGS. 14b and 14c show the relationship of the address enable signal (FIG. 14c) to that of the polling run signal FIG. 14b). When the polling run signal goes high, (shaded portion shown in FIG. 14b) the zero count decoder 832 (FIG. 17) causes the address enable signal to go high at end of period 8.

As can be seen from FIG. 14h, the three polling modes are activated during periods 2, 4 and 6 respectively. The cycle mode is entered through initialization (when the system is turned on), and upon activating display select switches.

FIG. 19 depicts control logic gates 1029, 1030, 1031, 1032, and 1033 of the control logic circuit 842 (FIG. 13). These gates generate an output at given periods, depending upon the states of the gray code flip-flops 1000, 1001 and 1002, i.e., A' or A', B' or B'; and C' or C' (see FIGS. 14d, 14e or 14f).

Logic gate 1029 generates output pulse 2; logic gate 1030 generates output pulse 4; logic gate 1031 generates output pulse 6; logic gate 1032 generates output pulse 8; and logic gate 1033 generates output pulse 7. Output pulses for periods 1, 3 and 5 are not generated because they are not used.

The last address decoder circuit 836 is shown in FIG. 18. This circuit is fed from the memory addressing counter 828 (FIG. 17). When the last address pulse is received by this circuit, it clears flip-flop 1015 over line 1029. Flip-flops 1016 and 1017 are cleared over line 1030 from circuit 836, which feeds gate 1031. Gate 1031 clears flip-flop 1016 and 1017 over lines 1032 and 1033, respectively.

The combination lock switch circuit 860 is shown in FIG. 18, and the add funds circuit over line 900. The combination lock switch circuit 860 is a well-known debouncing circuit.

FIG. 20 depicts the memory circuit 806 of FIG. 13b. The memory consists of RCA's 16 bit COS/MOS memory chips arranged to provide 32 words 4 bits wide. The 32 memory locations are divided up into three registers; ascending register 808; descending register 810; and a piece counter 812. Each location (4 bit word) holds a binary coded decimal (see FIG. 16). The memory comprises two identical cards, each having 4 chips 1037, 1038, 1039 and 1040, respectively. In selecting an address, 1 bit is accessed in each of the four chips 1037, 1038, 1039 and 1040. This allows you to store a 4 bit binary coded decimal digit.

COS/MOS was chosen for its low quiescent power, which allows for battery operation over extended periods of time. This is important because continuous power is necessary to retain the memory contents.

Other features of this memory circuit include high noise immunity and simplified interfacing, as well as the aforementioned non-critical power requirements.

FIG. 16 shows that the first (0-15) 16 locations are assigned to the ascending register 808; the next (16-23) 8 locations are reserved for the descending register 810; and the last (24-31) 8 locations belong to the piece counter 812.

FIG. 21 illustrates the circuitry for the memory address decoder 814 and memory buffer circuitry for the memory 806. The AND-gates 888 and 905 in FIG. 21 are represented as a single AND-gate in FIG. 13b for schematic purposes. The lines 885 and 887, respectively feeding these AND-gates as shown in FIG. 13b, are shown in FIG. 21 as respectively linked to the multiple gates 888 and 905.

The outputs of the gating network 1041 containing AND-gates 888 and 905 are given as AA, AA; BB, BB; CC, CC; DD, DD; and EE, EE; as shown. These outputs are fed to network 1042. The outputs of network 1042 connect to the memory chips 1037, 1038 1039 and 1040 shown in FIG. 20. The outputs of network 1042 (X₁ ; X₂ ; X₃ ; X₄ ;X₁ ; Y₂ ; Y₃ ; and Y₄) connect to the corresponding chip location.

The output gates 1043 and 1044 of network 1042, which provide outputs EE and EE, choose either the first deck of chips, or the second deck of chips in memory. In other words, these outputs correspond to the column bit "E" in FIG. 16.

Network 1045 refers to buffer circuitry which is associated with the memory 806. The outputs of the memory as shown in FIG. 20 (M₁ 2⁰ ; M₁ 2¹ ; M₁ 2² ; and M₁ 2³) are fed to circuit 1045. The second deck of chips (not shown) in the memory provide outputs (M₂ 2⁰ ; M₂ 2¹ ; M₂ 2² ; and M₂ 2³) which supply circuit 1045 as shown. The designations 2⁰ and 2³ refer to the least and most significant bits, respectively. The outputs of network 1045 are supplied to the arithmetic unit 816.

FIG. 22 shows the circuitry for the arithmetic unit 816, the buffer circuitry 818 feeding back to the memory 806 from the arithmetic unit, part of the insufficient funds circuit 820, and the add postage lock-out circuit (status indicator circuit 872).

Circuit 816 of FIG. 22 is fed by the outputs of circuit 1045 of FIG. 21 through lines 1046, 1047, 1048 and 1049, respectively. The memory outputs output fed over these lines is added to the applied signals to enter additional postage, which is fed over lines 1051, 1052, 1053 and 1054, respectively, from the postage buffer circuit 804 (FIG. 24). The postage buffer and memory outputs are fed to the binary adder 1050, where corresponding inputs (A and B) are summed. The outputs of the adder 1050 are fed to a decoder 1055 which converts the binary sums from binary to BCD.

Flip-flop 1056 and 1057 receive clocking pulses CP6 and CP8, respectively to control the proper propogation of the carry bit.

Output buffer circuitry 818 comprises four flip-flop flip-flops 1058, 1059, 1060 and 1061 respectively, which receive the BCD output from the decoder 1055, store the data, and pass it on to memory 806 over lines 895 (see FIG. 13b). Lines 895 are tapped into the insufficient funds circuit 820 over lines 1062. The "Descending Register Full" circuit of status circuitry 872 is tapped into lines 895, and is fed via line 1063. The latter circuit receives a signal which locks out of the combination lock when the descending register is full. FIG. 23 illustrates the aforementioned insufficient postage decoder circuit 820 and the Descending Register Full circuit of circuitry 872.

FIG. 23 also shows the arithmetic control circuit 1066, which supplies to clear carry and preset carry signals to the arithmetic circuit 816. The clear carry signal is carried over line 1064, and the preset carry signal is carried over line 1065, to the carry control flip-flop 1057 (FIG. 22).

FIG. 24 depicts the postage buffer circuit 804. The outputs from the print buffers of FIG. 25 are stored in a plurality of latches of postage buffer circuit 804. There are four sets of four latches as shown by arrows 1067, 1068, 1069 and 1070. Each set of four latches stores the postage amounts from $0.01 to $10.00 as shown. Each set of latches respectively feeds to a multiplexer (multiplexers 1071, 1072, 1073 and 1074, respectively). These multiplexers select one BCD digit at a time from its corresponding set of latches. These multiplexers feed to another row of multiplexers 1075, 1076, 1077 and 1078, respectively. The function of multiplexers 1075, 1076, 1077 and 1078 is to select the postage amount, the nine's complement of the postage amount, or zero. The nine's complement of the postage amount is used to effect the subtraction of the postage amount from the descending register during the enter postage mode through an addition process. The selection of the zero is, for example, to propagate carry through higher order decimal places, and to leave register contents unchanged during cycle (see FIG. 16). The outputs from the multiplexers 1075, 1076, 1077 and 1078, are respectively fed to the arithmetic circuit 816 over lines 1051, 1052, 1053 and 1054.

Multiplexers 1075, 1076, 1077 and 1078 are controlled by the inputs fed over lines 1079 and 1080 from the multiplexer control circuit 1081 of FIG. 23. Multiplexers 1075, 1076, 1077 and 1078 select the proper postage amount, nine's complement thereof, or zero for each of the three registers (ascending, descending, and piece counter) during the enter postage, add funds, and cycle modes as shown in FIG. 16. Multiplexers 1071, 1072, 1073 and 1074 are controlled by outputs A and B of the memory addressing counter 828 (FIG. 17) to select the $0.01, $0.10, $1.00 and $10.00 digits from the postage buffer circuit 804 at the same time the corresponding digits are being accessed from the ascending resister 808 and descending register 810 (FIG. 13B). The inputs fed over lines 1082 and 1083 derived from the outputs of the first two flip-flops 1010 and 1011 of the synchronous 5-bit counter 828.

The multiplexers 1075, 1076, 1077 and 1078 are fed with added funds over lines 1084, 1085, 1086 and 1087. In this case, the digit 5 is transmitted over lines 1084, 1085, 1086 and 1087 and added to the descending register in the $100's position selected by the multiplexer control logic 1081 (see FIG. 23) to give an added fund increment of $500.

FIG. 25 shows the print buffer circuitry feeding the postage buffer circuit 804. The print buffer circuit comprises four banks (only one shown here) of four D-type flip-flops 1088, 1089, 1090 and 1091, each. Each bank of four flip-flops 1088, 1089, 1090 and 1091 inputs one set of four latches in postage buffer circuit 804, over lines 1092, 1093, 1094, 1095 as shown. The signals fed over these lines are also fed to a comparator 1096 to check for BCD errors. The comparator is also fed from the 4-bit counter of FIG. 27 over lines 1097, 1098, 1099 and 1100. Flip-flops 1088, 1089, 1090 and 1091 receive BCD digit data 862 from the computer; strobe pulses for entering the data into the print buffer are generated by gates 1125, 1126, 1127 and 1128 and are outputted over lines 1101, 1102, 1103 and 1104 (FIG. 27) to print buffer (consisting of 1088, 1089, 1090 and 1091) enabling lines 1105 (FIG. 25) to enter $0.01, $0.10, $1.00, $10.00 digits respectively. As shown in FIG. 28 the BCD data is on bits 12 through 15 of the digital word.

The outputs of each bank of flip-flops 1088, 1089, 1090 and 1091 are fed to a 4-to-10 line decoder 1106, whose outputs feed a series of electrical contacts corresponding to various positions on the variable number modules 528 of FIG. 8. The decoder provides low signal on the contact corresponding to the position to be selected. These electrical contacts are sensed by a wiper arm on each module.

FIG. 26 illustrates circuits 1109 and 1110. Circuit 1110 is inputted on lines 1111, 1112, 1113 and 1114, which connect to each wiper arm (commutative brush) on the rotative elements of the variable number modules 528. When a high signal is sensed by a wiper arm, indicating a wrong wheel position, the signal is carried over the appropriate input line (1111, 1112, 1113 and 1114) to a respective gate 1115, thus enabling the gate and turning on a respective SCR 1116. Each respective SCR 1116 is connected to a driving coil of one of the variable number modules for rotating the number wheels to the proper position. When the appropriate position is reached, a low signal is detected by the wiper arm, which is subsequently fed back through one of the lines 1111, 1112, 1113 and 1114 to disable the respective gate 1115 and turn off the respective SCR 1116.

Circuit 1109 is fed from line 1166 of each comparator 1096 of FIG. 25, (only one of four circuits shown) over lines 1117, 1118, 1119 and 1120, respectively. The lines feed to a gate 1121, which checks for the Binary Coded Decimal and provides an output on line 1107. Line 1107 feeds to gate 1122 in FIG. 27 as shown. Gate 1122 and J-K flip-flop 1123 are part of the interrupt and status indicator circuitry 872.

The gate 1124 of circuit 1110 is connected to each of lines 1111, 1112, 1113 and 1114, and is used for checking whether the print wheels of the variable number modules are in the set position. The output of gate 1124 is fed over line 1108 to gate 1125 of the interrupt and status circuitry 872 as shown in FIG. 27. The outputs of flip-flops 1144 and 1123 form part of the feed back to the computer through the meter station status register (FIG. 29).

FIG. 27 depicts the print wheel logic circuitry. The print buffer to be loaded is selected by bits 10 and 11 and the digital output (FIG. 28). AND gate 1214 (FIG. 28) decode bits 10 and 11 as specifying $0.01, $0.10, $1.00, $10.00 digits and feeds the appropriate enabling signal to gates 1125-1128 (FIG. 27). A sampling pulse to gates 1125-1128 generates a strobe signal on one of the otuputs 1101-1104 which goes to the appropriate print buffer enabling lines 1105 (FIG. 25) which causes data present on the digital output 826 (FIG. 28) to be entered into the print buffer (flip-flop 1088-1091 in FIG. 25).

The print wheel logic circuit has pulse generating means (arrow 1129) to generate a 60 H_z square wave signal which operates a counter 1130 via an enabling gate 1131. The counter 1130 provides twelve pulses for operating the print wheels. The print wheels only require a maximum of 10 pulses, so that there are several superfluous pulses. This over abundance of pulses is planned, so that all the wheels will be set with assurity. If a wheel does not obtain the proper position after the twelfth pulse this will be sensed and indicated on the display as an error condition as aforementioned.

The counter 1130 feeds the pulses through a decoding gate 1133 to flip-flop 1134. Flip-flop 1134 passes an enabling signal to the gates 1115 of FIG. 26 over line 1132 to turn on the SCRs.

The meter status register (FIG. 29) is the means by which the meter communicates with the computer controlling it. It performs three functions: (1) transfer of data (2) indication of status (3) indication of error conditions. Bits 12-15 (not shown in FIG. 29) are used to transfer data from meter memory to the computer. Status indicators include:

______________________________________
Print wheels not moving
(bit 0)  line 1143
Print head not moving (bit 1)  line 1221
Print capacitor charged changed
(bit 8)  line 1220
No funds              (bit 9)  line 1217
Register reads complete
(bit 10) line 1219
Meter ready           (bit 11) line 1215
______________________________________

"Print head not moving" and "print wheels set" set flip-flops 1140 and 1139 respectively which generates interrupts through gate 1141. This relieves the computer of the necessity of waiting in a loop for the duration of the slow mechanical operations involved.

Normally in operating the meter, 4 BCD digits would be outputted to the print buffers, the meter printer would set to the number, the computer would check the meter to see that sufficient postage was available, then issue a print command. The computer would not issue another "set" or "print" command until after the meter has had time to complete the previous operation. The meter is logically locked out from attempting any operation not "well defined". Any such operation sets flip-flop 1135 which outputs a signal on line 1136 to bit 4 (line 1135 1136) of the digital input which indicates a programming error. Examples of such errors are: issuing a print command (a) before the print wheels have finished setting (b) while the print head is moving (c) when there is a setting error (d) when BCD is not in the print buffers (e) when there is insufficient postage in the meter (f) when the printer power supply is not ready and (g) when the meter is not ready. Such an error also generates an interrupt which signals the computer to read the status register and go into a routine to handle this--some error conditions could be handled by computer programming, others would require human intervention. Bit 5 is another error message--non BCD characters in a print buffer. Bit 6 comes up if the print wheels should change position due to the impact of printing.

One-shot 1148 provides a clock signal to the polling circuit of FIG. 18. This 1 sec signal is carried by line 874 to flip-flop 1035 (FIG. 18) to initiate the enter postage mode.

One-shot 1150 provides a dummy signal of 50 ms duration to indicate the print head return. However, the print head can actually be monitored by means of a switch, thus eliminating the need for one shot 1150 if so desired.

FIG. 30 shows the circuitry for the memory power supply 856, and the voltage sensing circuit 858. The voltage sensing circuit 858 comprises two zener diodes 1151 and 1152, respectively. The zener diode 1151 is used to monitor the voltage level before the regulator to the logic circuitry, and the zener diode 1152 is used to monitor the voltage level before the regulator means 1161 to the memory. When the voltage level drops below a desired level in either lines 1153 or 1154, one of the transistors Q₁ or Q₂, as the case may be, will turn off. When either Q₁ or Q₂ turns off, Q₈ will be caused to become non-conducting, which in turn causes Q₇ to turn off. This results in a low signal appearing on line 1155. This low signal is fed over line 1155 to the control power supply and initialization circuit 844 of FIG. 31. If there is no operation being performed in the meter, (for example, add funds) when this low signal is received, then a command to turn power off is given on line 1156 (FIG. 31). This command is then conveyed over line 1156 to the power circuit of FIG. 30 where it turns on transistor Q₄. When transistor Q₄ becomes conducting, current is drawn in line 1157, thus turning off transistor Q₃. This causes transistor Q₉ to become non-conducting, if transistors Q₁ and Q₂ are also non-conducting. Transistors Q₁ and Q₂ are assumed to be turned off because they initiated the start of the power-off condition. Transistor Q₉ will now influence transistor Q₁1 to turn off, thus depriving the memory of power.

On the other hand, if an operation is being performed in the meter when the low signal is received on line 1155, then gate 1158 (FIG. 31) will remain disenabled until the operation is completed. This will prevent the command to turn off power on line 1156 until the operation is completed.

Zener diode 1159 (FIG. 30) acts to regulate the voltage going to the memory. Above the 12 volt level, the zener diode 1159 conducts, clamping the output of transistor Q₁1 at about 12 volts.

Transistor Q₁0 and Q₅ are used in a current limiting circuit to protect the memory power supply. If too much current is drawn in line 1162, transistor Q₁0 becomes conducting which in turn causes transistor Q₅ to turn on. Current is reduced in line 1163 which starts turning off transistor Q₁1 thus limiting the current in line 1162 to a safe value.

Transistor Q₆ is used to provide a "power-on" signal on line 1160 which is fed to the control power supply and initialization circuit 844 of FIg. FIG. 31.

FIG. 31 illustrates the control power supply and initialization circuit 844 as aforementioned. Elements 1164 and 1165 are "one-shots." The one-shot 1164 supplies the "turn-power-off" command carried on line 1156 as previously discussed. The one-shot 1165 supplies the initialization signal used to preset logic elements on start-up including the flip-flop that initiates the cycle mode on start-up.

FIG. 32 depicts the circuitry for the display selector switches 612, 614, 616, 618 and 620. Each switch circuit acts as a buffer register which stores the information. Each switch circuit comprises a single pole double throw switch 1167, a well known debouncing circuit 1168, and a "J-K" flip-flop 1169. Only one switch can be thrown at one time; the switches are mechanically exclusive.

Information is transferred to the flip-flops 1169 when the system is not operating in any of the three modes. The outputs from these circuits are, therefore, well defined (i.e. constant) during the cycle mode.

The gate 1171 generates a signal every time a switch is depressed. The signal is carried on line 619 to the Cycle mode circuit of FIG. 18.

A switch clock signal is introduced on line 1170 which synchronizes reading the manually operated switches into the J-K flip-flops with the clock controlled meter operation. The switch clock signal is generated by the switch clock circuit 1172 of FIG. 33. This signal will only be generated when there is no run signal, and the addressing counter is at zero.

The display used in this postage meter system is a standard Hewlett-Packard display. (No. 5082-7300) which has latches and decoder built-in.

The multiplexer circuitry 1173 of FIG. 33 gates data from the memory to the display, and also blanks and tests the display. The multiplexer elements 1178, 1179, 1180 and 1181 receive memory data from the arithmetic unit output buffer 818 (FIG. 22) over lines 1174, 1175, 1176 and 1177 respectively.

In the display mode the memory data is outputted to the display inputs over lines 1182-1185 one BCD digit at a time. Circuit 1186 of FIG. 33 generates clock signals to enter data into the appropriate display latch. The "0" output of 1186 clocks data into the least significant number display and "9" output into the most significant number display. Because the memory only stores numbers, there is need for a circuit to select the decimal point in the display. Circuit 1188 is such a circuit, and is shown in FIG. 33.

The panel indicator circuits 604, 606 and 608 (lamp drivers) are also illustrated in FIG. 33.

FIG. 34 shows the direct memory read control logic circuitry, which transfers address data to the memory control logic circuitry of FIG. 21. Bits 7 through 11 on the digital output from the computer (see FIG. 28) is placed on lines 1189, 1190, 1191 1192 and 1193 of buffers 1194, 1195, 1196, 1197 and 1198, respectively. When the "read memory" command is given on line 912, flip-flop 1199 is set, provided that the system is not in the middle of a mode. The buffers 1194, 1195, 1196, 1197 and 1198 transfer the address data on line 887 to gates 888 of circuit 1041 of FIG. 21.

On clock pulse 2, flip-flop 1200 provides a "direct" signal on line 892 of circuit 1041 which enables these gates, and the address data is transferred to the buffers 1201, 1202, 1203 and 1204 of circuit 1045 via the memory of FIG. 20. Clock pulse 2 also clears flip-flop 1199 via line 1205 from flip-flop 1200.

On clock pulse 6, gate 1206 is enabled, and buffers 1201, 1202, 1203 and 1204 transfer to latches 1207, 1208, 1209 and 1210 which feeds into interface circuit 914 (FIG. 28).

Flip-flop 1211 (FIG. 34) is set on clock pulse 6 indicating that "read" has been completed. Flip-flop 1211 is left "high" after the meter is read. An interrupt signal is also provided in circuit 872 as a result. This notifies the computer that the read operation has been carried out and the information requested is present on the digital input to the computer.

On clock pulse 8, flip-flop 1200 is cleared, resetting the circuitry for a new read operation.

It will now be appreciated that this invention provides a secure postage metering device which uses a computer-compatible piggy-back-mounted postage printer and electronic digital postal accounting techniques, and is therefore suitable for use in computer-controlled, high-speed-printer-implemented, high volume mailing operations.

Since the foregoing description and drawings are merely illustrative, the scope of protection of the invention has been more broadly stated in the following claims; and these should be liberally interpreted so as to obtain the benefit of all equivalents to which the invention is fairly entitled.

Claims

1. In the combination of a computer and postage metering means arranged to print a numerical amount, said metering means including means for receiving from said computer a signal designating said amount, printing means responsive to said signal receiving means, an addressable memory for storing a present balance, an arithmetic unit responsive to said memory and said signal receiving means to alter said present balance by said computer-designated amount each time said printing means is actuated, memory addressing means for fetching a present balance from a predetermined memory address and conveying it to said arithmetic unit for said balance altering operation and loading the new balance resulting from such operation back into said same memory address, said memory addressing means comprising:

a pulse stream source, a first counter responsive to said pulse stream, a gate responsive to said first counter, a second counter responsive to said gate, means for selecting a memory address in response to said second counter, means for detecting the beginning of a count sequence of said first counter, means for detecting the end of a count sequence of said second counter, and means responsive to both said count sequence detecting means for enabling said gate to start a memory addressing count sequence of said second counter at the beginning of said first count sequence, sequence and for disabling said gate at the end of said memory addressing count sequence.

2. An electronic postage meter comprising:

input means for inputting postage data into said postage meter;

a postage printing means operatively connected to said input means and responsive to said inputted postage data for printing postage to be issued; and

electronic accounting means operatively connected to the postage printing means for monitoring the postage printing means so that an accounting is kept of the postage that is being issued by said printing means, said accounting means having a non-volatile memory for storing postal data, said non-volatile memory being resistive to attempts at erasing said postal data therefrom, so that said accounting means is protected from attempts to erase the accounting of printed postage said accounting means having a non-volatile memory for storing data representative of postage to be issued.

3. The electronic postage meter of claim 2, further comprising electrical disruption means operatively connected to the accounting means for sensing when the accounting means is subjected to changes in voltage effecting the accountability of said accounting means.

4. The electronic postage meter of claim 2, further comprising control means operatively connected between the postage printing means and the accounting means for controlling the operation of the accounting means and the printing means such that a printing of postage cannot be accomplished without being

accounted for by said accounting means. 5. In an electronic franking machine comprising: means for providing an electrical input representative of a franking value selected for a desired next franking operation of the machine, for setting the selected franking value into the machine; a digital electronic input register, having an input connected to said input providing means, for receiving and holding said selected franking value; an electrically adjustable printing device, settable electrically to any selected one of a plurality of different conditions enabling the device to be actuated respectively to print a plurality of different franking values; setting control circuitry, connected with said input register and said printing device, operable in dependence upon said electrical input to bring about setting of said printing device to the condition in which it is actuable to print said selected franking value; a digital electronic total register, for holding an accumulated value representative of the sum of the respective franking values used in preceding franking operations of the machine; and totalling circuitry, connected between said input register and said total register, for effecting addition of said selected franking value held in the input register to said accumulated value; whereby a new accumulated value is provided, to be held in said total register, after printing of said selected franking value, in place of said accumulated value previously held there, the improvement wherein said machine comprises an electronics unit which houses said input providing means, said input register, said total register and said totalling circuitry and a separate printing unit which houses the said electrically adjustable printing device and with which said electronics unit is engaged during the operation of the machine, said electronics and printing units being separable one from the other and having complementary coupling means for setting up operative electrical connections therebetween when the electronics unit is engaged

with the printing unit. 6. A machine as claimed in claim 5, wherein said total register is a non-volatile store. 7. A machine as claimed in claim 6, having an electrical mains input for receiving operating power for the machine from an external mains supply, further comprising capacitive storage means connected to store electrical energy and to deliver that stored energy in the event of failure of said external mains supply in the course of such an addition, whereby the addition can be completed after such failure. 8. A machine as claimed in claim 5, having an electrical mains input for receiving operating power for the machine from an external mains supply, wherein said total register is a volatile store, the machine further comprising auxiliary supply means including a battery, operable to provide an electrical supply for said total register from said battery in the event of failure of said external mains supply, for energizing the total register to retain the said accumulated value after such failure. 9. A machine as claimed in claim 5 further comprising: a digital electronic credit register, housed in the said electronics unit, for holding a current credit value produced by subtraction of the respective franking values used in preceding franking operations of the machine from a maximum credit value preset in said credit register; and subtraction circuitry, housed in the said electronics unit and connected between said input register and said credit register, for effecting subtraction of said selected franking value held in said input register from said current credit value, whereby a new current credit value is provided to be held in said credit register, after said printing, in place of said current credit value previously held there. 10. A machine as claimed in claim 9, having an electrical mains input for receiving operating power for the machine from an external mains supply, wherein said credit and total registers are volatile stores, the machine further comprises auxiliary supply means including a battery, operable to provide an electrical supply for said credit and total registers and said totalling circuitry and subtraction circuitry in the event of failure of said external mains supply, for energizing said credit register to retain said current credit value, and said total register to retain said accumulated value, after such failure.

11. A machine as claimed in claim 9, further comprising, housed in the said electronics unit, an auxiliary register and associated circuitry components operable to accumulate and store in the auxiliary register a count of the number of franking operations that have been carried out by the franking machine using a particular preselected

franking value. 12. The electronic postage meter of claim 2, further comprising electrical means operatively connected to the accounting means for sensing when the accounting means is subjected to changes in voltage affecting the storing of data in the memory of said accounting means. 13. The electronic postage meter of claim 2, further comprising control means operatively connected to the postage printing means and the accounting means for controlling the operation of the accounting means and the printing means whereby printing of postage cannot be effected without being accounted for by said accounting means.