Multiple channel data communication system

Abstract

A multiple channel communications system and method for communication among multiple channels using a channel selectable modem. The system is comprised of a coaxial cable, a variety of interface units with attached communicating devices and a channel bridge. The interface units include a modem and a microprocessor based support element adapted for the attached communicating device. The channel bridge includes two or more modem's modems and a microprocessor based computer for receiving data from one modem and transmitting the data on another modem.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to data communication systems and more particularly to a data communication system for broadband coaxial cable which supports a plurality of communication channels.

2. Description of the Prior Art

Data communication is the transfer of digital information from one point to another, usually between a user terminal and a computer. In more sophisticated systems communication may take place between two computers, a computer and a remote printer or between combinations of computers, memory devices, terminals, or microprocessors used to control various devices, e.g. burglar alarms, to traffic controls, industrial operations, etc. Data is transmitted through a communication channel by a transceiver, sometimes referred to as a MODEM. Generally, the channel composes a pair of wires but can also assume other forms, e.g. radio frequency channels, microwave transmission channels, or optical fibers. In many applications a channel has a device at each end such as a computer connected to a terminal by a pair of wires. Data communication is also possible where there are more than two devices communicating on a channel.

When more than two using devices are connected to a single communication channel there are two methods of data communication. The first method is to assign time slots to the using devices connected to the channel. A using device may then transmit data during its time slot and must wait until the next cycle to transmit again. This method is known as "time division multiple access." The second method of communication allows any using device to transmit data when the communication channel is not being used by another device. This method of communication is referred to as "carrier sense multiple access (CSMA)."

A problem encountered with CSMA communication systems is that data collision occurs when two devices begin to transmit data at the same time. A signal sent by one transceiver will reach another transceiver a short time later, thus during the interim a second transceiver may begin transmitting a signal. The two signals will collide causing the data to be garbled.

Several methods have been developed for collision detection. One method, described in U.S. Pat. No. 4,063,220, granted to Metcalfe, et al., is to compare concurrently the cable contents bit by bit against the locally transmitted contents. If a difference is detected the transmission is aborted. Another method uses a looped cable where a signal is transmitted on an inbound cable and received on an outbound cable. A transceiver will receive its own transmission after the propagation delay of the cable. Once the entire transmission is received it is then compared to the transmitted signal to determine if the data has collided with another transmission. This method is inefficient in that a collision is not detected until multiplex 174 182 and PROM 168 would be necessary in the multiplex terminal support element 30 if encrypted data is to be received or transmitted.

The multiplex terminal support element 30 includes a CPU 197 is connected to a data bus and address bus 198. A RAM 200 is connected to the data and address buses 198. The RAM 200 includes approximately two thousand bytes of memory. A ROM 202 is also connected to the data and address buses 198. The ROM 202 includes approximately four thousand bytes of memory. Also connected to the data and address buses 198 are a support device 204, a USRT 206, eight UART's UARTs 208 and a control 210. The support device 204 is connected to a latch 212 by eight parallel lines. The latch 212 is connected to the channel select input of the MODEM 22 by eight parallel lines. The support device 204 receives a carrier detect input from the MODEM 22. The USRT 206 is connected to the MODEM 22. Each of the eight UART's UARTs 208 is connected to an EIA converter 214 and each of the eight EIA converters 214 is connected to one of the eight terminals 32.

The multiplex terminal support element 30 requires a larger block of random access memory than the terminal support element 24. The multiplex terminal support element 30 also includes eight UART's UARTS 208 where the terminal support element 24 includes only one UART 180. The eight UART's UARTS 208 are necessary to enable the multiplex terminal support element 30 to be connected to the eight terminals 32. The read/write, clock synchronization reset and interrupt request signal are connected to and from the CPU 197 in the same manner as with the CPU 162 of the terminal support element 24. The device select outputs from the control 210 are connected in the same manner as for the control 184 of the terminal support element 24, the only difference being that additional device select outputs are necessary from the control 210 to connect to the additional UART's UARTs 208.

FIG. 6 is a block diagram of the host support element 36 of FIG. 1 and also shows the connection to the MODEM 22 and to the host computer 38. The architecture of the host support element 36 is similar to that of the terminal support element 24 and the multiplex terminal support element 30. Again the encryption/decryption feature of CRYPTO 182 and the EPROM 172 have been omitted for simplification.

The host support element 36 includes a CPU 216. The CPU 216 is connected to a data bus and address bus 218. A RAM 220 is connected to the data and address buses bus 218. The RAM includes approximately two thousand bytes of memory. A ROM 222 is also connected to the data and address buses 218. The ROM 222 includes approximately four thousand bytes of memory. Also connected to the data and address buses 218 are a support device 224, a USRT 226, a direct memory access controller (DMAC) 228, a host interface 230 and a control 232. The support device 224 is connected to a latch 234 by eight parallel lines. The latch 234 is connected to the channel select input of the MODEM 22 by eight parallel lines. The support device 224 receives a carrier detect input from the MODEM 22. The USRT 226 is connected to the MODEM 22. The host interface 230 is connected to the host computer 38.

The host interface 230 comprises a circuit supplied by the manufacturer of the host computer 38. The host interface 230 will interface the signals from the host computer 38 to the host support element 36. The DMAC 228 transfers data directly between the RAM 220 and the host interface 230. The direct memory access feature is included in the host support element 36 to facilitate the higher speed generally encountered with the host computer 38.

FIG. 7 is a block diagram of the channel bridge 18 of FIG. 1. The channel bridge 18 includes a CPU 236 connected to a data bus and address bus 238. The channel bridge 18 also includes a RAM 240 and a ROM 242 each connected to the data and address buses bus 238. Also connected to the data and address bus 238 are a support device 244, a plurality of USRT's USRTs 246, a DMAC 248, a UART 250 and a control 252. The support device 244 is connected to a plurality of latches 254 by eight parallel lines. Each of the latches 254 is connected to the channel select input of each of the MODEM's MODEMs 22. Each of the USRT's USRTS 246 is connected to one of the MODEM's MODEMs 22. Each of the MODEM's MODEMs 22 is connected to a signal splitter 256. The signal splitter 256 is connected to the coaxial cable 14. The UART 250 is connected to an EIA converter 258. The EIA converter 258 has an input/output terminal 260 to provide programmer access to the channel bridge 18. The control 252 has a separate output connected to each of the latches 254.

The channel bridge 18 receives signals on a channel and searches for packets of data directed to a different channel and then retransmits those packets onto the appropriate channel. Each MODEM 22, included in the channel bridge 18, is set to a different channel, thus the channel bridge 18 is capable of providing a direct bridge between a number of channels equal to the number of MODEM's MODEMs 22 included in the channel bridge 18. Data received by the MODEM 22 is transferred to the USRT 246. When data is being received by several USRT's USRTs 246 simultaneously the CPU 236 will become overburdened and incapable of transferring the data to the RAM 240. Thus, the DMAC 248 is used to control the transfer of data from the USRT's USRTs 246 to the RAM 240.

The channel on which the MODEM's MODEMs 22 operate is selected by storing the appropriate value for the desired channel in the support device 244, then the appropriate latch 254 is selected by the control 252 and the output of the latch 254 is held at the desired value. The channel of each of the MODEM's MODEMs 22 may be set by enabling the appropriate latch 254.

In practice the number of channels bridged by the channel bridge 18 is limited by the rate at which received data may be transferred to the RAM 240 and back to the USRT 246. Thus, several channel bridges 18 may be required for the data communication system 10. Where several channel bridges 18 are included in the data communication system 10 a packet of data may need to be routed through more than one channel bridge 18. Routing through more than one channel bridge 18 may be handled by means of a routing table stored in the RAM 240.

FIG. 8 illustrates the data format used by the data communication system 10. The terminal interface 20, the multiplex terminal interface 28, or the host computer interface 34 will transmit a frame of data, referred to by the general reference numeral 300, onto the cable 14. The frame of data 300 is comprised of bytes of data. Generally each byte is comprised of eight bits of data where a bit is a logical "1" or "0". The first byte of the frame 300 is a flage flag 302. The flag 302 has a fixed value of 01111110 and is used to indicate to a receiver that a stream of data is following. Following the flag 302 is a data field 304. Following the data field 304 is a cyclic redundancy check field 306. The cyclic redundancy check field 306 is two bytes in length and is a value generated by the transmitter for the data field 304. The receiver generates a cyclic redundancy check value for the received frame 300 and by comparing with the value of the received cyclic redundancy check field 306 the receiver detects transmission errors. Following the cyclic redundancy check field 306 is a flag 308. The flag 308 has the same value as the flag 302 and indicates the end of the frame 300.

The data field 304 comprises a datagram referred to by the general reference numeral 310. The datagram 310 includes a destination node address 312. The destination node address 312 is the first byte of the datagram 310 and indicates the node which is to receive the frame 300. In the present preferred embodiment a node is defined to be a point in the cable 14 where the terminal interface 20, the multiplex terminal interface 28 or the host computer interface 34 is connected. Each node is assigned a unique address.

The datagram 310 also includes a channel number field 314 following the destination node address 312. The channel number field 314 is one byte in length. The channel number field 314 indicates the channel on which the destination node is located. When the destination node's channel is different from the source node's channel the frame 300 is routed through the channel bridge 18. The channel on which a node is located is determined by the channel select input to the MODEM 22.

Following the channel number field 314 is a transport control field 316. The transport control field 316 is one byte in length. The transport control field 316 is followed by a data field 318.

The data field 318 comprises a packet referred to by a general reference numeral 320. The first byte of the packet 320 is a port field 322. The port field 322 is one byte in length and indicates the destination within a node, for example, one of the terminals 32 connected to the multiplex terminal interface 28. A control field 324 follows the port field 322 and is one byte in length. Following the control field is a data field 326 which can be any length less than 64 bytes.

FIG. 8A illustrates the subfields of the transport control field 316. A version field 328 comprises the first two bits of the transport control field 316. The version field 328 is used to indicate the format of the data contained in the packet 320. The third and fourth bits of the transport control field 316 are not used in the presently preferred embodiment. A hop count field 330 comprises the last four bits of the transport control field 316. When a packet 320 is transmitted by a node the hop count field 330 has an initial value of seven. Each time the packet 320 is routed through the channel bridge 18 the value of the hop count field is decremented by one. When the value of the hop count field equals zero, the packet 320 is discarded. This prevents indefinite looping of packets in the data communication network 10 due to transmission errors.

FIG. 8B illustrates the subfields of the control field 324 when the first bit of the control field 324 is a "1". When the first bit of the control field 324 is a "1" the packet 320 is a data packet. In a data packet the data field 326 contains the information being communicated. Following the first bit of the control field 316 324 in a data packet is a flow control bit 332. The flow control bit 332 is used to adjust for a possible speed mismatch between the transmitting node and the receiving node. Following the flow control bit 332 in a data packet is a sequence field 334. The sequence field 334 is three bits in length. Following the sequence field 334 in a data packet is an acknowledgement field 336. The acknowledgement field 336 is three bits in length.

The sequence field 334 is incremented each time a packet is sent, thus, indicating the order of the packets sent and enabling the receiver to disassemble the packets 320 in the correct order. The acknowledgement field indicates the value of the sequence field 334 for the last correctly received data packet.

When a receiving node runs out of buffer space to store the received data it will discard the received packet 320 and transmit a data packet with the value of the acknowledgement field 336 set to the value of the sequence field 334 of the previously received packet 320 and will set the flow control bit 332 to enable flow control. In the flow control enabled state the transmitting node will delay transmission of the next packet 320 by a predetermined time delay.

When the transmission of a packet 320 has not been acknowledged by the receiving node, then after a predetermined time interval the transmitting node will retransmit the unacknowledged packet. After five retransmission attempts the connection will be aborted.

FIG. 8C illustrates the control field 324 when the first bit is "0". A "0" in the first bit of the control field 324 indicates a control packet. A control type field 338 follows the first bit of the control packet 324. The control type field 324 338 contains a control message for the other node in a connection. The types of control messages include open connection request, open connection acknowledged, open connection nonacknowledged, close connection request and close connection acknowledged.

An open connection request control message signals to another (receiving) node in the data communication system 10 that the transmitting node requests a connection. An open connection acknowledged control message is sent by the receiving node to signal the transmitting node that the receiving node is ready to accept transmitted data. At this point a connection is established between the transmitting and receiving nodes. An open connection nonacknowledged is sent by the receiving node to signal the transmitting node that the receiving node is not ready to receive transmitted data in which case no connection is established. A close connection request control message signals the other node in a connection to close the connection. A close connection acknowledged signals the other node in a connection that a closed connection request was received and thus terminates the connection.

The operation of the data communication system 10 may now be illustrated by way of describing a communication between the terminal 26 and the host computer 38. In such a situation, a user will type a request at the terminal 26 to open a connection with the host computer 38. The user at this time will input the address of the host computer 38. The request will be transmitted to the UART 180 of the terminal support element 24. The UART 180 will output an interrupt request signal to the CPU 162. The CPU 162 will respond to the interrupt request by reading the status register of the UART 180 which will tell the CPU 162 to begin transferring the contents of the registers to the RAM 166. After the data from the terminal 26 has been transferred to the RAM 220 of the host support element 36, the CPU 162 will then read the contents of the RAM 166 which will contain the open connection request. The CPU 162 will assemble the datagram 310 (illustrated in FIG. 8) with the node and channel address for the host computer 38, set the version and hot count of the transport control field 316, set the first bit of the control field 324 to "0" and set the value of the control type field 338 to the code for an open connection request control message. The data field 326 will contain the address of the terminal interface 20. The assembled datagram 310 is then transferred to the USRT 178 of the terminal support element 24. As the datagram 310 is received by the USRT 178, it will generate a cyclic redundancy check value which will be placed in the cyclic redundancy check field 306.

Before the CPU 162 enables the USRT 178 to transfer the data to the MODEM 22, the CPU 162 will read the status register of the support device 176 which will indicate whether or not the carrier detect signal is being generated by the MODEM 22. If the carrier detect signal is being output by the MODEM 22, indicating that coaxial cable 14 is being used, then the CPU 162 will delay enabling the USRT 178 until the carrier detect signal indicates that cable 14 is free. When the cable 14 is free the CPU 162 will enale the USRT 178. The USRT 178 will transmit a request to send signal to the MODEM 22. When the MODEM 22 receives the request to send signal it will disenable the transmit mute 118 thus, allowing an output signal to be broadcast onto the coaxial cable 14. The USRT 178 will then begin to serially transmit the frame 300 to the MODEM 22.

Each time a transmit clock pulse is received from the MODEM 22 the USRT 178 will output a bit of data. The bit of data will be received by the data encoder 84 of the MODEM 22. The data encoder 84 will encode the data into an amplitude modulated output. The amplitude modulated output of the data encoder 84 is received by the voltage controlled oscillator 70. The frequency of the output from the voltage controlled oscillator 70 is determined by the voltage of the inputs from the phase comparator 82 and the data encoder 84. The voltage of the input from the data encoder 84 will be constantly varying, thus, the output frequency from the voltage controlled oscillator 70 will vary according to the amplitude of the input from the data encoder. Thus, the data is encoded into a frequency modulated signal. The output of the voltage controlled oscillator 70 is mixed with the output of the main phase lock loop circuit 56 48 by the mixer 106, thereby making the transmit frequency a function of the channel select input. The output of the mixer 106 is amplified and then transmitted onto the cable 14. When the entire frame 300 has been output from the URST 178 the request to send signal will be turned off and the MODEM 22 will cease transmitting.

The signal transmitted by the MODEM 22 will be received by the central retransmission facility 12. The central retransmission facility 12 translates the frequency of the received signal to a mathematically related higher frequency and rebroadcasts the signal at the higher frequency. In the preferred embodiment the central retransmission facility will rebroadcast the signal at a frequency 156.25 MHz higher than the frequency of the received signal. The unidirectional taps 16 permit only signals in the frequency range of approximately 17.7 to 47.7 MHz to be transmitted in the direction towards the central retransmission facility 12 and only signals in the frequency range of approximately 173.95 to 203.95 MHz to be transmitted in the direction away from the central retransmission facility 12. Thus, a communication channel is comprised of a transmit frequency bandwidth in the frequency range of approximately 17.7 to 47.7 MHz and a receive frequency range of approximately 123.95 173.95 to 203.95 MHz.

The signal rebroadcast by the central retransmission facility 12 will be received by the MODEM 22 included in the host computer interface 34. The signal received by the MODEM 22 will be fed through the mixer 130 within the MODEM 22. The mixer 130 will also receive an input from the main phase lock loop circuit 48. Thus, both the transmit frequency and receive frequency are jointly stepped when the channel select input to the main phase lock loop circuit 48 is changed. The output of the mixer 130 is eventually fed to the IF amplifier 140. The IF amplifier 140 converts the frequency modulated input to an amplitude modulated output. The amplitude modulated output of the IF amplifier 140 is then fed to the data decoder 144. The data decoder 144 converts the amplitude modulated input to a serial digital output identical to the frame 300 generated by the terminal support element 24. The output of the data decoder 144 is then fed to the host support element 36.

The data received by the host support element 36 is fed to the USRT 226. The first eight bits of data are the flag 302 which indicates the start of the frame 300. The next two bytes of data are the node field 312 and the channel field 314 which the USRT 226 internally compares to the address of the host support element 36. The same comparison is made by all nodes on the channel. The USRT 178 of the terminal support element 24 will receive back the flag 302 if the transmission of the frame 300 has not collided with a transmission by another node. If the USRT 178 does not receive the flat 302 it will continue the transmission in the normal manner. However, if the USRT 178 does not receive the flag 302 it is presumed that a data collision has occurred and the USRT 178 will stop transmitting the frame 300. The USRT 178 will then send an interrupt request signal to the CPU 162. The CPU 162 will respond to the interrupt request by waiting a random time and then retransmitting the frame 300. The random backoff will assure that the terminal support element 24 does not restart transmission at the same time that the transmission from th the other node is restarted.

If the node field 312 and the channel field 314 contain the address of the host support element 36 then the USRT 226 will send an interrupt request signal to the CPU 216. The CPU 216 will respond to the interrupt request by enabling the DMAC 228 which will transfer the incoming data from the USRT directly to the RAM 220. As the data is received by the USRT 226 a cyclic redundancy check value is internally computed. When the final flag 308 is received, the cyclic redundancy check value computed by the USRT 226 is compared to the cyclic redundancy check value contained in the cyclic redundancy check field 306. If a transmission error is detected the USRT 226 will output an interrupt request to the CPU 216. If no transmission error is detected the CPU 216 will read the datagram 310 from the RAM 220.

The CPU 216 will then read the control field 324 which contains the open connection request control message and the address of the terminal interface 20. If the host computer 38 has an open port the CPU 216 will assemble an open connection acknowledged data packet. The data field 326 of the return packet 320 will contain the address of the host computer interface 34 plus a port address. All future transmissions by the terminal interface 20 will contain the port address in the port field 322. The open connection acknowledged data packet will be transmitted by the host computer 38 in a manner similar to that described for the terminal interface 20.

When the open connection acknowledged control message is received by the terminal interface 20 a connection is established. Once the connection is established the terminal 26 and the host computer 38 may transmit information back and forth between each other. Each time the terminal 26 sends a data packet the sequence field 334 will be incremented and the acknowledgement field 336 will be set to the sequence number of the highest consecutively numbered data packet received from the host computer 38. Likewise, each time the host computer 38 sends a data packet the sequence field 334 will be incremented and the acknowledgement field 336 will be set to the sequence number of the highest consecutively numbered data packet received from the terminal 26.

When all communication with the host computer 38 is complete the user will type a request at the terminal 26 to close the connection. The terminal support element 20 will transmit the request to the host support element 34. The host support element 34 will send back a close connection acknowledgement to the terminal support element 20 which will terminate the connection.

Communication through the channel bridge 18 may be illustrated by the following example. A transmitting node is assigned to Channel A and a receiving node is assigned to Channel B. In order for the transmitting node to send data to the receiving node the data must be routed through the channel bridge 18. The channel bridge 18 includes one MODEM 22 set to Channel A and one MODEM 22 set to Channel B. The MODEM 22 set to Channel A feeds the incoming data to the USRT 246. The USRT 246 will see the flag 302 and then load the next two bytes into registers and compare the channel field 314 to the code for Channel A. If the channel field 314 contains the address of Channel A the USRT 246 will not send an interrupt request to the CPU 236 since the data does not need to be transferred to another channel. If the channel field 314 does not contain the address of Channel A then the USRT 246 will send an interrupt request to the CPU 236. The CPU 236 will respond to the interrupt request by enabling the DMAC 248 which will transfer the received data from the registers of the USRT 246 to the RAM 240. The USRT 246 will perform the cyclic redundancy check and send an interrupt request to the CPU 236 if a transmission error is detected.

After the received data has been transferred to the RAM 240, the CPU 236 will read the channel field 314 containing the address for Channel B and then begin transferring the received data to the USRT 246 which is connected to the MODEM 22 set to Channel B. If no other transmissions are detected on Channel B the request to send signal will be sent to the MODEM 22 and the data will be transmitted onto the cable 14 on Channel B. The USRT 246 associated with Channel B will perform collision detection for the frame 300 retransmitted onto Channel B in the same manner as was done with the USRT 178 of the terminal support element 24. The receiving node will then detect and receive the data in the normal manner.

The data communication system 10 provides increased data communication capacity through the connection of channels by the channel bridge 18. Low cost of the MODEM 22 is achieved by use of the DAC 98 to produce an amplitude modulated signal which is then used to produce a frequency modulated signal for transmission thus enabling the use of less expensive filters. The programmable channel select feature is made possible by the use of two phase lock loop circuits. The overall expense of installing the data communication system 10 is reduced by the capability for use of existing CATV coaxial cable networks.

Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. Accordingly, it is intended tha that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.

Claims

1. A data communication system comprising:

a coaxial cable;

a plurality of modem's modems connected to the cable including means for selecting the transmit and receive frequency bandwidths frequencies of each of the modem's modems;

means connected to the modem's modems for supplying data to and receiving data from each of the modem's modems;

a central retransmission facility connected at the head end of the cable whereby such that a signal transmitted by at least one of the modem's modems is received by the central retransmission facility and translated to the receive frequency bandwidth of the modem which transmitted said signal; and

a channel bridge connected to the cable including two or more modem's modems each of said modem's modems having different transmit frequency bandwidths transmitting frequencies and different receive frequency bandwidths receiving frequencies than the other of said modems in said channel bridge and including means for transferring a signal signals received by one of said modem's to another of said modem's whereby the modem's modems in the channel bridge such that the modems connected to the cable which are transmitting and receiving in at different frequency bandwidths frequencies may receive signals from and transmit signals to each other via the channel bridge.

2. The data communication system of claim 1, wherein;

the coaxial cable comprises a broadband coaxial cable.

3. The data communication system of claim 1, wherein;:

the means connected to some of the modem's modems for supplying data to and receiving data from the modem's modems include means for supplying data to and receiving data from a terminal.

4. The data communication system of claim 1, wherein;:

the means connected to some of the modem's modems for supplying data to and receiving data from the modem's modems include means for supplying data to and receiving data from a plurality of terminals.

5. The data communication system of claim 1, wherein;:

the means connected to some of the modem's modems for supplying data to and receiving data from the modem's modems include means for supplying data to and receiving data from a host computer.

6. The data communication system of claim 1, wherein;:

the modem's modems include means for detecting the presence of a signal on the cable.

7. The data communication system of claim 1, wherein;:

the means connected to the modem's modems for supplying data to and receiving data from each of the modem's modems includes means for comparing a plurality of the first bits of data received to the corresponding bits of data transmitted by one of the modem's modems attempting to transmit a signal whereby data collisions may be detected.

8. The data communication system of claim 7, wherein;

said means for comparing data are included in a universal synchronous receiver/transmitter.

9. The data communication system of claim 1, further comprising;:

encryption means coupled with the means for supplying data to and from the modem's modems whereby data transmitted over the cable is encrypted by the transmission source and decrypted by the transmission destination.

10. The data communication sytem of claim 9, wherein;

the encryption means includes an interchangeable encryption key.

11. The data communication system of claim 10, wherein;

said encryption key comprises an erasable programmable read only memory.

12. The data communication system of claim 1, wherein;:

said means for transferring a signal included in the channel bridge comprises: a universal synchronous receiver/transmitter connected to said modem's modems, data and address buses connected to each of said universal synchronous receiver/transmitters, a central processing unit connected to said data and address buses, and memory connected to said data and address buses.

13. A method of collision detection for data communication comprising the steps of:

formating digital data by a transmitting node whereby a flag is inserted at the beginning of a transmission frame;

broadcasting said transmission frame onto a cable;

receiving said transmission frame by a central transmission facility;

translating said transmission frame by said central retransmission facility to a receive frequency bandwidth;

rebroadcasting said transmission frame in said receive frequency bandwidth onto said cable;

receiving said flag of said transmission frame by said transmitting node;

comparing said flag as received to said flag as transmitted to detect a collision of data;

aborting the broadcasting of said transmission frame when a collision of data is detected;

waiting a random time after detecting a collision of data; and

rebroadcasting said transmission frame after waiting a random time.