Precessing display pager

Abstract

A hand held paper pager is disclosed in which a transmitted message is displayed in alpha/numeric form by a precessing display which moves the received message across the display in a continuous fashion so that the display need be only large enough to present a relatively small portion of the total message at any given time. In one embodiment a dot matrix LED display is used and is driven by a recirculating shift register memory to provide the precession of the message as a result of the recirculation. In another embodiment the pager may also include a message entry section in which the precessing display is used to present and edit the message prior to transmission either via an acoustic telephone link to a remote transmitter, or directly from a transmitter carried in the pager/encoder package.

Description

FIELD OF THE INVENTION

This invention relates to paging systems anddesription, , it replaces a blank portion of the display with the appropriate character. In normal operation, te the recirculating shift register memory refreshes continually. With the advent of the pointer bit, the recirculating shift register cyclically reads out blank characters or spaces. Upon the depression of a character key, this character is added after the pointer bit and the blank characters are shifted one position to the right in the shift register such that one of the blank characters is lost and one character is added. This is reflected in the next character refresh cycle and the key depressed is now present for visual verification. The character refresh is going on all the time and at a very rapid rate such that the columns of the matrix display are rapidly and sequentially actuated via the clocking of the display, which also reads out the dot matrix character ROM. It will be obvious that the refresh cycle must be sufficiently rapid to avoid flickering of the display. It is therefore important when entering a character into the recirculating shift register memory that this be done at the appropriate time. In this case, the appropriate time means at the end of a refresh cycle. It is therefore the function of the pointer bit to insure that the character is entered into the recirculating shift register memory at this particular point and time. When a character key is depressed, the pointer bit is delayed by one bit position within the memory control register. This permits the next character to be entered at the correct time in the refresh cycle. When the display is full (12 twelve characters displayed) the delay of the pointer bit by 1 one bit results in the display now presenting the characters following this pointer bit such that one character is deleted and one character is added.

By the shifting of the pointer bit, what is displayed therefore are 11 eleven old characters and one new character with the new character being the last one entered. This corresponds to a manual precession of the display such that the precession is controlled by the position of the pointer bit within the memory control register. What has been accomplished, therefore, is that by the depression of keys in the keyboard, a message is loaded into the recirculating shift register memory in timed relationship to the refresh cycle which is established by a pointer bit originated by depression of a control key and the appropriate character key in the keyboard. Since the recirculating shift register memory is continually read out to the dot matrix character ROM, what is read out of the shift register memory is displayed. Thus, changes in data held by the memory are immediately displayed.

Editing of the encoded message is accomplished very simply by precessing the display to the point where the inaccurate or error character is at the right hand most portion of the display. This corresponds to the pointer bit location and merely entering the appropriate correction at that time replaces the character in error with the corrected character. the The corrected character then appears at that display position corresponding to the key depressed.

Thus, a convenience feature of this particular pager is that there is provided on the keyboard a key which, when activated simultaneously with the control key, causes the precessing circuit to time out such that the display precessed precesses by one character at a time in a forward direction, corresponding to one depression of the key. This enables editing of the message by exactly the exact positioning of the message within the display such that locating of the error character at the right most display positon position is easily accomplished.

Another attractive feature of the subject pager is that by activating a simple freeze switch to its ON position, the automatic precessing circuit is disabled thereby freezing the message on the display in the its position at the moment that the freeze switch is actuated. Precessing continues when the precessing circuit is again enabled by throwing changing the freeze switch to its OFF position. It will be appreciated that the freeze switch is in the freeze position during message composition.

It will also be appreicated appreciated that by tapping off of the lines between the recirculating shift register memory and the dot matrix character ROM to parallel-to-serial conversion shift register 770, the encoded message may be made available at the output of this shift register for transmission.

In order to transmit the encoded message, a control key is depressed on the keyboard along with a preselected character key such that the recirculating shift register memory is read out in a timed sequence compatible with the transmission of FSK modulation to a transmitter. It will be appreciated that parallel-to-serial conversion register 770 is loaded in synchronism with the clocking of the recirculating shift register memory during the specially timed readout. By virtue of the specially generated clocking signals, the recirculating shift register is read out in parallel a word at a time to the parallel-to-serial conversion register. Thereafter, the parallel-to-serial conversion register is clocked serially to read out this word.

With the output of the parallel-to-serial conversion register 770 being applied to a conventional FSK modulator, it will be appreciated in one embodiment that the signal from the FSK modulator may contain an address code followed by a message. The addresses will, of course, be entered from the keyboard as a prefix to the message to be transmitted. The pager which receives this message obviously does not display the address code; but, is rather, is actuated after receipt and decoding of its particular address code. Thus, in the case of digital addresses, the keyboard of the subject pager may be utilized to formulate these addresses.

In another aspect of the subject invention, it is a feature that the same counter provides a timing sequence to refresh the LED dot matrix display by reading out the memory cyclically and provides for the encoding of signals (i.e., character codes) to be read into the recirculating shift register memory. In one configuration, illustrated in FIG. 3, an n-bit binary counter 800 in display refresh and encoder timing circuit 746 is utilized which has a certain number of least significant bits, for purposes of illustration in this case, 4 four. These four least significant bits are utilized through a 1-out of-16 one-out-of-sixteen binary decoder circuit 802 to drive the display made up of multiple 5×7 dot matrices 803 via column drivers 804 and to drive encoder keyboard 734 such that the data is read out in three character blocks. The rows of matrices 803 are driven by row driver 806 in accordance with dot matrix character generator 742. After the 4 four least significant bits, the next least significant bits are then routed to a row driver group enable decoder 807, also in circuit 746, which is utilized to drive the next group of characters to be presented. In this manner, the message is grouped via sets of three characters and, in this sense, the character generation and display is multiplexed. The use of the n-bit binary counter sets the multiplexing for the display such that a minimum of row and column drivers are required. This counter is used both in the encoding of a message when the message is to be encoded as well as in the driving of the display. What will now be described is the interaction of the keyboard with the n-bit binary counter to provide the 6 six bit ASCII character codes during the encoding operation.

As mentioned before, a one-out-of 1 one-out-of-sixteen binary decoder 802 is provided along with 15 fifteen column drivers, and 16 sixteen column keyboard matrix 734. The function of this binary decoder is to decode the 4 four least significant bits of the n-bit binary counter and to simultaneously drive both the column drivers in sets of five and the 16 sixteen columns of the keyboard matrix.

In the generation of the 6 six bit ASCII code characters, the n-bit counter is continuously cycled via timing logic 816 to sequentially present by its states all ASCII character codes to a data register 808. Binary decoder 802 is also cycled to produce output pulses at its output terminals in a serial fashion so that during a complete cycle all characters are available as a combination of the signals from the n-bit counter. At the same time, the cycling binary decoder outputs are used to drive the columns to the display. This cycling occurs very rapidly to prevent flicker of the display. Since the outputs from the binary decoder are applied to different keys in a timed sequence, depending on the key switch closed at a given time in the read out cycle, an enable pulse correlated with the character to be encoded is gated over line 809 to data register 808 which is fed in parallel with the output of the n-bit binary counter. At any given time, the n-bit binary counter has an output which corresponds to a given character. Thus, at a given instant of time, the state of the n-bit counter corresponds to a character, for instance, the letter "M.". If the M key is depressed at this time, then the data register is loaded to encode M and this character is entered into the recirculating shift register memory.

The gating logic for gating the enable pulse to the data register is illustrated in dotted box 810 and operates in combination with the fifth bit of the n-bit shift register. The fifth bit determines whether it is the top or bottom row of the keyboard which is actuated. In one embodiment, the keyboard has two rows and 16 sixteen columns. An electronic (digital) switch is provided to enable the choosing of which row of the keyboard is actuated by controlling the state of the fifth bit in the n-bit shift register. This electronic switch includes a shift key 812.

In summary, it is the function of the binary decoder in the display refresh and keyboard decoder timing circuit 746 to provide 16 sixteen output terminals and to produce sequentially a series of pulses, each at a different output terminal wherein the time that each pulse is generated corresponding corresponds to a state of the counter as it cycles through its 16 sixteen states and, therefore, a character. This relates the output terminals to the character represented by the state of the n-bit binary counter. Thus, if a pulse appears at the "nd∅Iadd."output of the binary decoder, this corresponds to a state of the n-bit binary counter and some predetermined ASCII character. If a pulse appears on the "1" output of the binary counter, this will occur at a subsequent period of time and indicates that the n-bit binary counter has changed thereby to recognize a different ASCII character. The closing of a keyboard switch connects the pulse from an associated output of the binary pointer to a gating system to provide a dump signal to the data register which changes its ASCII output with each change of the n-bit register. The binary decoder cycles through its 16 sixteen states sequentially such that the depression of a key will produce a clock pulse to the data register which clock pulse arrives at a time corresponding to the given character. Thus, in a given sequence, the delivery of a dump pulse to the data register results in the dumping of the particular ASCII code to the recirculating shift register memory. What has therefore been accomplished is that by delivering a dump pulse to the data register at a particular predetermined time in the sequence, the n-bit counter state is read out for that character through the data register and into the recirculating shift register memory as the appropriate ASCII code.

It will be appreciated, however, that if the key in the keyboard is depressed for a long period of time, absent any additional circuitry, the character will be repetitively read into the memory. This is undesirable since the depression of a key once is supposed to result in only one character being read into the memory. A circuit is therefore utilized which provides that for a single depression of a keyboard key, only one character is read into the recirculating shift register memory. Basically, this is accomplished by reading a clock 314 pulse only once for one key depression no matter how long the key is depressed. If multiple characters of the same type are to be read in, the key must be depressed a number of times.

Thus, the n-bit binary counter and binary decoder act as a single logic block or circuit to decode the characters entered at the keyboard while, at the same time, supplying timing signals to the column drivers of the display. In this connection, counter 800 is stepped through states representing all of the alpha/numeric characters. The binary decoder decodes these characters and produces, sequentially, a series of timing pulses at its output terminals. These signals sequentially actuate the columns of the matrices via drivers 804. Simultaneously, an output from a particular output terminal of the decoder defines a particular state of counter 800 and thus a character. It will be appreciated that counter 800 and decoder 802 are clocked quite rapidly such that the columns are actuated in quick succession. When a message is to be displayed, dot matrix character generator 742 is clocked and the first group row driver is enabled. Generator 742 produces the appropriate signals for energizing the appropriate dots for the first column of the character to be displayed. On the next clock pulse, generator 742 produces signals for energizing the appropriate dots for the next column of this same character, etc. Thus, the columns are always being quickly strobed while the rows are actuated in synchronism.

For keyboard encoding purposes, the outputs of decoder 802 function not as timing signals, but rather as signals indicative of the state of the binary counter. For instance, outputs 0-4 can correspond to characters A, B, C, and D. As mentioned before, the fifth n-bit binary counter output can be used to designate whether switches 1-16 are activated or switches 17-32. Thus, the 16 sixteen outputs of the decoder can determine 32 thirty-two characters. If during the strobing a particular key is depressed, sometime during the strobing cycle a pulse will be delivered to logic 810 to cause data shift register 808 to transmit a binary code to the recirculating shift register memory. Because the pulse transmitted corresponds in time to a particular state of the n-bit counter, the character read out of the n-bit counter at this time is the one corresponding to the key depressed.

In this way, the same logic circuit serves to generate one set of signals for both display timing and character designation.

It will be noted that both the row drivers and the column drivers are multiplexed. First, the leftmost group row driver is activated simultaneously with the sequential activation of the columns associated with the three leftmost column drivers. After the first three matrices are activated, the next group row driver is activated and the next set of three matrices is enabled. Thus, the matrices are enabled in sets of three. In this embodiment, row driver selection is accomplished by circuitry within row enable decoder 807. It will be appreciated that the column drivers are sequenced by the connections of the column drivers to successive output terminals of decoder 802.

Although a specific emobdiment embodiment to the invention has been described in considerable detail for illustrative purposes, many modifications will occur to those skilled in the art. It is therefore desired that the protection afforded by Letters Patent be limited only by the true scope of the appended claims.

Claims

1. A pager for displaying a message in alpha/numeric form comprising:

means for receiving address signals and coded message signals;

means for decoding said address - signals and for generating an actuation signal;

an internal memory for storing received message signals;

means for displaying an alpha/numeric message of a predetermined length, said display means having character display means at different lateral locations;

means responsive to said actuation signal for loading said message signals into said memory; and

means for reading out said memory, decoding the signals read out from said memory and for driving said display means with the decoded message in such a manner that said message precesses across said display by lateral displacement of a character in the message a number of times to next adjacent character locations, so that the character moves across the display from one side of the display to the other side, whereby long messages for a predetermined recipient may be displayed on a limited length display in a personally portable unit.

2. The pager of claim 1 wherein said memory is a recirculating memory which recirculates to precess the message.

3. The pager of claim 2 wherein said recirculating memory includes a shift register and means for advancing said shift register.

4. The pager of claim 3 wherein said pager includes means for freezing the precession and wherein said advancing means selectively advances said shift register continuously and a character at a time.

5. The pager of claim 1 wherein said display includes a number of light emitting diodes for defining the alpha/numeric character.

6. The pager of claim 5 wherein said light emitting diodes are arranged in a dot matrix.

7. A combination pager and message encoder comprising:

means for decoding a first message transmitted to said pager;

means for displaying said decoded first message in a precessing display in which characters in the decoded first message are laterally displaced a number of times to next adjacent character locations so that the characters move across the display from one side to the other side;

means including a keyboard for composing and encoding a second message; and

means for coupling said encoded second message to said precessing display, whereby a single precessing display is used for both message reception and message encoding composition.

8. The combination pager and message encoder of claim 7 wherein said encoding means further includes means for forming a serially encoded message stream corresponding to said encoded message.

9. The combination pager and message encoder of claim 8 and further including means adapted to couple said message stream to a telephone line via an acoustic coupler.

10. The combination of claim 8 and further including means at said pager and encoder for directly transmitting said message stream to other pagers in the vicinity of said pager-encoder combination.

11. In a pager adapted to receive encoded messages transmitted from a remote location,

means for decoding the transmitted message into a form suitable for display; and

means for displaying said decoded message in a precessing display in which characters in said decoded message are laterally displaced a number of times to next adjacent character locations so that the characters move across the display from one side to the other.

12. For use in combination with common carrier paging transmission apparatus having a voice an audio channel,

a device including an encoder remote from said apparatus having a keyboard for entering a message and means for transmitting to said paging transmission apparatus a series of coded audio tones indicative to of the message entered at said keyboard, said device including a precessing display for displaying portions of the message entered at said keyboard in which characters are laterally displaced a number of times to next adjacent character locations so that the characters move from one side of the display to the other; and

means for coupling said encoder to the audio channel of said transmitting apparatus, whereby the encoded message may be transmitted to a predetermined recipient via said audio channel after said apparatus has transmitted a predetermined address.

13. The encoder of claim 12 and further including a precessing display at said encoder for displaying portions of the message entered at said keyboard in which characters are laterally displaced a number of times to next adjacent character locations so that the characters move from one side of the display to the other.

4. The encoder of claim 13 12 wherein said precessing display includes a recirculating memory for storing the message entered at said keyboard, and means for driving said display in accordance with the output of said recirculating memory, said recirculating memory being coupled to said precessing display through said drive means for driving it in a precessing manner with the recirculation of said memory.

. A method for transmitting an alpha/numeric message to a predetermined pager adapted to receive and display the message and having an address, comprising the steps of:

encoding said message and, simultaneously in a precessing alpha/numeric display, precessing said message across said display such that characters in the message are laterally displaced a number of times to next adjacent character locations so that the characters move from one side of the display to the other;

dialing a telephone number corresponding to said predetermined address,

transmitting signals on an RF carrier, indicative of said predetermined address to activate said predetermined pager from a central transmitter remote from said encoding and from said display; and

wherein said encoding step, said dialing step and said first transmitting step being performed in any relative order, provided that said dialing step precedes said first transmitting step and said second transmitting step;

converting the encoded message produced by said encoding step into a series of audio tones indicative of said message;

generating a series of audio tones indicative of coupling said audio tones to said transmitter; and transmitting said message on the carrier from said central transmitter after transmitting said address signals, said generating step including the steps of encoding said message at a location remote from said transmitter, converting said encoded message into audio tones, and coupling said audio tones to said

transmitter. 16. A message encoding unit comprising:

means including a keyboard for encoding a message;

a memory for storing the encoded message;

a display including an arrangement of display elements, selected elements being actuateable actuatable to present an alpha/numeric character;

means for driving said display in accordance with selected characters in said memory such that a portion of an alpha/numeric message is presented by said display at any given time, said drive means including means for precessing said message across said display such that characters in the message are laterally displaced a number of times to next adjacent character locations so that the characters move from one side of said display to the other; and

means for decoding the message in said memory and for making said decoded

message available at an output thereof. 17. The message encoding unit of claim 16 wherein said memory includes a recirculating shift register memory and wherein said drive means includes means for incrementing said

shift register memory. 18. The message encoding unit of claim 17 wherein said means for making said decoded message available includes means coupled to said memory for converting the message therein into a serial bit stream and means for coupling said serial bit stream to said output.

. The message encoding unit of claim 16 wherein said drive means

includes means for inhibiting said precession. 20. The message encoding unit of claim 19 wherein said memory includes a recirculating shift register memory, wherein said drive means includes means for incrementing said shift register memory and wherein said precession inhibiting means

includes means for inhibiting said incrementing means. 21. The encoding unit of claim 16 wherein said display includes a dot matrix arrangement of

display elements. 22. The encoding unit of claim 16 wherein said display

includes light emitting diode elements. 23. A combination pager and message encoder comprising:

means for decoding a first message transmitted to said pager;

means for displaying said decoded first message in a precessing display in which characters in the decoded first message are laterally displaced a number of times to next adjacent character locations so that the characters move across the display from one side to the other;

means including a keyboard for composing and encoding a second message; and

means for coupling said second message to said displaying means,

whereby a single precessing display is used for both message reception and

message composition. 24. The encoder of claim 14 wherein said recirculating memory comprises a memory of capacity greater than that necessary to contain as many characters as can be displayed in said display at any one time. 25. A method as recited in claim 15, wherein said encoding step comprises encoding said message in a memory remote from said central transmitter. 26. A method for transmitting an alpha/numeric message to a predetermined pager adapted to receive and display the message, comprising the steps of:

dialing a telephone number corresponding to a predetermined address;

transmitting signals on an RF carrier indicative of said predetermined address to activate said predetermined pager from a central transmitter; and

generating a series of audio tones indicative of said message on the carrier from said central transmitter after transmitting said address signals, said generating step including the steps of encoding said message while simultaneously displaying said message in a precessing alpha/numeric display which precesses said message across said display such that characters in the message are laterally displaced a number of times to next adajcent character locations so that the characters move from one side of the display to the other at a location remote from said transmitter, converting said encoded message into audio tones, an coupling said audio tones to said transmitter. 27. A method as recited in claim 26, wherein said encoding step comprises encoding said message in a memory at a location remote from said central transmitter.