Data processing unit with pipelined operands

Abstract

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a data processing unit with pipeline control, and more particularly to a data processing unit which executes variable length instructions having operand specifiers for specifying addressing modes of operands issued independently from operation codes for ascertaining operations.

In a variable length instruction architecture, the instruction length varies even if the length of the operation code is fixed. The leading field of the instruction is an operation code but the other fields have various meanings. Accordingly, the meanings of the fields in the instruction are not uniquely defined. Furthermore, since the operand specifiers in the instruction have variable lengths depending on the addressing mode, the instruction length is variable even if the operation code is fixed.

In an instruction decoding unit which handles such variable length instruction architecture, if an instruction is fetched and decoded parallelly, a large scale hardware is required and a complex control is necessary.

In a system in which an instruction is fetched and decoded one or a plurality of predetermined lengths of units at a time, a long time is required to decode the instruction and hence high speed processing can not be attained. For example, if a basic unit comprises eight bits (byte), a basic instruction has a three to seven-byte length. If the instruction is decoded in synchronism with a machine cycle, the machine cycles which are equal in number to the number of bytes of the instruction are necessary to decode the instruction.

Thus, in the data processing unit which handles the variable length instruction architecture, it is an important factor to increase the speed of the processing of the instruction decoding operation to attain an efficient pipeline processing.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a data processing unit which can carry out the decoding of the variable instructions at a high speed.

It is another object of the present invention to provide a data processing unit which can carry out the decoding of the instructions regardless of the number of operand specifiers the instructions may have.

It is a further object of the present invention to provide a pipeline controlled data processing unit which prepares one operand per machine cycle regardless of the length of the operand specifier.

It is a still further object of the present invention to provide a data processing unit in which if the addressing mode of the last operand specifier in an instruction is a register mode, the operand specifier of the last operand is also decoded in the decode cycle for the operand specifier of the operand immediately preceding to the last operand so that the instructions are executed at a high speed.

According to one aspect of the present invention, there is provided a data processing unit for executing variable length instructions in which the operand specifiers for specifying the addressing modes of operands are independent from the operation codes for ascertaining operations, and in which not only the instructions but also the operands of the respective instructions are pipeline-controlled.

In accordance with another aspect of the present invention, if the last operand specifier of an instruction is the register mode, the operand specifier of the last operand is decoded in the decode cycle for the operand specifier of the operand immediately preceding to the last operand.

In accordance with a further aspect of the present invention, at least one operand specifier of an operand is decoded in each machine cycle to prepare different operands in order to process a plurality of operands in pipeline.

BRIEF DESCRIPTION OF THE DRAWINGS

The other objects and features of the present invention will be apparent from the following description on preferred embodiments when taken in conjunction with the accompanying drawings, in which:

301OER DER 701 of the OFU 700.

In order to transfer the address calculated by the AU 600 to the OFU 700, the OFU 700 must be ready to receive the data from the AU 600. The OFU 700 indicates through the signal line 15C if it is ready to receive the data from the AU 600. In the data transfer cycle to the OFU 700, the AU 600 checks the signal line 15C and only when it determines that the OFU is ready, the AU 600 loads the data generated therein to the registers in the OFU 700. When the OFU 700 is not ready to receive the data, the AU 600 invalidates the process of that cycle and repeats the same process in the next cycle.

The OFU 700 starts its operation when the calculated address of the operand specifier is loaded to the MAR 705 from the AU 600, the operation control signal for the OFU 700 is loaded to the OFCR 702 and the OFCVF 703 is set.

A primary function of the OFU 700 is to access the memory based on the address presented by the AU 600 to fetch the operand. In an addressing mode (e.g. immediate mode or literal mode) in which the operand has been prepared by the AU 600, the operand (to be presented to the MAR 705) is loaded to the OBR 707 through the SEL 706 and the memory is not accessed.

In several modes which need the memory access, the BM₂ 304 is accessed through the signal lines 332. The data read out of the BM₂ 304 is loaded to the OBR 707 through the SEL 706. The operands in the OBR 707 are aligned by the OALIG 708 and then transferred to the EU 800.

In the memory access or transfer of the leading (first) operand specifier of the instruction, the leading address of the microprogram stored in the OER 701 is transferred to the MPC 801.

In order to load the operand prepared in the OFU 700 to the OBR 707, the OBR 707 must contain no data prior to said operand, that is, the OBR 707 must be vacant. The EU 800 indicates through the signal line 12D if the operand in the OBR 707 has been used. In the loading cycle of the operand to the OBR 707, the OFU 700 determines if the OBR 707 is ready to receive the operand. If it is ready, the OFU 700 loads the operand, and if it is not ready the OFU 700 invalidates the process of that cycle and repeats the same process in the next cycle.

As described above, the information (operation code and operand specifier) on the instruction decoded by the DU 500 is transferred to the EU 800 through the AU 600 and the OFU 700.

The EU 800 accesses the ECS 802 by the leading address of the microprogram presented to the MPC 801 to fetch the microprogram to initiate the execution of the instruction. The operand specified by the operand specifier is presented from the OBR 707, or from the ERAR 813 as a register address. If the operand is a destination, the address of that operand is loaded to the MAR 705. The EU 800 executes the instruction using the operands presented from the OFU 700. When the result is to be stored in a register, it is stored in the ERF 812 through the bus 25E and the signal lines 29E. When the result is to be stored in a memory, it is temporarily stored in the MDR 808 and supplied to the BM₂ 304 through the signal lines 333. When the operands presented by the OFU 700 have been processed, it is indicated to the OFU 700 through the signal line 12D to make the OFU 700 ready for the receipt of the next operand.

FIG. 6 shows a stage flow illustrating an instruction flow and a process for executing the instructions, in which three instructions I(1), I(2) and I(3) are shown. Each of the instructions I(1) to I(3) has two operand specifiers. In the first cycle (t₁), the instruction I(1) is fetched (IF(1)). In the next cycle (t₂), the operation code and the operand specifier of the first operand are decoded (D(1) 1). In the next cycle (t₃), the effective address of the first operand is calculated (A(1) 1) in accordance with the decode result and the operand specifier of the second operand is decoded (D(1) 2). In the next cycle (t₄), the first operand is fetched (OF(1) 1) and the effective address of the second operand is calculated (A(1) 2). In the same cycle, the operation code and the operand specifier of the first operand of the instruction I(2) are decoded (D(2) 1). In the next cycle, (t₅), the second operand of the instruction I(1) is fetched (OF(1) 2) and the effective address of the first operand of the instruction I(2) is calculated (A(2) 1) and the operand specifier of the second operand of the instruction I(2) is decoded (D(2) 2). In the next cycle (t₆), the instruction I(1) is executed (E(1)), and the first operand of the instruction I(2) is fetched (OF(2) 1), the effective address of the second operand is calculated (A(2) 2) and the operation code and the operand specifier of the first operand of the instruction I(3) are decoded (D(3) 1). Similar processes are carried out in the cycles t₇ -t₁1. t₇ -t₁0. The fetches (IF(2), IF(3)) of the instructions I(2) and I(3) shown by broken lines in FIG. 6 indicate that instruction prefetches are carried out even when vacant areas in the IB 401 exceed a predetermined number of bits.

While FIG. 6 shows an example where the effective address calculation cycle for the operand and the operand and fetch cycle are completed in one cycle, respectively, the effective address calculation cycle may not be completed in one cycle depending on the addressing mode, or the operand may be fetched by twice referring to the memory in the indirect addressing mode (in which an operand is presented by the first memory reference). Accordingly, the instruction flow and the execution vary depending on the addressing mode.

FIG. 7 shows a stage flow illustrating an instruction flow and the execution of the instructions when three-operand instructions are sequentially executed, in which three instructions I(1), I(2) and (3) are shown, as in the case of FIG. 6. The execution of the instructions in each cycle is similar to that for the sequential two-operand instructions explained in FIG. 6. In the three-operand instruction, however, the third operand is not fetched because it is usually not a source operand but a destination operand. A stage flow for the instructions having more than three operands is essentially the same as the stage flows for the two-operand and three-operand instructions described above in connection with FIGS. 6 and 7. A combination of instructions having different numbers of operand specifiers may also be executed in a similar manner.

While the two-operand and three-operand instructions have been illustrated, it should be understood that the stage flows for one-operand instructions and the instructions having more than three operands are essentially the same as those shown in FIGS. 6 and 7.

The simultaneous decoding process for two operand specifiers and subsequent processes in an instruction which permits simultaneous decoding of the two operand specifiers are now explained.

The simultaneous decoding of the two operand specifiers is carried out only for the instruction which permits the simultaneous decoding of the two operand specifiers although it may be carried out for all of the instructions.

The simultaneous decoding of the two operand specifiers is carried out on condition that the addressing mode of the last operand specifier is the register mode when an operand specifier preceding the last operand specifier is decoded. If the addressing mode is not the register mode, the simultaneous decoding is not carried out but only the operand specifier preceding the last operand specifier is decoded. As an example, an add instruction having two operand specifiers is explained. In the add instruction, the content of the first operand is added to the content of the second operand and the sum of them is stored at the location of the second operand. Thus, the first operand is a read operand and the second operand is a read and write operand. Patterns of the DCS 503 for the add instruction are shown in FIG. 8, in which information of the first operand and the address of the second operand on the DCS 503 are contained at the address of the DCS 503 corresponding to the content of the operation code. Since the first operand is the operand preceding the last operand, the field RD of the DCS 503 contains "1" (indicating the permission of the simultaneous decode of the two operand specifiers). Information of the second operand is stored at the address of the DCS 503 for the second operand and the field E contains "1" indicating that the second operand is the last operand of the instruction. FIG. 9 shows a stage flow when add instructions having the same type of operand specifiers are sequentially executed and the second operands are of the register mode. When the second operands are not of the register mode, the stage flow is not as shown in FIG. 9, but the stage flow is similar to that shown in FIG. 6.

Referring to FIG. 9, the execution of the instructions is explained. In the first cycle (t₁), the data (instruction) on the address containing the instruction I(1) is fetched (IF(1)). In the next cycle (t₂), the operation code and the operand specifier of the first operand of the instruction I(1) are decoded. If the field RD of the DCS 503 contains "1" and the RD-DEC 506 in the DU 500 detects that the addressing mode of the operand specifier of the second operand following the operand specifier of the first operand is the register mode, the RD-DEC 506 reads out a register address from the operand specifier of the second operand and loads it to the ARR 610 in the AU 600 to simultaneously decode the two operand specifiers (D1 & D2(1)). In the next cycle, (t₃), the AU 600 calculates the address of the first operand of the instruction I(1) (A1(1)) based on the decoded result and transfers the calculated address to the OFU 700 and transfers a register address of the second operand of the instruction I(1) to the ORR 709 in the OFU 700. In the same cycle t₃, the DU 500 decodes the instruction I(2) (D1 & D2(2)) in the same manner as in the cycle t₂. In the next cycle (t₄), the OFU 700 fetches the first operand of the instruction I(1) (OF1(1)) and transfers the register address of the second operand of the instruction I(1) to the EU 800. In the same cycle t₄, the AU 600 calculates the address of the first operand of the instruction I(2) (A1(2)) and transfers the address to the OFU 700 and transfers the register address of the second operand of the instruction I(2) to the OFU 700. In the same cycle t₄, the DU 500 decodes the instruction I(3) (D1 & D2(3)) in the same manner as in the decode for the instruction I(1) in the cycle t₂. In the next cycle (t₅), the EU 800 receives the register addresses of the first operand of the instruction I(1) and the second operand of the instruction I(1) from the OFU 700 to execute the instruction I(1) (E(1)). In the same cycle t₅, the OFU 700 fetches the first operand of the instruction I(2) (OF1(2)) and transfers the register address of the second operand of the instruction I(2) to the EU 800. In the same cycle t₅, the AU 600 calculates an address of the first operand of the instruction I(3) (A1(3)) and transfers the address to the OFU 700 and transfers a register address of the second operand of the instruction I(3) to the OFU 700. In the following cycles t₆ and t₇, similar processes are carried out. While the effective address calculation cycle of the operand and the operand fetch cycle are completed in one cycle, respectively, in the example of FIG. 9, the effective address calculation cycle may not be completed in one cycle depending on the addressing mode or a plurality of cycles may be required when the required data is not contained in the BM₂ 304 in the operand fetch cycle and it has to be fetched from the MM 301. Accordingly, various instruction flows and execution processes may be included.

FIG. 10 shows a stage flow illustrating an instruction flow and the execution of the instructions when same type of three-operand instructions are sequentially executed. Similar to FIG. 9, three instructions I(1), I(2), and I(3) are shown in FIG. 10. Also similar to FIG. 9, each of the instructions permits simultaneous decoding of two operand specifiers in a decode cycle of an operand preceding the last operand when the last operand is of the register mode. FIG. 10 shows the stage flow when the last operand (which corresponds to the third operand) is of the register mode. When the third operand is not of the register mode, the stage flow is not the same as shown in FIG. 10, but the stage flow is similar to that shown in FIG. 7. In the two operand instructions shown in FIG. 9, two operand specifiers are decoded in the decode cycle for the operand specifier of the first operand, but in the three-operand instructions shown in FIG. 10, two operand specifiers are decoded in the decode cycle for the operand specifier of the second operand. This difference is due to the fact that the operand preceding the last operand is the first operand in the two-operand instructions while it is the second operand in the three-operand instructions, and it is not an essential difference.

While the processes for the two-operand instructions and the three-operand instructions have been shown in FIGS. 9 and 10, respectively, it should be understood that for the instructions having four or more operands the two operand specifiers can be simultaneously decoded in the decode cycle of the operand specifier of the operand preceding the last operand of the instruction when the last operand is of the register mode. A combination of instructions having different numbers of operands may be similarly executed.

Claims

1. A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising:

(A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including,

(1) instruction prefetch means for prefetching and retaining instructions from said memory means, and

(2) instruction alignment means for aligning bit sequences of instructions including at least one operand specifier prefetched from said memory means;

(B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including,

(1) a first operand specifier decoding means and a second operand specifier decoding means both connected to said instruction alignment means, said second operand specifier decoding means being capable of decoding a next sequential operand specifier received from said instruction alignment means in the same machine cycle as a first operand specifier; and

(2) operation code decoding means connected to said instruction alignment means for ascertaining the operand specifiers included in the instruction from said instruction alignment means and ascertaining the function of said instruction, said operand operation code decoding means including a simultaneous decode permission means for issuing a signal to permit simultaneous decoding of two operand specifiers within the same machine cycle, said permission signal being provided to said second operand specifier decoding means, said second operand specifier decoding means decoding the next sequential operand specifier to the operand specifier decoded by said first operand specifier decoding means only when said permission signal is provided thereto; and

(C) address calculation means connected to said instruction decoding means for calculating an effective address of the operand in accordance with information of an operation code and operand specifiers decoded by said instruction decoding means in the previous machine cycle,

whereby said instruction fetch means, said instruction decoding means and said address calculation means carry out their processes in parallel, and said instruction decoding means and said address calculation means carry out their process for each operand specifier.

2. A data processing unit according to claim 1 wherein said simultaneous decode permission means provides said permission signal only when said second operand specifier decoding means is in a register designation mode.

3. A data processing unit according to claim 1, wherein said instruction prefetch means includes:

(1) instruction buffer means connected to said memory means, said instruction buffer means retaining instructions prefetched from said memory means, and

(2) a fetch pointer connected to said memory means for applying to said memory means an address of an instruction to be prefetched to said instruction buffer means.

4. A data processing unit according to claim 3, wherein said instruction decoding means further includes a decode pointer means for pointing to a leading address to be decoded, and wherein said instruction fetch means includes alignment means connected to an instruction buffer means and said decode pointer for aligning sequential data from the address of said instruction buffer means pointed to by said decode pointer such that said data includes at least one operand specifier.

5. A data processing unit according to claim 3, wherein said instruction prefetch means further includes:

instruction fetch control means connected to said memory means, said instruction fetch control means prefetching an instruction from said memory when said instruction buffer means has a vacant area.

6. A data processing unit according to claim 2, wherein said instruction decoding means further includes:

a decode pointer means for pointing to a leading address to be decoded, and wherein said instruction fetch means includes

alignment means connected to an instruction buffer means and said decode pointer, said alignment means aligning sequential data from the address of said instruction buffer means pointed to by said decode pointer such that said data includes operation codes and at least one operand specifier in a first decode cycle of an instruction, and at least one operand specifier in a subsequent decode cycle of the instruction.

7. A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising:

(A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including:

(1) instruction buffer means connected to said memory means, for retaining instructions prefetched from said memory means,

(3) a fetch pointer connected to said memory means for applying to said memory means an address of an instruction to be prefetched into said instruction buffer means, and

(3) instruction alignment means connected to said instruction buffer means, for aligning bit sequences of instructions prefetched from said memory means in the order of their address, for outputting a bit sequence including an operation code and at least one operand specifier in a first decode cycle, and for outputting a bit sequence including at least one operand specifier in a succeeding decode cycle;

(B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including:

(1) operation code decoding means connected to said instruction alignment means for ascertaining the operand specifiers included in instruction aligned by said instruction alignment means and ascertaining the function of said instruction, and

(2) operand specifier decoding means connected to said instruction alignment means for decoding one or more operand specifiers aligned by said instruction alignment means in the same machine cycle, and

(C) address calculation means connected to said decoding means for calculating an effective address of the operand in accordance with an operation code and operand specifiers decoded by said decoding means in the previous machine cycle,

whereby said instruction fetch means carries out instruction fetching independently of the instruction decoding means and of the address calculation means, said instruction decoding means operates, utilizing an operand specifier as a basic processing unit of, independently of the instruction fetch means and of the address calculation means, and said address calculation means operates, utilizing an operand specifier as a basic unit of processing, independently of the instruction fetch means and of the instruction decoding means, thereby carrying out pipelined processing based on a unit of one or more than one simultaneously processed operand specifiers.

8. A data processing unit according to claim 7, wherein said instruction fetch means includes instruction fetch control means connected to said memory means and said instruction decoding means for fetching an instruction from said memory means when there occurs a vacant area in said instruction buffer means, comparing the effective data length of the vacant area in said instruction buffer means with the data length necessary to a decoding operation, and giving permission for decoding to said decoding means.

9. A data processing unit according to claim 8, wherein said instruction decoding means further includes:

(1) a decode pointer connected to said instruction fetch control means for applying a leading address to be decoded to said instruction fetch control means and to said instruction alignment means,

(2) instruction decode length calculation means connected to said instruction fetch control means for calculating the length of instruction to be decoded and providing the calculated length to said instruction fetch control means, and

(3) decoding control means connected to said instruction fetch control means and said address calculation means for receiving signals from said instruction fetch control means and said address calculation means to control the overall operation of said decoding means.

10. A data processing unit according to claim 8, wherein said decode length calculating means calculates the sum of the length of the operation code and the length of the operand specifier of the first operand following the operation code when the operation code is included in the decoding process, and calculates the length of an operand specifier when the operation code is not included in the decoding process, and provides the calculated length to said instruction fetch control means.

11. A data processing unit according to claim 9 wherein said instruction diode length calculation means includes means operative, when the simultaneous decode of two operand specifiers is permitted, to further add the length of an operand specifier of a register designation mode and provide the resulting sum to said instruction control means.

12. A data processing unit according to claim 9, wherein said instruction decoding means further includes: address calculation program counter value calculation means connected to said instruction fetch means and said address calculation means, said address calculation program counter value calculation means calculating a program counter value used in the address calculation in a program relative mode of an operand specifier to be decoded, based on the decode results from said operation code decoding means and said operand specifier decoding means and the information of the leading address to be decoded from said decode pointer, and providing the calculated count to said address calculation means.

13. A data processing unit according to claim 9, wherein said alignment means includes a multi-bit shifter capable of shifting a plurality of bits simultaneously, the number of times of shift being indicated by said decode pointer.

14. A data processing unit according to claim 9, wherein said address calculation means includes:

(1) decode result retaining means connected to said instruction decoding means, said decode result retaining means retaining information decoded by said instruction decoding means,

(2) calculation means connected to said decode result retaining means, said calculation means calculating an execution address of an operand, based on the information from said decode result retaining means, and

(3) address calculation control means connected to said decoding control means, said address calculation control means being operative when a decode result for at least one operand specifier is loaded to said decode result retaining means for causing said calculation means to calculate the effective address of the operand based on the decode result and providing to said decoding control means information indicating whether the decode result can be loaded to said decode result retaining means.

15. A data processing unit according to claim 14, wherein said decode result retaining means includes:

(1) control data latch means for latching control data necessary to calculate the address,

(2) register address latch means for latching register addresses included in an operand specifier,

(3) displacement latch means for latching displacement, literal data and absolute address information included in an operand specifier and

(4) address calculation start signal latch means for latching a signal indicating the start of the address calculation of an operand based on the decode result.

16. A data processing unit according to claim 9 wherein said instruction decoding means further includes:

(1) decode pointer updating means connected to said decode pointer, said decode pointer updating means adding to the content of said decode pointer the length of an instruction decoded in the decode cycle and sending the resulting sum to said decode pointer as a leading address to be decoded next, and

(2) instruction decode length calculation means connected to said operation code decoding means and said first operand specifier decoding means, said instruction length calculation means calculating a sum of the length of the operation code and the length of an operand specifier of a first operand following to the operation code in a decode cycle including the operation code and calculating the length of the operand specifier in a decoding cycle including no operation code and presenting the calculated length to said decode pointer updating means as a decoded instruction length.

17. A data processing unit according to claim 16 wherein said instruction decode length calculation means includes means operative, when the simultaneous decode of the two operands is permitted, to further add the length of the operand specifier of the register designation mode and provide the resulting sum to said decode pointer updating means.

18. A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising:

first means for storing data including variable length instructions and certain of the operands to be executed by certain of the instructions;

second means for prefetching an instruction from said first means, for retaining the prefetched instruction, and for aligning a predetermined sequence of elements of the instruction including at least one operand specifier;

third means for decoding an operation code and each operand specifier of an aligned instruction received from said second means, for calculating the effective address for the operand specified by each operand specifier in accordance with the decoded operation code, for fetching the operand from said first means in accordance with the calculated effective address for each operand specifier, and for retaining the fetched operands;

fourth means for controlling said third means so that said decoding and said address calculating are executed independently and at different times for each operand specifier, with one operand specifier being decoded while an effective address for an operand corresponding to another preceding operand specifier is being calculated; and

fifth means for executing the instruction in accordance with the decoded operation code and the retained operand.

19. A data processing unit according to claim 18, wherein said fourth means includes means for controlling the decoding by said third means so as to decode two operand specifiers simultaneously in case of a last operand specifier of the instruction having a register mode and for controlling said address calculation by said third means so as to not calculate the effective address for the operand corresponding to the register mode operand specifier, the decoded data of the register mode operand specifier being treated as the effective address for the register directly. 20. A data processing unit according to claim 18, wherein said third means includes means for providing a two operand specifier decoding permission signal in response to certain operation codes, and said fourth means includes means for controlling the decoding by said third means so as to decode two operand specifiers simultaneously when said two operand specifier decoding permission signal is provided and the last operand specifier of the instruction is in a register mode, and for controlling said address calculation by said third means so as to not calculate the effective address for the operand corresponding to the register mode operand specifier, the decoded data of the register mode operand specifier being treated as the effective address for the register

directly. 21. A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising:

first means for storing data including variable length instructions and certain of the operands to be executed by certain of the instructions;

second means for accessing said first means to exchange data with said first means;

third means for prefetching an instruction from said second means, for retaining the prefetched instruction, and for aligning a predetermined sequence of elements of the instruction including at least one operand specifier;

fourth means for decoding an operation code and each operand specifier of an aligned instruction received from said third means, for calculating the effective address for the operand specified by each operand specifier in accordance with the decoded operation code, for fetching the operand from said second means in accordance with the calculated effective address for each operand specifier, and for retaining the fetched operands;

fifth means for controlling said fourth means so that said decoding and said address calculating are executed independently and at different times for each operand specifier, with one operand specifier being decoded while an effective address for an operand corresponding to another preceding operand specifier is being calculated; and

sixth means for executing the instruction in accordance with the decoded operation code and the retained operand. 22. A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operand codes for ascertaining operations, comprising:

(A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including,

(1) instruction prefetch means for prefetching and retaining instructions from said memory means, and

(2) instruction alignment means for aligning bit sequences of instructions including at least one operand specifier prefetched from said memory means;

(B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including,

(1) operand specifier decoding means connected to said instruction alignment means for decoding a next sequential operand specifier received from said instruction alignment means simultaneously with a preceding operand specifier and

(2) operation code decoding means connected to said instruction alignment means for decoding the operation code included in the instruction from said instruction alignment means and ascertaining the function of said instruction, said operation code decoding means including a simultaneous decode permission means for issuing a signal to permit simultaneous decoding of two operand specifiers within the same machine cycle, said permission signal being provided to said operand specifier decoding means to permit the decoding of the next sequential operand specifier simultaneously with decoding of the preceding operand specifier, and

(C) address calculation means connected to said instruction decoding means for calculating an effective address of the operand in accordance with information of an operation code and operand specifiers decoded by said instruction decoding means in the previous machine cycle,

whereby said instruction fetch means, said instruction decoding means and said address calculation means carry out their processes in parallel, and said instruction decoding means and said address calculation means carry out their process for each operand specifier. 23. A data processing unit according to claim 22 wherein said operand specifier decoding means operates to decode the next sequential operand specifier simultaneously with the decoding of the preceding operand specifier only when said permission signal is provided thereto and the addressing mode of said next sequential operand specifier is a register mode.