Frequency divider

Abstract

In utilizing frequency dividers at high frequencies the maximum operating frequency is determined by the delay time through the frequency divider. To minimize this delay time, a digital frequency divider is provided having a binary counter constructed of flip-flops and a shift register coupled to the output of said counter, wherein the output state of the shift register is forcibly reduced to a low level in response to a control signal for varying the number of frequency division of said counter. A circuit is also provided for feeding the input terminal of the flip-flop at the first stage of said counter with an OR output made up of the outputs of said shift register and said counter. Thus, the digital frequency divider can operate at a speed which is limited only by the toggle frequency of said flip-flop circuits.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a frequency divider, and, more particularly, to a 2-modulus prescaler which is constructed of a digital circuit so that it can operate at a high speed.

2. Background of the Invention

The digitalization of an RF circuit to be used in a TV receiver, an FM receiver or a mobile telephone has recently been performed. Of these, the development of the frequency synthesizer which operates at radio frequencies in the VHF and UHF bands has been promoted. One of the important parts of such a circuit is a frequency divider which can count down the frequency.

An important consideration for the development of a digital frequency divider is that the division ratio can be varied in accordance with its intended use, i.e., that it can be programmed. Also, it is important that the divider can operate at a high speed and that its production yield is so high that it can be constructed at a low cost.

The digital frequency divider is preferably constructed with a pulse counter using a number of flip-flop circuits. But the construction of the flip-flop circuit operating at a GHz band raises a number of problems in the careful selection of the circuit constituting elements and in the design and production of the device.

As the frequency divider which can operate at a high speed and which can be programmed, the so-called "Swallow-count" frequency divider has conventionally been used. This device is constructed of high and low speed units in which the 2-modulus prescaler developed as the Swallow-count frequency divider is used in the high speed unit. This 2-modulus prescaler can have its number of frequency division (or mode) interchanged in two (or more) stages in response to an external control signal and is used in combination with another programmable (or frequency division number variable) frequency divider which can operate at a low speed.

The Swallow-count frequency divider is, in principle, a variable frequency divider belonging to that class of divider having high operating speeds. However, even so, the device practically has its upper operating limit at 650 MHz at the present time. In case, however, the frequency divider is to be used in a mobile telephone or a UHF TV receiver, there is required a frequency divider which operates at a frequency equal to or higher than about 1 GHz. This requirement has not been satisfied by the conventional frequency divider. Therefore, the realization for the digital frequency divider which can operate at a frequency as high as 1 GHz or more has been desired.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to improve the conventional 2-modulus prescaler and to provide a digital frequency divider which can operate at a high speed. More specifically, the object of the present invention is to provide a digital frequency divider which has its operating speed (as high as 1 GHz) substantially determined only by the delay time of one stage of a flip-flop circuit constituting the digital frequency divider.

In order to attain the aforementioned object, the present invention is characterized in that the 2-modulus prescaler is constructed in the following manner. Namely, the 2-modulus prescaler is constructed to include a binary counter which is constructed of a flip-flop circuit and a shift register having an input terminal connected with the output terminal of said frequency divider, a terminal having its output state forcibly reduced to a "0" level in response to an external control signal, and an output terminal. An OR gate feeds the input terminal of the flip-flop at the first stage of said frequency divider with denoted atand no mode change control signal is fed to the second clear terminal CR₂ [LLL], the outputs at the terminals Q₇, Q₈ and Q₉ are changed to the state [HLH] in response to the clock signal t₁.

Since the terminal Q₈ is cleared to the low level in response to the next clock signal t₂ by feeding the clear terminal CR₁ with the signal from the output terminal Q₉ of the frequency divider 13, the terminal Q₈ holds the low level thereby to effect the state [LLH] following clock signal t₂. As a result, since the flop-flop 7-9 maintains the clear state until two rises of the output at the terminal Q₇ come to the input terminal C₉ of the frequency divider, the 2-modulus frequency divider effects the toggle operation as a 1/2 frequency divider. Specifically, the states [LLH] and [HLH] are repeated twice. When the clock signal t₅ comes, the terminal Q₇ is changed to the high level thereby to feed the terminal C of the frequency divider 13 with the second clock signal so that the level at the terminal Q₉ is inverted. As a result, immediately prior to a clock signal t₆, the state [HLL] is reached. Thus, the state [LHL] is invited in response to the clock signal t₆, the state [LLL] is invited in response to a clock signal t₇, and the state [HLL]is invited in response to a clock signal t₈. Thus, the terminal C of the frequency divider 13 is fed with the high rise of the first Q₇ as the clock signal, but the output at the terminal Q₉ is left unchanged. As a result, during the clock signals t₉ to t₁1, the outputs at the output terminals Q₇ and Q₈ are varied similarly to the manner of the clock signals t₆ to t₈. In response to the clock signal t₁1, however, the level at the terminal Q₇ is raised to the high value thereby to feed the frequency divider 13 with the second clock so that the output terminal Q₉ takes the high level. As a result, during the clock signals t₆ to t₁2, the 2-modulus frequency divider operates as the 1/3 frequency divider thereby to twice repeat the 1/3 frequency divisions so that the state becomes similar to that immediately prior to the application of the aforementioned clock signal t₁. Therefore, the states, at which the 1/2 and 1/3 frequency divisions are performed twice, respectively, are repeated so that the signal, which has been generated by dividing the frequency of the clock signal to be fed to the input terminal 1 into 1/10, can be generated at the output terminal 12 which is connected with the output Q₉ of the low speed frequency divider 13.

The foregoing description is directed to the state at which no mode change control signal is fed to the second clear terminal CR₂ of the shift register 7-9. When the control signal is fed to this second clear terminal CR₂ from the input terminal 8, the output Q₈ takes the low level so that the 2-modulus frequency divider becomes a 1/2 frequency divider which is constructed of the flip-flop circuit 7-8. As a result, a signal, which has been generated by dividing the frequency of the input clock into 1/8, can be attained at the output of the 1/4 frequency divider 13.

Although the embodiment shown in FIG. 5 as described above is directed to the case in which the 2-modulus frequency divider accomplishes 1/2 and 1/3 frequency divisions whereas the low speed frequency divider 13 accomplishes 1/4 frequency division, it is generally possible to realize a frequency divider which has any desired number of frequency division and which can operate at a high speed by the construction shown in FIG. 7. In this Figure, reference numeral 14 indicates a 2-modulus frequency divider which accomplishes high speed operations at the frequency division numbers n and n+1, while numeral 17 indicates a low speed frequency divider having a frequency division number M. Numeral 16 indicates a control circuit for varying the frequency division number M of the aforementioned frequency divider 17. This frequency divider 17 is constructed by connecting flip-flop circuits in cascade such that the outputs of the respective stages are fed as the clear signal of the shift register of the aforementioned 2-modulus frequency divider through an OR circuit 18. The plural input signals of the aforementioned OR circuit are varied by the control circuit 16.

Since the output of the aforementioned frequency divider 17 takes M output states, if the frequency divider is so controlled that the m states of the M stages are at the low level whereas the remaining (M-m) stages are at the high level, the whole frequency division number N of the output terminal 12 for the signal from the input terminal 1 can be expressed by the following Equation:

N=n(M-m)+(n+1)m=nM+m (1).

On the other hand, if the clear signal is supplied from the control terminal 8, the whole frequency division number N can be expressed by the following Equation:

N=2M (2).

Therefore, if the aforementioned numbers M and m are suitably set, it is possible to realize a frequency divider having any desired frequency division number. As is different from the "Swallow-count" frequency divider, as shown in FIG. 1 and well known in the art, the downcounter 6 can be dispensed with. In most cases where the frequency division number of the low speed frequency divider becomes higher than 10000, the point of requiring no down-counter can be effective for reducing the cost and improving the stability of the system. The embodiment of FIG. 5 corresponds to the case of n=2, M=4 and m=2.

In the construction of FIG. 7, on the other hand, in the case of n=2 and m=1, the whole frequency division number N can be determined from the aforementioned Equations (1) and (2), as follows, respectively:

N=2M+1 (1)';

and

N=2M (2)'.

These Equations express all of the odd and even integers so that a frequency divider having any desired frequency division number can be realized by applying the external control signal. Thus, it is remarkably feasible to design a circuit system such as the digital frequency synthesizer making use of the frequency divider of the present invention. The reduction of the number m to 1 can be easily realized by feeding the OR circuit with the outputs of the respective stages of the flip-flop circuits which are connected in cascade while constituting the frequency divider 17.

As has been basically described hereinbefore, according to the present invention, the AND function for the mode change is replaced by the clearing function of the flip-flop circuit thereby to effect the high speed. Since the delay time for determining the speed corresponds to only one stage of the flip-flop circuit, the speed can be made far higher than that of the conventional frequency divider. According to the present invention, more specifically, it is feasible to provide a high speed frequency divider which has the same speed as the frequency of the flip-flop circuit and which has, on principle, the maximum operating speed of the frequency divider constituting the flip-flop circuit. The possibility of frequency divisions of 1/10 and 1/8 up to 1 GHz has been confirmed with the use of the flip-flop circuit which is being practiced at present and which has a toggle frequency of 1 GHz.

It is to be understood that the above-described arrangements are simply illustrative of the application of the principles of this invention. Numerous other arrangements may be readily devised by those skilled in the art which embody the principles of the invention and fall within its spirit and scope.

Claims

1. A frequency divider comprising:

a counter constructed of one or more flip-flop circuits;

a shift register including an input terminal connected with an output terminal of said counter, an output terminal for providing a shift register output signal and a clear terminal responsive to a predetermined external control signal for varying the number of the frequency division of the frequency divider by forcing the shift register output signal at the output terminal to a zero condition; and

a feedback circuit for feeding an input terminal of the flip-flop circuit at the first stage of said counter with an OR signal comprised of the output of said counter and the output signal of said shift register.

2. A frequency divider as set forth in claim 1, wherein said feedback circuit is constructed of a wired logic circuit having two input terminals to which said output signal of said counter and said output signal of said register are applied, and an output terminal connected to said input terminal of the flip-flop circuit at the first stage of said counter.

3. A frequency divider as set forth in claim 1, wherein said shift register includes a flip-flop circuit.

4. A frequency divider as set forth in claim 1, wherein said counter includes: a first flip-flop circuit; a second flip-flop circuit coupled to a not-output signal of said first flip-flop circuit; an input terminal for commonly feeding clock terminals of the respective flip-flop circuits with an input signal; and an output terminal for extracting the not-output signal of said first flip-flop circuit as a frequency divided output.

5. A frequency divider as set forth in claim 4, wherein the division ratio of the frequency divider is 1/6 when the external control signal is not applied and 1/5 when the external control signal is applied.

6. A frequency divider as set forth in claim 1, wherein said counter includes a single flip-flop circuit, and wherein said feedback circuit includes a NOR circuit, whereby the input terminal of said single flip-flop is commonly fed to respective clock terminals of said flip-flop circuit and said shift register thereby to interchange the division ratio between 1/2 and 1/3.

. A frequency divider as set forth in claim 1, wherein the flip-flop

circuits of the counter are D-type flip-flop circuits. 8. A frequency divider as set forth in claim 1, wherein said output terminal of the shift register is held in said zero condition for as long as said predetermined external control signal is applied to said clear terminal.

A frequency divider as set forth in claim 1, wherein said feedback circuit is comprised of a single wired OR gate having a much smaller delay time than a delay time τ_F of said flip-flop circuit so that a maximum operating frequency of said frequency divider is 1/τ_F.

A frequency divider comprising:

a first counter including a binary counter including one or more flip-flop circuits;

a shift register including an input terminal connected with an output terminal of said first counter, a clear terminal for effecting the clearing operation of the shift register in response to an external control signal for varying the frequency division number, and an output terminal for providing a shift register output signal;

a logic circuit a first feedback circuit for feeding an input terminal of the flip-flop circuit at the first stage of said first counter with an OR signal a logical operation signal of the output of said first counter and the output signal of said shift register;

a second counter including one or more flip-flop circuits coupled to the output of said first counter for further dividing the frequency of the output of said first counter; and

a second feedback circuit for applying at least one portion of the output of the flip-flop circuits constituting said second counter,

as a clear signal, to said shift register. 11. A frequency divider as set forth in claim 10, wherein said first counter includes a 2-modulus frequency divider for interchanging the frequency division number between n and n+1 (wherein n is an integer), and wherein said second feedback circuit includes an OR circuit made receptive of all the outputs of a plurality of flip-flop circuits constituting said second

counter. 12. A frequency divider as set forth in claim 6 10, wherein the flip-flop circuits of the first counter are D-type flip-flops and the flip-flop circuits of the second counter are toggled flip-flops which produce a change in state of their output for

every other input signal applied to their input terminals. 13. A frequency divider as set forth in claim 10, wherein the frequency division ratio at the output of the second counter is 1/10 when the external control signal is not applied to the shift register clear terminal and 1/8 when the external control signal is applied to the shift register clear terminal.

. A frequency divider as set forth in claim 10, wherein the logic circuit the first feedback circuit comprises a NOR gate.

5. A frequency divider comprising:

a counter constructed of one or more flip-flop circuits;

a shift register including an input terminal connected with an output terminal of said counter, an output terminal for providing a shift register output signal and a clear terminal responsive to a predetermined external control signal for varying the number of the frequency division of the frequency divider by forcing the shift register output signal at the output terminal to a zero condition; and

a feedback circuit for feeding an input terminal of the flip-flop circuit at the first stage of said counter with a NOR signal of the output of said

counter and the output signal of said shift register. 16. A frequency divider as set forth in claim 15, wherein said output terminal is held in said zero condition for as long as said predetermined external control

signal is applied to said clear terminal. 17. A frequency divider as set forth in claim 15, wherein said feedback circuit is comprised of a single wired NOR gate having a much smaller delay time than a delay time τ_F of said flip-flop circuit so that a maximum operating

frequency of said frequency divider is 1/τ_F. 18. A frequency divider as set forth in claim 15, wherein said feedback circuit is constructed of a wired logic circuit having two input terinals to which said output signal of said counter and said output signal of said register are applied, and an output terminal connected to said input terminal of

the flip-flop circuit at the first stage of said counter. 19. A frequency divider as set forth in claim 4, wherein the division ratio of the frequency divider is 1/5 when the external control signal is not applied and 1/4 when the external control signal is applied. 20. A frequency divider comprising:

a counter means for counting an input signal;

a shift register means for generating an output signal, wherein said output signal is a first signal produced from shifting an output of said counter means when an external control signal is not applied to said shift register means and a second signal produced from clearing an output of said counter means when an external control signal is applied to said shift register; and

a feedback circuit means for feeding said counter means with a logical operation signal of the output signal of said counter means and the output signal of said shift register means. 21. A frequency divider as set forth in claim 20, wherein said counter means includes one or more flip-flop circuits. 22. A frequency divider as set forth in claim 20, wherein said feedback circuit means includes a wired

logic circuit. 23. A frequency divider as set forth in claim 20, wherein said shift register means includes a flip-flop circuit. 24. A frequency divider as set forth in claim 20, wherein said counter means includes a first flip-flop circuit, and a second flip-flop circuit coupled to a not-output signal of said first flip-flop circuit as a frequency divided output. 25. A frequency divider as set forth in claim 20, wherein said feedback circuit means includes an OR circuit. 26. A frequency divider comprising:

a first counter means for counting an input signal;

a second counter means for dividing the frequency of the output signal of said first counter means;

a shift register means for generating an output signal, wherein said output signal is a first signal produced from shifting an output of said first counter means when a clear signal including an external control signal and an output signal of said second counter means is not applied to said shift register means and a second signal produced from clearing an output of a first counter means when said clear signal including at least one of an external control signal and an output signal of said second counter means is applied to said shift register; and

a feedback circuit means for feeding said first counter means with a logical operation signal of the output signal of said first counter means

and the output signal of said shift register means. 27. A frequency divider as set forth in claim 26, wherein said second counter means includes one or more flip-flop circuits. 28. A frequency divider as set forth in claim 26, wherein said first counter means includes one or more flip-flop circuits. 29. A frequency divider as set forth in claim 26, wherein said feedback circuit means includes a NOR circuit. 30. A frequency divider as set forth in claim 26, wherein said feedback circuit means a wired logic

circuit. 31. A frequency divider comprising:

a counter having one or more flip-flop circuits;

a shift register coupled to said counter, having input means for deriving an input signal from said counter, output means for providing a shift register output signal and clear means responsive to a predetermined external control signal for varying the number of the frequency division of the frequency divider by forcing the shift register output signal to the logic value zero; and

a feedback circuit coupled to said counter and shift register, for feeding said counter with a logical operation signal comprised of the output of said counter and the output of said shift register.