A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused n+ capacitor region similar to the n+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.
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1. A dynamic memory cell formed in a face of a semiconductor body, said cell comprising:
an access transistor having a source-to-drain path at a channel area of said face, and a metal gate over said channel area separated therefrom by a thin gate oxide; a bit line including an elongated n+ region of said face, the drain of said transistor being an edge of said n+ region; a metal word line extending along said face perpendicular to said bit line, said metal gate being a part of said word line; said n+ region of said bit line being insulated from said word line by thick thermal field oxide overlying said bit line; a capacitor area at said face including a trench etched into said face and n+ region surrounding said trench, with a thick thermal field oxide overlying said n+ region; a region of thermal field oxide encircling said trench inset into said n+ region surrounding said trench, a field plate including a conductive layer covering said face overlying said capacitor area, said bit line and all areas except said channel area of said transistor, and extending down into said trench to provide the upper plate of the capacitor, insulated from the silicon in said trench by a thin oxide.
2. A memory cell according to
3. A memory cell according to
4. A memory cell according to
5. A memory cell according to
6. A memory cell according to
7. A memory cell according to
8. A dynamic memory cell formed in a face of a semiconductor body, said cell comprising:
an access transistor having a source-to-drain path at a channel area of said face, and a gate over said channel area separated therefrom by a thin gate oxide; a bit line including an elongated n+ region of said face, the drain of said transistor being an edge of said n+ region; a word line extending along said face perpendicular to said bit line, said gate being a part of said word line; said n+ region of said bit line being insulated from said word line by thick thermal field oxide overlying said bit line; a capacitor area at said face including a trench etched into said face and n+ region surrounding said trench, with a thick thermal field oxide overlying said n+ region; a region of thermal field oxide encircling said trench inset into said n+ region surrounding said trench, a field plate including a conductive layer covering said face overlying said capacitor area, said bit line and all areas except said channel area of said transistor, and extending down into said trench to provide the capacitor, insulated from the silicon in said trench by a thin oxide. 9. A memory cell according to
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This invention relates to manufacture of semiconductor devices, and more particularly to a dynamic read/write memory cell of the MOS VLSI type.
Semiconductor dynamic RAM devices of the type shown in U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine (a 16K RAM), or U.S. Pat. No. 4,293,993 issued to McAlexander, White and Rao (a 64K RAM), have been manufactured by processes of the type described in U.S. Pats. Nos. 4,055,444 or 4,388,121, both issued to G. R. M. Rao; all of these patents are assigned to Texas Instruments. In order to reduce the size of a dynamic RAM cell to the level needed to produce very high density RAMs, such as the 1-Megabit DRAM, various methods of reducing the capacitor size have been proposed. The magnitude of the capacitor must be maintained at no less than a certain value so that sufficient charge is stored. One method of reducing capacitor area yet maintaining adequate charge storage is to reduce the oxide thickness as explained in U.S. Pat. No. 4,240,092 issued to Kuo, assigned to Texas Instruments; this approach reaches a limit in the area of about 100 to 200 Å oxide thickness because of yield and reliability problems. Another way of increasing the capacitance per unit area is to etch a groove, or trench, in the capacitance region, thus increasing the area; an example of this method is shown in U.S. Pat. No. 4,225,945, also assigned to Texas Instruments.
It is the principle object of this invention to provide an improved process for making high density dynamic RAM cells, particularly with an increased capacitance area due to a trench etched into the storage capacitor region. Another object is to provide an improved method of making trench capacitor type dynamic RAM cells in which the step of etching the trench avoids the effect of undercut. A further object is to provide a simple and reliable process for forming trench capacitors.
In accordance with one embodiment of the invention, a dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a plan view, greatly enlarged, of a small part of a memory cell array in a semiconductor dynamic read/write memory, including a memory cell according to the invention;
FIG. 2 is an elevation view, in section, of the cell of FIG. 1, taken along the line 2--2 in FIG. 1;
FIG. 3 is an elevation view, in section, of the cell of FIG. 1, taken along the line 3--3 in FIG. 1;
FIG. 4 is an elevation view, in section, of the cell of FIG. 1, taken along the line 4--4 in FIG. 1;
FIG. 5 is an electrical schematic diagram of the memory cell of FIGS. 1-4; and
FIGS. 6-9 are elevation views in section of the cell of FIGS. 1, corresponding to FIG. 2, at successive stages in the manufacture thereof.
Referring to FIGS. 1-5, a one-transistor dynamic memory cell is shown which is constructed according to the invention. This cell has an N-channel access transistor 10 and a storage capacitor 11 formed in a silicon substrate 12. The transistor 10 has a metal gate 13 which is part of an elongated strip 14 forming a row (or word) line for the memory array. The drawin 15 of the transistor is part of an elongated bit line 16, perpendicular to the word line 14. The portion of the substrate shown is a very small part of a silicon bar of perhaps 150×400 mils containing 220 or 1,048,576 of these cells in an array of rows and columns, generally as shown in copending application Ser. No. 626,791, filed July 2, 1984, now U.S. Pat. No. 4,630,240 by Poteet & Chang, assigned to Texas Instruments.
The bit line 16 is buried beneath a thick thermal oxide layer 17, so the metal word line can pass directly over the bit line. Isolation laterally along the face is provided by a field plate 18, composed of polysilicon in this example, and electrically connected to the substrate voltage Vss. A hole 19 in the field plate 18 defines the area of the gate 13 of the transistor 10.
According to the invention, the capacitor 11 includes a trench 20, which is a hole etched into the silicon by an anistropic etch technique such as RIE. The trench 20 is about one micron wide and three microns deep. A thin silicon oxide layer 21 provides the capacitor dielectric, and thin silicon oxide 22 the transistor gate insulator. A thicker oxide coating 23 and a silicon nitride layer 24 provide the insulator beneath the field plate 18. The grounded field plate 18 also provides a flat surface for the metal line 14, as well as insulating the polysilicon 16 from the metal word line.
The trench 20 and the capacitor 11 are formed in a square area of field oxide 28 having a N+ region 29 beneath it, similar to the oxide 17 and bit line 16. This N+ region 29 functions as the source of the access transistor 10, and is spaced from the drain 15 by the channel length of this transistor.
A method of making the cell of FIGS. 1-5 will be described with respect to FIGS. 6-9. A silicon slice has a layer of thermal silicon oxide 23 of about 1000 Å grown on the face, then a layer 24 of silicon nitride deposited over the oxide. The oxide-nitride sandwich is patterned by photolithographic steps, leaving an exposed area 30 for the bit line 16 and an area 31 where the capacitor will be formed. An ion implant is performed to creat the N+ regions 32 and 33 which will later form the N+ bit line 16 and N+ region 29.
Referring to FIG. 7 an etch mask 34 is deposited for the purpose of defining the trench. This etch mask is silicon oxide of a thickness of about 8000 Å, formed by low pressure chemical vapor deposition. Photoresist could also be used if the etch selectivity of silicon to photoresist is high enough. A hole 35 is formed in the layer 34 by photolithography to define the trench 20. Using an anistropic etch, such as RIE (reactive ion etch) the trench 20 is created in the capacitor region to a depth of about three microns. Actually, the bottom of the trench may be narrower than the top, rather than being squared off, so the trench may be more cone-shaped than perfectly rectangular, depending upon the etch process used.
According to the invention, this trench etch is a two-step process. As seen in the enlarged view of FIG. 7a, the first etch is shallow, and removes some of the silicon in the hole 35 but also undercuts the mask 34 by etching into the region 33 by a small amount at area 36 encircling the hole. A thermal oxidation is then performed in steam to grow oxide 36a in the area 36, seen in FIG. 7b. Oxide 37 also grows in the trench, but much thinner because of the doping level of the silicon. A dip-out etch removes this oxide in the shallow trench, and so the etch can proceed to the full depth of the trench, using the oxide 36a in the area 36 as an etch stop to prevent further undercutting. The extent to which this area 36 propogates through to the final structure as a ring 36' of FIGS. 1, 2 and 4 is very slight.
The trench mask 34 is stripped off, using a conventional oxide etch such as HF since the etch will stop on the nitride 24. Turning to FIG. 8, the oxide 17 and 28 is now grown over the N+ regions 32 and 33. The oxide grows many times faster on the N+ silicon than on the very lightly doped silicon in the trench 20, so the thickness of the oxide 17 and 28 is about 4000< while only about 200 Å grows in the trench. This thin oxide is grown in the trench and stripped, then regrown as the oxide 21. A seen in FIG. 9, a layer of polysilicon is deposited by an isotropic process so it coats the sidewalls of the trench and the face of the slice to about the same thickness, to about 2500 Å. Next, an oxide layer 26 is deposited over the entire face of the slice to planarize the face and fill up the trench 20; the oxide 26 will also isolate the word line from the face. This polysilicon/oxide stack is patterned using photoresist to leave the field plate 18 and capacitor plate 25; i.e., the hole 19 is cut for the transistor 10.
Referring back to FIGS. 1-4, the oxide in the gate area is stripped and regrown as the oxide 22, and at this point thermal oxide is grown over the exposed edge of the polysilicon around the periphery of the hole 19. Then the word line is formed by depositing a layer of molybdenum over the entire face of the slice and patterning it by photolithography to leave the gate 13 and word line 14. A protective coating is added on top, (not shown) and patterned to expose bonding pads, then the slice is tested, scribed and broken into individual bars, and the bars mounted in semiconductor packages.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications to the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that te appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
Baglee, David A., Parker, Ronald
Patent | Priority | Assignee | Title |
5111428, | Jul 10 1990 | Silicon Integrated Systems Corp. | High density NOR type read only memory data cell and reference cell network |
5146425, | Oct 11 1990 | Samsung Electronics Co., Ltd. | Mist type dynamic random access memory cell and formation process thereof |
5146426, | Nov 08 1990 | North American Philips Corp. | Electrically erasable and programmable read only memory with trench structure |
5191550, | Nov 30 1989 | Seiko Epson Corporation | Dual antifuse memory device |
5202849, | Oct 20 1989 | Fujitsu Semiconductor Limited | Dynamic semiconductor memory device |
5506431, | May 16 1994 | Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications | |
5688709, | Feb 14 1996 | Bell Semiconductor, LLC | Method for forming composite trench-fin capacitors for DRAMS |
5838045, | Mar 15 1995 | International Business Machines Corporation | Folded trench and RIE/deposition process for high-value capacitors |
6081008, | Feb 14 1996 | Bell Semiconductor, LLC | Composite trench-fin capacitors for DRAM |
6175130, | Jan 20 1997 | Kabushiki Kaisha Toshiba | DRAM having a cup-shaped storage node electrode recessed within a semiconductor substrate |
6362042, | Jan 20 1997 | Kabushiki Kaisha Toshiba | DRAM having a cup-shaped storage node electrode recessed within an insulating layer |
6713814, | Aug 05 2002 | National Semiconductor Corporation | DMOS transistor structure with gate electrode trench for high density integration and method of fabricating the structure |
6777293, | Aug 05 2002 | National Semiconductor Corporation | DMOS transistor structure with gate electrode trench for high density integration and method of fabricating the structure |
6909137, | Apr 07 2003 | GLOBALFOUNDRIES Inc | Method of creating deep trench capacitor using a P+ metal electrode |
7439128, | Apr 07 2003 | GLOBALFOUNDRIES U S INC | Method of creating deep trench capacitor using a P+ metal electrode |
8587045, | Aug 13 2010 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of forming the same |
8987797, | Aug 13 2010 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of forming the same |
Patent | Priority | Assignee | Title |
3961355, | Jun 30 1972 | International Business Machines Corporation | Semiconductor device having electrically insulating barriers for surface leakage sensitive devices and method of forming |
4003036, | Oct 23 1975 | American Micro-systems, Inc. | Single IGFET memory cell with buried storage element |
4017885, | Jun 02 1972 | Texas Instruments Incorporated | Large value capacitor |
4105475, | Oct 23 1975 | American Microsystems, Inc. | Epitaxial method of fabricating single IGFET memory cell with buried storage element |
4115795, | Dec 26 1975 | Tokyo Shibaura Electric Co., Ltd. | Semiconductor memory device |
4116720, | Dec 27 1977 | SAMSUNG ELECTRONICS CO , LTD | Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance |
4164751, | Nov 10 1976 | Texas Instruments Incorporated | High capacity dynamic ram cell |
4199772, | Nov 17 1976 | Tokyo Shibaura Electric Co., Ltd. | Semiconductor memory device |
4225945, | Jan 12 1976 | Texas Instruments Incorporated | Random access MOS memory cell using double level polysilicon |
4262296, | Jul 27 1979 | General Electric Company | Vertical field effect transistor with improved gate and channel structure |
4319342, | Dec 26 1979 | International Business Machines Corporation | One device field effect transistor (FET) AC stable random access memory (RAM) array |
4327476, | Dec 07 1979 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of manufacturing semiconductor devices |
4353086, | May 07 1980 | Bell Telephone Laboratories, Incorporated | Silicon integrated circuits |
4364074, | Jun 12 1980 | International Business Machines Corporation | V-MOS Device with self-aligned multiple electrodes |
4369564, | Oct 29 1979 | American Microsystems, Inc. | VMOS Memory cell and method for making same |
4397075, | Jul 03 1980 | International Business Machines Corporation | FET Memory cell structure and process |
4412237, | Dec 30 1977 | Fujitsu Limited | Semiconductor device |
4432006, | Aug 30 1979 | Fujitsu Limited | Semiconductor memory device |
4434433, | Feb 21 1977 | Zaidan Hojin Handotai Kenkyu Shinkokai | Enhancement mode JFET dynamic memory |
4462040, | May 07 1979 | International Business Machines Corporation | Single electrode U-MOSFET random access memory |
4472240, | Aug 21 1981 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
4476623, | Oct 22 1979 | International Business Machines Corporation | Method of fabricating a bipolar dynamic memory cell |
4536785, | Aug 26 1983 | One transistor dynamic random access memory | |
4568958, | Jan 03 1984 | GENERAL ELECTRIC COMPANY A CORP OF | Inversion-mode insulated-gate gallium arsenide field-effect transistors |
4630088, | Sep 11 1984 | Kabushiki Kaisha Toshiba | MOS dynamic ram |
4636281, | Jun 14 1984 | Commissariat a l'Energie Atomique | Process for the autopositioning of a local field oxide with respect to an insulating trench |
4649625, | Oct 21 1985 | International Business Machines Corporation | Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor |
4650544, | Apr 19 1985 | Advanced Micro Devices, Inc. | Shallow groove capacitor fabrication method |
4651184, | Aug 31 1984 | Texas Instruments Incorporated; TEXAS INSTRUMENTS INCORPORATED A CORP OF DE | Dram cell and array |
4670768, | Dec 16 1983 | Hitachi, Ltd. | Complementary MOS integrated circuits having vertical channel FETs |
4672410, | Jul 12 1984 | Nippon Telegraph & Telephone | Semiconductor memory device with trench surrounding each memory cell |
4673962, | Mar 21 1985 | Texas Instruments Incorporated | Vertical DRAM cell and method |
4683486, | Sep 24 1984 | Texas Instruments Incorporated | dRAM cell and array |
4702795, | May 03 1985 | Texas Instruments Incorporated; TEXAS INSTRUMENTS INCORPORATED, A DE CORP | Trench etch process |
4704368, | Oct 30 1985 | International Business Machines Corporation; INTERNATIONAL BUSINESS MACHINES CORPORATION, A CORP OF NY | Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor |
4717942, | Jul 29 1983 | NEC Electronics Corporation | Dynamic ram with capacitor groove surrounding switching transistor |
4751557, | Mar 10 1982 | Hitachi, Ltd. | Dram with FET stacked over capacitor |
4751558, | Oct 31 1985 | International Business Machines Corporation | High density memory with field shield |
DE2706155, | |||
DE3508996, | |||
DE3525418, | |||
EP118878, | |||
EP167764, | |||
EP176254, | |||
EP186875, | |||
EP198590, | |||
GB2002958, | |||
GB2168195, | |||
JP55133574, | |||
JP5651854, | |||
JP59141262, | |||
JP6012752, | |||
JP60213053, | |||
JP60261165, | |||
JP6136965, | |||
JP6173366, |
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