Integrated circuit having permanent adjustment circuitry which requires low adjustment current

Abstract

An integrated circuit resistor adjustment network with resistors (R1, R₂, R₃, R₄) which may be paralleled by trimming resistors (R5, R7, R6, R8, respectively) upon electrical "zapping" of zener diodes (Z1, Z2, Z3, Z4, respectively) connected in series with the trimming resistors. The zener diodes (Z1, Z4 or Z2, Z3) are connected in inverse series via inverse paralleled diodes (D1, D2 or D3, D4 respectively) which are non-conductive during normal operation, but conduct during higher voltage zapping operation to permit the currents for zapping the zener diodes to bypass the resistors. By having the trimming resistors in two branches (R1, R5, R4, R6 and R2, R7, R3, R8 respectively) so arranged that in one branch a resistor of value 4R may be paralleled with a 1R resistor and an 8R resistor may be paralleled with a 2R resistor, and in the other branch, a 4R resistor may be paralleled with an 2R resistor and an 8R resistor may be paralleled with a 1R resistor, offsets can be trimmed in either direction in approximately equally spaced steps.

Description

This is a continuation of application Ser. No. 637,513 filed Aug. 3, 1984, now abandoned.

The present invention relates generally to integrated circuits, especially packaged integrated circuits, such as operational amplifiers, comparators, instrumentation amplifiers, sample and hold circuits, as well as other linear devices, and more particularly to a technique for making adjustments to these types of devices, both at wafer testing and after the devices have been packaged.

The permanent adjustment at wafer testing of linear integrated circuit parameters is a well-established procedure. By shorting out one or more predesigned zener diodes using any number of readily available terminals (commonly referred to as "Zener Zapping") and/or by carrying out other suitable techniques such as laser trimming, prepackaging adjustments can be made. However, during assembly, the integrated circuit undergoes slight changes due to the high temperatures and stresses introduced during and as a result of this packaging. This is especially true when plastic and hermetic dual inline packages are used. As a result, some of the advantages of wafer test trimming are negated and, because of the packaging, the prepackaging techniques are not available.

One typically used post-packaging technique which compensates for manufacturing errors including those resulting from the packaging process is to provide internal circuitry cooperating with external trim terminals. The end user connects these terminals to an external potentiometer to adjust a given parameter, for example input offset voltage, to zero or to its optimum value. While this approach is generally satisfactory, it can be inconvenient to the extent that the potentiometer must itself be adjusted if, for example, the integrated circuit it is connected to become defective, requiring a replacement. At the same time, it has been difficult heretofore to make any worthwhile permanent adjustments to the integrated circuit after packaging since only a limited number of terminals are available.

Other techniques for adjusting integrated circuits, both in the wafer testing period and after the circuits have been packaged, are described in U.S. Pat. Nos. 4,225,878 (Dobkin) and 4,412,241 (Nelson). Each of these patents uses what may be referred to as "back-to-back" pairs of zener diodes and zener zapping for selectively shorting out combination of these diodes in order to make the desired adjustments. For example, in the Dobkin patent, two pairs of back-to-back zener diodes are placed in parallel relationship with four resistors. Three pads (terminals) are connected with these diodes and resistors so that any one of the diodes can be zapped (permanently shorted out) by applying a suitable source of voltage (a pulse source), properly biased, across two of the pads. This causes current (trimming pulses) to flow in the reverse biased direction across one of the diodes of the back-to-back pair, e.g., the one to be zapped and in the forward biased direction across the other diode of the pair. In the Nelson patent, pairs of straight diodes are used to couple the zener diode pairs to their pads.

In the trimming techniques described in the Dobkin and Nelson patents, each requires a relatively large amount of current, for example on the order of an ampere, in order to zap their respective zener diodes. For the reasons to be discussed hereinafter, as well as other reasons, it is not always desirable to use such high currents in an integrated circuit environment generally or for trimming purposes in particular. For the moment, it suffices to say the excessive zapping currents could damage other components making up the integrated circuit or prevent zapping from occurring at all because of excessive lateral current flow in the substrate of the IC.

In view of the foregoing, it is an object of the present invention to provide an integrated circuit having permanent adjustment circuitry which uses a zener zapping technique with back to back zener diodes but which operates at relatively low zapping current, for example, on the order of eighty milliamperes, rather than the much higher currents required in the Dobkin and Nelson patents.

A more specific object of the present invention is to provide adjustment circuitry in an integrated circuit using a zener zapping technique which includes one or more transistors functioning as zener diodes and associated passive elements, typically resistors, formed within the circuit substrate such that all or substantially all of the zapping current flows into the emitter-base junction of the zener diode to be zapped.

Another specific object of the present invention to provide a packaged integrated circuit of the general type described above, that is, one which is ultimately packaged so as to encase at least certain circuit components while providing access to these components from outside the package by means of external terminals, and particularly an integrated circuit which can be permanently altered after packaging in an uncomplicated, versatile, and reliable way using the low current zener zapping technique recited above.

Still another specific object of the present invention is to provide particular post-packaging adjustment circuitry using a low current zener zapping technique including two pairs of zener diodes in a way which can provide a fourteen fold improvement in the parameter being adjusted.

As indicated above, the integrated circuit disclosed herein may be one which is ultimately packaged so as to encase at least certain circuit components while providing access to these components from outside the package by means of external terminals. The post-packaging adjustment circuitry forming part of this circuit uses zener zapping principles to provide a means of permanently adjusting a given parameter of this integrated circuit after the latter has been packaged and, preferably, before the integrated circuit reaches the ultimate user, e.g., at the manufacturer's test site. This is accomplished by applying zapping current to a selected one or more encased zener diodes from a specific one or more of its external terminals so as to permanently short out the selected diode or diodes in a way which provides the desired adjustment to the overall circuit.

In accordance with one aspect of the present invention, the adjustment circuitry just recited uses transistors as its zener diodes to be zapped. Each zener diode has its emitter and collectors connected together and each along with associated passive element or element, e.g. resistors, are physically formed in a common tub isolated from the other zener diodes and associated passive elements. This insures that all or substantially all of the current which is provided to zap a given zener diode passes through that diode's emitter-base junction (the shorting junction) with at most minimal current passing through its collector. In this way, it is not necessary to provide more zapping current than is necessary to physically and permanently short out the selected zener diode which is typically on the order of eighty milliamps as compared to an ampere as required in the Dobkin and Nelson patents. As a result of this low current zapping capability, the adjustment circuitry disclosed herein may be taken advantage of in a modified form at wafer testing also.

In an actual working embodiment of the present invention the packaged integrated circuit is one which includes two balanced inputs such as an operational amplifier, a comparator, and the like and the particular parameter to be adjusted is, for example, offset voltage. This particular circuit also includes typical trim terminals for use with an external potentiometer in the manner described above, and a terminal for supplying operating voltage to the circuit. The post-packaging adjustment circuitry includes a pair of back-to-back transistors (functioning as the zener diodes to be zapped) and associated resistors designed into each input side of the integrated circuit, each transistor having its emitter and collector tied together and formed in its own tub with an associated resistor or resistors. So long as these zener diodes remain operative (that is, function as zener diodes), the post-packaging adjustment circuitry remains balanced and does not alter in any way the given parameter in question. However, the post-packaging adjustment circuitry is designed such that either one of the zener diodes on each side of the integrated circuit can be permanently shorted out by applying relatively low level current pulses, for example, in the eighty milliampere range, through it from the voltage supply terminal to an associated trim terminal or from the trim terminal to the voltage supply terminal, depending on which zener diode is being shorted out.

In addition to the four zener diodes, the post-packaging adjustment circuitry includes a specific network of associated resistors which are incorporated into or eliminated from both sides of the integrated circuit depending upon which zener diodes are permanently shorted out. In a preferred embodiment of the present invention, these resistors are selected in combination with four zener diodes, so that as much as a fourteen fold improvement can be made in the given parameter being adjusted. At the same time, even if both zener diodes making up a back-to-back pair are shorted out, the adjustment circuitry is designed so that this does not short out the corresponding trim terminal to the positive voltage supply. As a result, the trim terminals can be subsequently used in the conventional manner by the end user.

In another actual working embodiment of the present invention at wafer test, the integrated circuit is one which includes two balanced inputs such as an operational amplifier, a comparator, and the like and the particular parameter to be adjusted is, for example, offset voltage. This particular circuit also includes test pads which can be contacted during wafer test. The wafer test adjustment circuitry includes multiple pairs of back-to-back transistors (functioning as the zener diodes to be zapped) and associated resistors designed into each input side of the integrated circuit, each transistor having its emitter and collector tied together and formed in its own tub with an associated resistor or resistors. So long as these zener diodes remain operative (that is, function as zener diodes), the adjustment circuitry remains balanced and does not alter in any way the given parameter in question. However, the adjustment circuitry is designed such that either one of the zener diodes on each side of the integrated circuit can be permanently shorted out by applying relatively low level current pulses, for example, in the eighty milliampere range through the test pads.

Other objects and features of the present invention will be described in more detail hereinafter in conjunction with the drawings wherein:

FIG. 1 schematically illustrates part of a packaged integrated circuit including post-packaging adjustment circuitry designed in accordance with the present invention; and

FIGS. 2a-2d and 3a-3d schematically illustrate how the post-packaging circuitry of FIG. 1 functions to alter a given parameter of the overall integrated circuit shown in FIG. 1.

FIG. 3 shows a top view of an integrated circuit structure that may be used.

FIG. 4 schematically illustrates part of the integrated circuit including wafer test adjustment circuitry designed in accordance with the present invention.

Referring now to FIG. 5, R11 should equal R12 for balance. The presence of R11 and R12 increases the adjustment range with an external potentiometer. For calculation purposes, in the equations above R11 is added to R9, R12 is added to R10.

As indicated above, any one or all of the zener diodes Z1-Z4 can be permanently shorted out, or a combination thereof, by utilizing three external terminals only, specifically the two trim terminals T1 and T2 and the voltage supply terminal V+ in the case of the specific integrated circuit illustrated. At the same time, this does not prevent the trim terminals from being used in the conventional way, even if all of the zener diodes are permanently shorted out since the trim terminals are never shorted to the voltage supply terminal. As a result, the present invention is especially suitable for use in a post-packaging adjustment procedure. Because four zener diodes can be permanently shorted out by means of three terminals only, an otherwise standard integrated circuit of the general type described above, that is, one having a pair of trim terminals and a voltage supply terminal can be designed with these four zener diodes in the manner illustrated in FIG. 1 along with the described resistor networks in order to provide as much as a fourteen fold improvement in the given parameter being adjusted. By valuing the various resistors making up these networks in the manner indicated, a truth table can be made and incorporated into a computer program to determine exactly which zener diode or combination of zener diodes Z1-Z4 must be shorted out to achieve a desired change in the parameter being adjusted.

While a post-packaging adjustment procedure has been described in conjunction with the present invention and particularly the low current zapping technique disclosed herein it is to be understood that this latter technique is also useful in making adjustment at wafer sort. In this case it would not be necessary to limit the circuitry to three terminals, e.g., two trim terminals and a voltage supply terminal.

The circuit of FIG. 4 functions in a similar manner to FIG. 1 modified for specific adjustment at wafer test. Multiple back to back diodes (Z5-Z9) and their associated resistors (R13-R18) are contacted by test pads T1, T2, P3, P4, P5. T1 and T2 can be the same trim terminals as in FIG. 1, thus only three additional test pads are required. In the specific example of FIG. 4, thirty two times improvement can be achieved by shorting an appropriate combination of Z5 through Z9.

The uniqueness of the innovation, however, lies in the way the emitter and collector of each transistor are tied together and formed in its own isolation tub with associated resistors, as illustrated by the dotted enclosures in FIG. 4, and previously discussed in conjunction with FIGS. 1 and 3. This connection ensures that all the zapping current will enter the emitter-base junction to be zapped and the resistor parallel with it.

The circuit of FIG. 4 can be generalized to use more (or less) back to back diodes. For example adding two more zeners, two resistors of 16R and 32R (and changing R18 to 64R) and one more contact pad, increases the theoretical improvement from thirty two times to one hundred twenty eight times. These back-to-back zener diodes operate in the same manner discussed above with respect to FIG. 1. However, because the circuit of FIG. 4 is at wafer test, when two back-to-back zener diodes are zapped their associated terminals are shorted together while in the post packaging circuit of FIG. 1, the trim terminals are not shorted out to the positive supply.

Claims

1. A packaged integrated circuit including a substrate, circuit components including two zener diodes and four resistors supported by said substrate, each of said zener diodes having an anode terminal and a cathode terminal, packaging means cooperating with said substrate so as to encase said components and a plurality of terminals including a voltage supply terminal and a trim terminal located outside said packaging means but cooperating with said circuit components for providing electrical access thereto, the improvement comprising:

a post packaging adjustment subcircuit including said two zener diodes and said four resistors, the first of said four resistors being connected in series between said voltage supply terminal and a first node, a first one of said zener diodes being connected in series between said voltage supply terminal and a second node, a second of said four resistors being connected in series between said first node and said second node, a third of said four resistors being connected in series between said first node and said trim terminal, the other of said zener diodes being connected in series between said trim terminal and a third node, and the fourth resistor being connected in series between said third node and said first node, the terminal of said first zener diode which is connected to said voltage supply terminal being of the same polarity as that terminal of the other zener diode which is connected to said trim terminal, whereby the resistance of said subcircuit measured between said voltage supply terminal and said trim terminal can be set to one of four different values by passing a current between said voltage supply terminal and said trim terminal to electrically short-circuit one or both of said two zener diodes if adjustment is desired, said subcircuit also including an arrangement of diodes connected between said second and third nodes such that during the short-circuiting of one or both of said zener diodes a low resistance path is provided through the arrangement of diodes and said zener diodes between said voltage supply terminal and said trim terminal.

2. The improvement according to claim 1 wherein said first diode is a transistor having its base and collector connected with said second node and its emitter connected with said third node, and wherein said second diode is a transistor having its base and collector connected to said third node and its emitter connected to said second node.

3. The improvement according to claim 1 wherein the resistance of said first resistor is twice the resistance of said third resistor, wherein the resistance of said second resistor is four times the resistance of said third resistor, and wherein the resistance of said fourth resistor is eight times the resistance of said third resistor.

4. A packaged integrated circuit including a substrate, circuit components including two pairs of zener diodes and two sets of resistors with four resistors in each set supported by said substrate, each of said zener diodes having an anode terminal and a cathode terminal, packaging means cooperating with said substrate so as to encase said components and a plurality of terminals including a voltage supply terminal and two trim terminals located outside said packaging means but cooperating with said circuit components for providing electrical access thereto, the improvement comprising two post packaging adjustment subcircuits, each including:

a respective one pair of said zener diodes and a respective one set of said four resistors, the first of said four resistors of said one set being connected in series between said voltage supply terminal and a first node, a first one of said zener diodes of said one pair being connected in series between said voltage supply terminal and a second node, a second of said four resistors of said one set being connected in series between said first node and said second node, a third of said four resistors of said one set being connected in series between said first node and a respective one of said two trim terminals, the other of said zener diodes of said one pair being connected in series between said one trim terminal and a third node, and the fourth resistor of said one set being connected in series between said third node and said first node, the terminal of said first zener diode of said one pair which is connected to said voltage supply terminal being of the same polarity as that terminal of the other zener diode of said one pair which is connected to said one trim terminal, whereby the resistance of each subcircuit measured between said voltage supply terminal and its trim terminal can be set to one of four different values by passing a current between said voltage supply terminal and its trim terminal to electrically short-circuit one or both of the two zener diodes of each pair of zener diodes if adjustment is desired, each of said subcircuits also including an arrangement of diodes connected between its second and third nodes such that during the short-circuiting of one or both of said zener diodes a low resistance path is provided through the arrangement of diodes and said zener diodes between said voltage supply terminal and its trim terminal.

5. The improvement according to claim 4 wherein, in one of said two post-packaging adjustment subcircuits, the resistance of its first resistor is twice the resistance of its third resistor, the resistance of its second resistor is four times the resistance of its third resistor, and the resistance of its fourth resistor is eight times the resistance of its third resistor, and in the second set of two sub-circuits, the resistance of said first resistor is twice the resistance of said third resistor, a resistance of said second resistor is eight times the resistance of said third resistor, and the resistance of said fourth resistor is four times the resistance of said third resistor.

6. The improvement according to claim 5 wherein the first diode in each of said sub-circuits is a transistor having its base and collector connected with the second node of that sub-circuit and its emitter connected with a third node of that sub-circuit, and wherein the second diode in each of said sub-circuits is a transistor having its base and collector connected to the third node of that sub-circuit and its emitter connected to the second node of said sub-circuit.

7. A packaged integrated circuit including a substrate, circuit components including two zener diodes and five resistors supported by said substrate, each of said zener diodes having an anode terminal and a cathode terminal, packaging means cooperating with said substrate so as to encase said components and a plurality of terminals including a voltage supply terminal and a trim terminal located outside said packaging means but cooperating with said circuit components for providing electrical access thereto, the improvement comprising:

a post packaging adjustment subcircuit including said two zener diodes and said five resistors, the first of said five resistors being connected in series between said voltage supply terminal and a first node, a first one of said zener diodes being connected in series between said voltage supply terminal and a second node, a second of said five resistors being connected in series between said first node and said second node, a third of said five resistors being connected in series between said first node and a third node, a fourth of said five resistors being connected in series between said third node and said trim terminal, the other of said zener diodes being connected in series between said trim terminal and a fourth node, and the fifth resistor being connected in series between said third node and said fourth node, the terminal of said first zener diode which is connected to said voltage supply terminal being of the same polarity as that terminal of the other zener diode which is connected to said trim terminal, whereby the resistance of said subcircuit measured between said voltage supply terminal and said trim terminal can be set to one of four different values by passing a current between said voltage supply terminal and said trim terminal to electrically short-circuit one or both of said two zener diodes if adjustment is desired, said subcircuit also including an arrangement of two diodes connected between said second and fourth nodes such that during the short-circuiting of one or both of said zener diodes a low resistance path is provided through the arrangement of diodes and said zener diodes between said voltage supply terminal and said trim terminal. 8. The improvement according to claim 7 wherein said first diode is a transistor having its base and collector connected with said second node and its emitter connected with said fourth node, and wherein said second diode is a transistor having its base and collector connected to said fourth node and its emitter connected to said second node. 9. The improvement according to claim 7 wherein the resistance of said first resistor is twice the resistance of said fourth resistor, wherein the resistance of said second resistor is four times the resistance of said fourth resistor, and wherein the resistance of said fifth resistor is eight times the resistance of said fourth resistor. 10. A packaged integrated circuit including a substrate, circuit components including two pairs of zener diodes and two sets of resistors with five resistors in each set supported by said substrate, each of said zener diodes having an anode terminal and a cathode terminal, packaging means cooperating with said substrate so as to encase said components and a plurality of terminals including a voltage supply terminal and two trim terminals located outside said packaging means but cooperating with said circuit components for providing electrical access thereto, the improvement comprising two post packaging adjustment subcircuits, each including:

a respective one pair of said zener diodes and a respective one set of said five resistors, the first of said five resistors of said one set being connected in series between said voltage supply terminal and a first node, a first one of said zener diodes of said one pair being connected in series between said voltage supply terminal and a second node, a second of said five resistors of said one set being connected in series between said first node and said second node, a third of said five resistors of said one set being connected in series between said first node and a third node, a fourth of said five resistors of said one set being connected in series between said third node and a respective one of said two trim terminals, the other of said zener diodes of said one pair being connected in series between said one trim terminal and a fourth node, and the fifth resistor of said one set being connected in series between said third node and said fourth node, the terminal of said first zener diode of said one pair which is connected to said voltage supply terminal being the same polarity as that terminal of the other zener diode of said one pair which is connected to said one trim terminal, whereby the resistance of each subcircuit measured between said voltage supply terminal and its trim terminal can be set to one of four different values by passing a current between said voltage supply terminal and its trim terminal to electrically short-circuit one or both of the two zener diodes of each pair of zener diodes if adjustment is desired, each of said subcircuits also including an arrangement of diodes connected between its second and fourth nodes such that during the short-circuiting of one or both of said zener diodes a low resistance path is provided through the arrangement of diodes and said zener diodes between said voltage supply terminal and its trim terminal. 11. The improvement according to claim 10 wherein, in one of said two post-packaging adjustment subcircuits, the resistance of its first resistor is twice the resistance of its fourth resistor, the resistance of its second resistor is four times the resistance of its fourth resistor, and the resistance of its fifth resistor is eight times the resistance of its fourth resistor, and in the second set of two sub-circuits, the resistance of said first resistor is twice the resistance of said fourth resistor, a resistance of said second resistor is eight times the resistance of said fourth resistor, and the resistance of said fifth resistor is four times the resistance of said fourth resistor. 12. The improvement according to claim 10 wherein the first diode in each of said sub-circuits is a transistor having its base and collector connected with the second node of that sub-circuit and its emitter connected with a fourth node of that sub-circuit, and wherein the second diode in each of said sub-circuits is a transistor having its base and collector connected to the fourth node of that sub-circuit and its emitter connected to the second node of said sub-circuit.