A digital proportional-integral controller for controlling the speed of a d.c. electric motor in a copying machine and synchronizing it with the speed of another motor in the copying machine. The proportional stage and the integral stage of the controller are each formed by an up/down counter which counts up or down depending upon the pulses of the actual speed signal and the reference signal. logic circuits are provided for processing the speed signal pulses and the reference signal pulses before they are fed to the up/down counters. The controller also has an interface for a two-wire bus system over which data and commands for adjusting and varying the control parameters can be input.
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16. An electronic integral controller for controlling the speed of an electric motor in accordance with a reference signal whose frequency represents the desired output speed of the controlled electric motor and a speed signal whose frequency represents the actual output speed of the controlled electric motor, comprising:
an integrator circuit for generating an I-control signal corresponding to the time integral of the difference between the frequencies of the reference signal and the speed signal and wherein the integrator circuit comprises a logic circuit connected to an up/down counter such that the logic circuit: (1) delivers an upward a downward counting pulse to the counter on each rising flank of the speed signal; (2) delivers a downward an upward counting pulse to the counter on each rising flank of the reference signal; (3) generates a read signal after one cycle of the speed signal and the reference signal to output the value of the counter which is the I-control signal; (b) an addition circuit connected to the integrator circuit for generating a sum signal corresponding to a predetermined weighing of the I-control signal; and (c) an output stage for controlling the motor in accordance with the sum signal of the addition circuit.
15. An electronic proportional controller for controlling the speed of an electric motor in accordance with a reference signal whose frequency represents the desired output speed of the controlled electric motor and a speed signal whose frequency represents the actual output speed of the controlled electric motor, comprising:
(a) a proportional circuit for generating a P-control signal corresponding to the difference between the frequencies of the reference signal and the speed signal and wherein the proportional circuit comprises a logic circuit connected to an up/down counter such that the logic circuit: (1) converts the speed signal into a standardized speed signal which changes its state on each rising flank of the speed signal; (2) converts the reference signal into a standardized reference signal which changes its state on each rising flank of the reference signal; (3) delivers a sequence of upward counting pulses to the counter in synchronism with a first clock signal when there is present a pulse of the standardized speed signal and no pulse of the standardized reference signal; (4) delivers a sequence of downward counting pulses to the counter in synchronism with the first clock signal when there is present a pulse of the standardized reference signal and no pulse of the standardized speed signal; (5) generates a read signal to output the value of the counter which is the P-control signal; and (6) generates a reset signal to reset the counter if a pulse has occurred in both the standardized speed signal and in the standardized reference signal and both standardized signals simultaneously have a pulse break; (b) an addition circuit connected to the proportional circuit for generating a sum signal corresponding to a predetermined weighting of the P-control signal; and (c) an output stage for controlling the motor in accordance with the sum signal of the addition circuit.
1. An electronic proportional-integral controller for controlling the speed of an electric motor in accordance with a reference signal whose frequency represents the desired output speed of the controlled electric motor and a speed signal whose frequency represents the actual output speed of the controlled electric motor, comprising:
(a) a proportional circuit for generating a P-control signal corresponding to the difference between the frequencies of the reference signal and the speed signal and wherein the proportional circuit comprises a logic circuit connected to an up/down counter such that the logic circuit: (1) converts the speed signal into a standardized speed signal which changes its state on each rising flank of the speed signal; (2) converts the reference signal into a standardized reference signal which changes its state on each rising flank of the reference signal; (3) delivers a sequence of upward counting pulses to the counter in synchronism with a first clock signal when there is present a pulse of the standardized speed signal and no pulse of the standardized reference signal; (4) delivers a sequence of downward counting pulses to the counter in synchronism with the first clock signal when there is present a pulse of the standardized reference signal and no pulse of the standardized speed signal; (5) generates a read signal to output the value of the counter which is the P-control signal; and (6) generates a reset signal to reset the counter if a pulse has occurred in both the standardized speed signal and in the standardized reference signal and both standardized signals simultaneously have a pulse break; (b) an integrator circuit which uses the speed signal and the reference signal for generating an I-control signal corresponding to the time integral of the difference between the frequencies of the reference signal and the speed signal; (c) an addition circuit connected to both the proportional circuit and the integrator circuit for generating a sum signal corresponding to the sum or the weighted sum of the P-control and I-control signals; and (d) an output stage for controlling the motor in accordance with the sum signal of the addition circuit.
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The present invention relates to an electronic proportional-integral controller for controlling the speed of an electric motor, more particularly a d.c. motor, in accordance with the frequency of a reference signal. Controllers of this kind are used for controlling the various drive units in a copying machine.
It is important that the movements of various units in a copying machine such as the optical scanning system, the image recording medium, the paper transport system and the like, should be accurately synchronized with one another to produce high quality copies. Generally, this synchronization is achieved by driving all the units or components of the copying machine by a common drive unit having a single transmission. Since, however, this necessitates an expensive transmission design, it is desirable to separate the drives for the various units so that the copying machine construction is simplified, the ease of servicing is increased and the inert masses required to be moved during the operation of the copying machine are reduced. The separate drives for the various units, however, have to be synchronized electronically. One way this can be achieved is by sensing the speed of one of the drive units, such as the motor for the image recording medium, and using it to generate a reference signal, which is used to control the speeds of the drives of the other units.
Separate drives for the various units necessitate controllers which can easily be adjusted at any time to the conditions of the control system such as the power of the drive motor, the inertia of driven parts and the like. The controllers also need to allow substantially immediate adjustment of the speed of the controlled motor or drive to the reference frequency within close tolerances.
Typically these controllers have a speed sensor for generating a speed signal the frequency of which represents the motor output speed, a proportional circuit which generates a proportional control (P-control) signal corresponding to the difference between the frequencies of the reference signal and of the speed signal, an integrator which generates an integral control (I-control) signal corresponding to the time integral of the difference between the frequencies of the reference signal and of the speed signal, an adder, which generates an output signal corresponding to the sum or the weighted sum of the two control signals (P-control and I-control), and an output stage for controlling the motor in accordance with the adder output signal. Controllers of this kind can be made using either analog or digital components.
Although analog controllers allow rapid signal processing and hence a low delay time for the control system, they have the disadvantages that the accuracy of the control is limited and the adjustment to the conditions of use at any time is a relatively laborious operation requiring the balancing of resistors and the like.
In contrast, digital control systems have high accuracy and little liability to trouble while being relatively cheap. In digital control systems, the input variables such as the frequency of the reference signal and the scanned actual speed signal are usually quantified and then arithmetic operations are carried out to form the set-value/actual-value difference used to generate the proportional component and the integral component, and to form the final control signal. Since these operations require some computer time, the control time is relatively long. It would be desirable, therefore, to have a digital control system which had a short control time.
Generally, the present invention provides a versatile digital proportional-integral controller having a short control time and a high long-term stability, and which can be adjusted to different conditions of use within a wide range. As a result of these properties, the controller according to the present invention makes it possible to provide a copying machine with separate drives for the various subsystems while guaranteeing accurate synchronization of the subsystems.
According to the present invention, a proportional-integral controller uses a speed signal from the controlled motor and a reference signal from a reference signal generator, preferably a reference drive, to generate a motor control signal. The controller has a proportional circuit and an integrator circuit which are each formed by a logic circuit and an up/down counter. The counters receive the up and down counting pulses from the preceding logic circuit which directly utilizes the speed signal and the reference signal.
The proportional circuit is based on the operating principle that the speed signal and the reference signal are converted to standardized signals, wherein the pulse width of each corresponds to the cycle time of the original speed signal or reference signal, respectively. If, during the speed signal cycle, the reference signal cycle has not yet started or has already ended, the counter counts up at a predetermined clock frequency. If, conversely, during the reference signal cycle, the speed signal cycle has not yet started or has already ended, the counter counts down at the same frequency. On completion of the last of the two cycles, the contents of the counter is used for further signal processing and the counter is reset so that a new counting cycle can start. In this way, an output signal proportional to the difference between the cycle times is generated at very short intervals on the order of magnitude of the speed signal and reference signal cycles.
The counter of the integrator circuit counts up on each rising flank of the speedspeed signal fmu and reference signal fru reference signal fru and speed signal fmu . Clock signal fs1 controls flipflops 12 and 14 which respectively receive output signal Q11 of flipflop 11 and output signal Q13 of flipflop 13. Upward counting input UP of counter 300 is connected to a circuit of logic gates 304 which have a NAND function. The input signals of circuit 304 are: inverted output signal Q12 of flipflop 12; clock signal fs2 ; speed signal fmu reference signal fru ; a signal b; and a signal ov'. The significance of signals b and ov' will be discussed later. At this stage it will be assumed that these signals have the value 1. When the state of signal fmu fru changes from 0 to 1, an upward counting pulse of logic 0 is generated on the next clock pulse fs2. Before the arrival of the next clock pulse fs2, signal Q12 drops so that the other counting pulses are suppressed until the associated cycle of signal fmu fru is over. Thus only exactly one counting pulse is generated for each speed reference signal cycle.
Similarly, a circuit of logic gates 306 which have a NAND function generate exactly one downward counting pulse for each cycle of reference signal fru speed signal fmu if input signals a and uv' have the value 1. Logic circuit 306 functions in a similar manner to logic circuit 304.
The signals a=fmu fmu .Q12 and b=fru fmu .Q14 (where represents a logic AND) prevent counter 300 from simultaneously receiving an upward and a downward counting pulse. Signal a assumes the value 0 when the conditions for an upward counting pulse are present, and in that case blocks the generation of a downward counting pulse. Signal b assumes the value 0 when the conditions are present for a downward counting pulse and in that case blocks the generation of the upward counting pulse. In addition, signals a and b control the transmission of read command e1 to output stage ET. Read command e1 is generated by an AND gate 310 which receives clock signal fs1 and signals a and b after they have been processed through a NAND gate 308.
Signals ov' and uv' are generated by logic circuits 312 and 314, respectively, and are intended to protect counter 300 from exceeding the top capacity limit or bottom capacity limit, respectively. Signal ov' generated by logic circuit 312 is dependent not only upon output signals dI1 -dI8 of counter 300, but also upon signals c and d. When the multiplication factor in shifter S1 is set to 21 or 22 by signals c and d, the capacity of counter 300 is artificially reduced by one or two binary digits respectively to prevent the capacity from being exceeded in shifter S1. If the capacity of counter 300 is exceeded or undershot, a NAND gate 316 delivers a signal L which is transmitted as a fault signal to the superior control system.
Shifter S1 is built substantially of NAND gates. The circuit details and configuration are typical and will be clear from FIG. 8.
If controls signals c and d both have the value 0 or 1, the 8-bit signal dI indicating the contents of the counter 300 remains unchanged (i.e. dS1 =dI). If, however, signal c has the value 0 and signal d has the value 1, integral signal dI is multiplied by the factor 21 (i.e. dS11 =0, dS12 =dI1, dS13 =dI2, etc). If signal c has the value 1 and signal d has the value 0, integral signal dI is multiplied by the factor 22 (i.e. dS11 =0, dS12 =0, dS13 =dI1, dS14 =dI2, etc).
Shifter S2 also receives control signals c and d and causes amplitude signal dA to vary in accordance with the variation of integral signal dI. Control signals c and d, therefore, provide a simple means for adjusting the weighting of the proportional component and the integral component in the controller according to the present invention in order to adapt the control characteristic to the specific control system.
The present controller also affords the possibility of setting different speeds for the controlled motor. The division ratio of the frequency divider unit FRD can be varied, thereby reducing the frequency of reference signal fr. As can be seen in FIG. 2, frequency divider unit FRD comprises a frequency divider D1, which can be operated with selectable division ratios between 1:1 and 1:255. Two different division ratios for frequency divider D1 can be stored in two shift registers Df1 and Df2. Switching between the two shift registers Df1 and Df2 is possible by means of a binary control signal a1 so that frequency divider D1 operates either with the division ratio stored in shift register Df1 or with the division ratio stored in shift register Df2.
Clock generator D comprises an oscillator OSC which delivers a signal fc1 at a frequency of 10 MHz to a frequency divider D2. Frequency divider D2 delivers a number of parallel frequency signals which are produced by frequency division with different division ratios in the range from 1:4 to 1:56 from the frequency of signal fc1. A multiplexer M1 receives seven different frequency signals from frequency divider D2 and selects one of these frequency signals depending upon a 3-bit signal DFm1.
The selected frequency signal fpwm is fed as a clock signal to output stage ET. Another multiplexer M2 receives fifteen different signals from frequency divider D2 and selects one of these fifteen frequency signals depending upon a 4-bit signal DFm2. The selected frequency signal is fed to a frequency divider D3. Frequency divider D3 comprises a flipflop which halves the frequency of the selected frequency signal delivered by multiplexer M2. Phase-shifted clock signals fs1 and fs2 are generated by a NOR combination of the output signal of multiplexer M2 and the inverting and non-inverting output of the flipflop in frequency divider D3.
Signals DFm1 and DFm2, which determine what frequencies are selected as the outputs of multiplexers M1 and M2, are delivered either by a shift register Df3 or a shift register Df4. The selection of shift register Df3 or Df4 is controlled by a signal a1 which also controls the selection of shift registers Df1 and Df2 of frequency divider unit FRD.
In this way, when PI-controller 100 is switched to a different speed, clock signals fpwm, fs1 and fs2 are also automatically adapted to the new conditions so that controller adjustment is maintained. In particular, the change of clock frequencies fs1 and fs2 also adjusts the proportionality factor in proportional circuit P since clock frequency fs2 forms the counting frequency of counter 200 in proportional circuit P.
As can be seen in FIG. 9, shift registers Df1, Df2, Df3, Df4 and amplitude register A are connected in series and to a common clock signal SCL. On initialization of the controller, the data to be stored in these registers is fed in the form of a serial data signal SDA and is transmitted through shift registers Df1 -Df4 and A. Upon operation of controller 100, the contents of shift registers Df1 or Df2 are transmitted to frequency divider D1 and signals DFm1 and DFm2 which control multiplexers M1 and M2 are transmitted from shift register Df3 or Df4. The transmission of signals from Df1 or Df2 and Df3 or Df4 is effected via electronic switches which are controlled alternately by signal a1.
An advantageous modification of the preferred embodiment described herein is possible by forming shift registers Df1 -Df4 and amplitude register A as parallel registers to which the data is fed for storage in parallel via a bus.
Command signal a1, serial data signal SDA and clock signal SCL are generated by command unit COMM. Command unit COMM also generates control signals c and d for shifters S1 and S2 and reset signals R1 -R5 for resetting the individual controller components, and a signal h which controls the direction of rotation of the motor.
Command unit COMM communicates with a superior control system via an I2 C-bus. This bus is a two-wire data transmission system over which a data signal and a clock signal, or a control signal are transmitted. During transmission of data, the data and clock signal are so modulated that the signals in the two wires of the bus always have opposite polarity. However, during transmission of control signals which, for example, indicate the start or the end of a data transmission, the signal is so modulated that the two wires of the bus have the same polarity. In this way it is possible to distinguish between data signals and control or command signals.
Command unit COMM comprises an I2 C interface which during data transmission recovers the clock signal and the data signal from the modulated signals of the two bus channels. On initialization of the controller, the clock signal is transmitted to shift registers Df1 -Df4 and A and the next five data bytes are read serially into these shift registers. Further commands such as commands for switching the controller on and off, changing the speed (change of state of signal a1) and for changing the multiplication factor of shifters S1, S2 (change of state of signals c and d) can then be transmitted via the I2 C bus. The commands or data transmitted to the command unit COMM can also be acknowledged via the I2 C bus. Similarly, status signal L which indicates the status of counter 300 of integrator I can be sent back to the superior control unit.
Command unit COMM also comprises I/O ports h, i, j and k. Controller 100, therefore, can alternatively be controlled via parallel lines connected to I/O ports h, i and j. I/O ports h, i, j and k also serve for carrying out test operations. If the signal 1 is applied to port i, command unit COMM delivers clock signals fs1, fs2 and fpwm to ports h, k and j, respectively. If the signal 0 is applied to the port i, synchronized speed signal fmu and reference signal fru are sent back via ports h and k, respectively.
The controller can also be adjusted to operate only as a P-controller or only as an I-controller.
The invention is not limited to the above-described presently preferred embodiment. With the teachings disclosed herein, one skilled in the art will be able to carry out numerous modifications of the present invention which has been shown and described with particularity. Such modifications are also embodied within the scope and protection of the following claims.
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