High electron mobility single heterojunction semiconductor devices

Abstract

A thin electron accumulation layer is generated along a heterojunction between two kinds of semiconductors each of which has a different electron affinity. This electron accumulation layer suffers less ionized-impurity scattering, because the thickness does not exceed the spread of an electron wave. A channel constituted with this electron accumulation enjoys an excellent electron mobility, particularly at cryogenic temperatures. A layer configuration fabricated with two different semiconductors having different electron mobilities and a similar crystal lattice coefficient, and including a single heterojunction, is effective to improve electron mobility. Such a layer configuration can be employed for production of an active semiconductor device with high electron mobility, resulting in high switching speed. The semiconductor devices including a FET, a CCD, etc., exhibit an excellent transfer conductance Gm.

Description

BACKGROUND OF THE INVENTION

This invention relates to semiconductor devices with high electron mobility, more particularly to FETs utilizing electrons accumulated in the neighborhood of a single heterojunction due to the difference in electron affinity between the two different kinds of semiconductors which form a single heterojunction. More specifically, this invention relates to active semiconductor devices each of which has a single heterojunction formed between a pair of layers fabricated with two different semiconductors having different electron affinities from each other and which employs a field effect caused by one or more gates for regulation of the concentration of electrons accumulated along the single heterojunction due to the difference in electron affinity, resulting in the impedance of a channel formed with the accumulated electrons between an input and an output terminal being regulated depending on the voltage applied to the one or more gates.

The field effect transistors available in the prior art are classified into three types, including the junction gate type, the insulated gate type and the Schottky barrier type. Out of these three families, the insulated gate type and the Schottky barrier type (Metal semiconductor or MES) are rather easy to produce in the form of integrated circuits. Therefore, insofar as the integrated circuits are concerned, these two types are predominantly employed. For the purpose of improving the switching speed of the FETs, various means including decrease of geometrical dimensions are employed. However, improvement in switching speed is inherently limited by electron mobility or the speed of electrons moving in a conductive channel. In other words, improvement in electron mobility is the easiest means or even the essential means for improvement of the switching speed of a FET. It was believed, however, that electron mobility is determined by the kind of and the concentration of impurities doped into a semiconductor, temperature, etc., and that there is a limitation for improvement of electron mobility.

It is noted, however, that R. Dingle et al. have disclosed results of efforts for improvement of electron mobility which were successfully realized by a multi-layered structure of semiconductors including plural heterojunctions. Their report entitled "Electron Mobilities in Modulation-doped Semiconductor Heterojunction Superlattices" disclosed in Applied Physics Letters, Vol. 33, Pages 665 through 667 on Oct. 1, 1978 reveals that albeit the electron mobility of GaAs doped with n-type impurities at a concentration of 10¹7 /cm³ is approximately 5,000 cm² /V.sec at the temperature of 300° K., a multilayered structure fabricated by alternately growing n-doped AlGaAs layers and undoped or unintentionally doped GaAs layers allows the GaAs layers to have an electron mobility of approximately 20,000 cm² /V.sec at the temperature of 77° K. This improvement in electron mobility was realized in the electrons accumulated in the GaAs layer contiguous with the heterojunction due to the difference in electron affinity, because of the lesser ionized-impurity scattering in the undoped or unintentionally doped GaAs layer at a cryogenic temperature

SUMMARY OF THE INVENTION

An object of this invention is to provide active semiconductor devices with high electron mobility.

To attain the object mentioned above, an active semiconductor device with high electron mobility in accordance with this invention is provided with a single active heterojunction formed between a pair of layers fabricated with two different semiconductors. The two different semiconductors are selected to provide a substantial difference of their electron affinities, for example GaAs and AlGaAs. Further, the semiconductor layer having the lower electron affinity is doped with an n-type impurity. Due to the difference in electron affinity, electrons contained in the semiconductor layer having the lower electron affinities are depleted and move to the semiconductor layer having the higher electron affinity. The electrons accumulate in an extremely thin region close to the single heterojunction. These accumulated electrons provide a channel. From this viewpoint, the semiconductor layer, having a lower electron affinity and the semiconductor layer having a higher electron affinity will be referred to respectively as an electron source region and a channel region. The electrons accumulated along the single heterojunction do not spread beyond the extent of an electron wave. In other words, the entire quantity of the electrons are confined in an extremely thin region with the thickness of several tens of angstroms and are spatially separated from the doped n-type impurity atoms. This means the electrons suffer less from ionized-impurity scattering. Therefore, the mobility of the electrons is significantly improved particularly at cryogenic temperature at which the effect of ionized-impurity scattering becomes dominant in determining the electron mobility. On the other hand, the electron source region is depleted to some extent. When the thickness of the electron source region is selected to a proper magnitude, it is possible to make the electron source region entirely depleted. As a result, the electrons accumulated along the single heterojunction function as the only channel for the layer configuration consisting of an electron source region and a channel region. Accordingly, when one or more insulated gates or Schottky barrier gates together with a source and a drain are placed on the top surface of the layer configuration, a FET may be fabricated with a path of electric current limited to the channel formed on the electrons accumulated along the single heterojunction.

As described earlier, it is essential for an electron source region to be doped with n-type impurity atoms. However, a channel region can be either undoped; or unintentionally doped, or n-doped, or even p-doped, unless the positive dopant concentration is extremely high.

It is noted that the thickness of an electron source region is required to be less than a specific thickness which is determined predominantly by the kind of semiconductors employed and the temperature at which the device is employed.

The above described novel concept of the present invention for active semiconductor devices with high electron mobility may be applied various manner.

Two different layer configurations are available. One is to grow a channel region on a substrate before growing an electron source region on the channel region and placing one or more gates, a source and a drain on the layer configuration. The other is to grow an electron source region on a substrate before growing a channel region on the electron source region and further placing one or more gates, a source and a drain on the layer configuration.

The former embodiment functions as either a normally-on mode (depletion mode) or a normally-off mode (enhancement mode) depending on whether the thickness of an electron source region is larger than a specific thickness which is determined predominantly by the kind of semiconductors employed and the temperature at which the device is employed.

The latter embodiment functions as either a normally-on mode (depletion mode) or a normally-off mode (enhancement mode) depending on whether the ratio of the thickness of a channel region and the thickness of an electron source region is larger than a specific amount which is determined predominantly by the kind of semiconductors employed and the temperature at which the device is employed.

In addition to the pair of GaAs and AlGaAs, the pairs of Ge and AlGaAs, Ge and GaAs, InSb and CdTe, InAs and GaSb, etc., can be utilized.

The gate or gates can be fabricated either in the form of the Schottky barrier gate type or the insulated gate type. The essential requirements are that (i) it generates a field effect and (ii) it is effective to confine electrons depleted from the layer configuration to the interface between the gate or gates and either the electron source region or the channel region.

The substrate can be fabricated with either a semiconductor or an insulator. In either case, a single heterojunction constituting a single channel connecting a source and a drain is essential.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with its various features and advantages, can be readily understood from the following more detailed description presented in conjunction with the following drawings, in which:

FIG. 1 shows a cross-sectional view of a FET having a multilayered superlattice structure fabricated with n-doped Al₀.3 Ga₀.7 As layers and undoped GaAs layers interleaving a plurality of heterojunctions and which was produced for trial without success,

FIG. 2 shows a graph showing the source-drain voltage vs. the source-drain current characteristic determined employing the gate-source voltage as a parameter, of the FET whose layer configuration is shown in FIG. 1,

FIG. 3 shows a graph showing the electron concentration vs. the depth from the surface of the layer configuration shown in FIG. 1,

FIG. 4 shows an energy band diagram of a layer configuration constituted with a metal layer, an Al₀.3 Ga₀.7 As layer and an undoped GaAs layer interleaving a single heterojunction between them, under thermal equilibrium,

FIG. 5 shows an energy band diagram of a layer configuration which depicts a boundary of the thickness of an n-doped AlGaAs layer which allows regulation of conductivity with a field effect caused by a metal layer, under thermal equilibrium,

FIG. 6 shows an energy band diagram corresponding to the diagram shown in FIG. 5, but showing the field effect,

FIG. 7 (a) shows an energy band diagram corresponding to FIG. 5, showing the case in which the barrier gap between a metal layer and an n-doped AlGaAs layer is larger than the barrier gap between the AlGaAs layer and a GaAs layer, under thermal equilibrium,

FIG. 7 (b) shows an energy band diagram corresponding to FIG. 5, showing the case in which the barrier gap between an n-doped AlGaAs layer and a GaAs layer is larger than the barrier gap between the AlGaAs layer and a metal layer, under thermal equilibrium,

FIG. 8 shows an energy band diagram corresponding to FIG. 7(a), showing the case in which the thickness of an n-doped AlGaAs layer is thinner; under thermal equilibrium,

FIG. 9 shows an energy band diagram showing the same layer configuration as for FIG. 8, showing the influence of a field effect,

FIG. 10 shows an energy band diagram equivalent to FIG. 4, for defining various variables,

FIG. 11 shows a cross-sectional view of a FET workable in the normally-on mode, in accordance with an embodiment of this invention,

FIG. 12 shows a cross-sectional view of a FET workable in the normally-off mode, in accordance with an embodiment of this invention,

FIG. 13 shows a cross-sectional view of a charge coupled device in accordance with this invention,

FIG. 14 shows a layer configuration and the energy band diagram of another embodiment of this invention, in which a channel region is overlaid on an electron source region, under thermal equilibrium,

FIG. 15 shows an energy band diagram equivalent to that which is shown in FIG. 14, for defining various variables,

FIG. 16 shows a cross-sectional view of a FET workable in the normally-off mode, in accordance with another embodiment of this invention,

FIG. 17 shows a cross-sectional view of a FET workable in the normally-on mode, in accordance with another embodiment of this invention,

FIG. 18 shows a graph showing the source-drain current vs. the source-drain voltage characteristic determined employing the gate-source voltage as a parameter, of the FET whose layer configuration is shown in FIG. 16,

FIG. 19 shows a graph showing the source-drain current vs. the source-drain voltage characteristic determined employing the gate-source voltage as a parameter, of the FET whose layer configuration is shown in FIG. 17.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The inventor of the present invention conceived that the above mentioned phenomenon reported by R. Dingle et al. could be utilized for improvement of electron mobility and for development of a FET with an extremely high switching speed. In the experimental work leading to the present invention, first a FET was produced comprising a multilayered superlattice structure fabricated with n-doped Al₀.3 Ga₀.7 As and undoped GaAs, as shown in FIG. 1. Referring to the same figure, plural n-doped AlGaAs layers (4) and plural undoped GaAs layers (5) are grown one after the other to form a multilayer on a GaAs substrate (3) which is a semi-insulator. Reference numerals (4') and (5') respectively show n-doped AlGaAs layers and n-doped GaAs layers for forming source and drain regions. On top of these n-doped layers, a source electrode (7) and a drain electrode (8) are placed. (These source and drain electrodes are generally referred to in the art as outputs.) A Schottky gate (6) is provided between the source (7) and the drain (8). The relations between the source-drain voltage vs. the source-drain current were measured for the above described FET, varying the gate-source voltage as a parameter. FIG. 2 shows the result of the measurement. In the same figure, the X-axis and Y-axis respectively depict the source-drain voltage V_DS and the source-drain current I_DS. The gate-source voltage V_GS is shown for each curve as a parameter.

FIG. 2 shows that the transfer conductance Gm of this FET is non-linear for the gate-source voltage V_GS. For example, the transfer conductance Gm is extremely small for the gate-source voltage range of -2.0 V≦V_Gs ≦-3.0 V. Further, The amplification characteristic is also non-linear. Therefore, it is clear that this FET cannot be applicable for practical use. In order to determine the causes of such a characteristic, the relations between the electron concentration and the depth from the top surface were measured. FIG. 3 shows the result of the measurement. The figure shows a large electron concentration for the undoped GaAs layers (5) which have a relatively larger electron affinity, and a small electron concentration for the n-type AlGaAs layers (4) which have a smaller electron affinity. Based on the fact that an increasingly larger gate-source voltage V_GS causes the electrons located at an increasingly deeper region to be involved with conduction, it was determined that the non-linear distribution of electron concentration shown in FIG. 3 is the cause for the non-linear characteristic between the transfer conductance Gm and the gate-source voltages V_GS shown in FIG. 2.

Based on the above described experimental results, it was determined that a multilayered structure of semiconductors including plural heterojunctions as shown in FIG. 1 is not appropriate for production of a semiconductor device.

Thereafter, the case was studied in which a single heterojunction is formed between two kinds of semiconductors having different electron affinities from each other. With reference to the drawings, the results of the study are described below. FIG. 4 shows the energy band diagram of a layer configuration interleaved by a single heterojunction formed between an n-type Al₀.3 Ga₀.7 As layer and an undoped GaAs layer, thermal equilibrium. Referring to the same figure, a metal layer (10) makes a Schottky contact with an n-type AlGaAs layer (1). A GaAs layer (2) forms a single heterojunction with the n-type AlGaAs layer (1). From a functional viewpoint, the GaAs layer (2) is allowed to be either undoped or n-doped to a certain extent or even p-doped to a rather less extent. Reference characters E_C, E_V and E_f respectively show the energies of the conduction band, the valence band and the Fermi level. Due to the Schottky effect, some quantity of electrons contained in the n-type AlGaAs layer (1) move into the interface between the metal layer (10) and the AlGaAs layer, leaving depletion region in the form of a layer (11) in the n-type AlGaAs layer. As a result, the energy band diagram is shaped as depicted in the same figure. In addition, due to the difference in electron affinity, some of the electrons contained in the n-type AlGaAs layer (1) move into the GaAs layer (2) across the heterojunction formed between them. As a result, the energy band diagram is shaped as depicted in the same figure. It is noted that if the thickness of the n-type AlGaAs layer (1) exceeds a certain amount, an n-type layer (13) remains between the depletion layers (11) and (12). The electrons depicted from the n-type AlGaAs layer (1) accumulate along the heterojunction, forming an electron accumulation (14) in the GaAs layer (2). As a result, the energy band diagram is shaped as depicted in the same figure. The thickness of the electron accumulation (14) does not exceed the spread of an electron wave which is tens of angstroms.

FIG. 4 shows a case in which the magnitude of the Schottky barrier between the metal layer (10) and the n-type AlGaAs layer (1) is larger than the barrier gap which appears between the GaAs layer (2) and the n-type AlGaAs layer (1) due to the difference in electron affinities. However, a certain thickness of an n-type layer (13) remains between the two depletion layers (11) and (12) which effectively keeps the two depletion layers (11) and (12) independent from each other and prevents them from interfering with each other. In other words, the electrons depleted from the depletion layer (11) accumulate along the Schottky surface, and the electrons depleted from the depletion layer (12) independently accumulate in the GaAs layer (2) along the heterojunction to form the electron accumulation (14).

This potential condition does not allow a field effect caused by a positive or negative voltage applied to the metal layer (10) to affect the electron accumulation (14). Moreover, the remaining n-type layer in which the electron mobility is relatively low forms another conductive channel between the source and drain and consequently deteriorates the linearity of the characteristics and the switching speed of the device. Therefore, it is clear that this layer configuration is not satisfactory as an active device.

The layer configuration shown in FIG. 4 should not include an N layer (13) constituting a conductive bulk region in the n-type AlGaAs layer (1), that is, the n-type AlGaAs layer (1) will include only the depletion regions or layers (11) and (12), when the thickness of the n-type AlGaAs layer is sufficiently decreased. An example of this condition is shown in FIG. 5. When a negative voltage is applied to the metal layer (10), a depletion layer spreads into the GaAs layer (2). As a result, since the energy band diagram is shaped as shown in FIG. 6, the electron concentration of the electron accumulation (14) decreases. This means that the conductivity of a channel constituted by the electron accumulation (14) formed in the GaAs layer (2) along the single heterojunction can be regulated by application of a negative potential applied to the metal layer (10).

Albeit FIGS. 5 and 6 show the case in which the Schottky barrier between the metal layer (10) and the n-type AlGaAs layer (1) is larger than the barrier gap between the GaAs layer (2) and the n-type AlGaAs layer (1) due to the difference in electron affinity, the other case in which the magnitude of the barrier gaps is reversed is also possible. In each case, a different function results. Namely, when the thickness of the n-type AlGaAs layer (1) is further decreased, two different shapes as shown in FIGS. 7 (a) and 7 (b) are available for the energy band diagram. FIG. 7 (a) shows a case in which the barrier gap between the metal layer (10) and the n-type AlGaAs (1) is larger than barrier gap which appears between the GaAs layer (2) and the n-type AlGaAs layer (1) due to the difference in electron affinity. If the thickness of the n-type AlGaAs layer (1) is further decreased, the depletion layer (12) will not appear. In this case, the concentration of the electron accumulation (14) becomes extremely small, and this thickness of the n-type AlGaAs layer (1) constitutes a boundary of the range in which the negative regulation of conductivity is possible. On the other hand, FIG. 7 (b) shows a case in which the barrier gap between the metal layer (10) and the n-type AlGaAs layer (1) is smaller than the barrier gap which appears between the GaAs layer (2) and the n-type AlGaAs layer (1) due to the difference in electron affinity. If the thickness of the n-type AlGaAs layer (1) is further decreased, the depletion layer (11) does not appear. In this case, albeit some means is necessary to confine electrons along the interface between the metal layer (10) and the n-type AlGaAs layer (1), this thickness of the n-type AlGaAs layer (1) does not constitute a boundary of the range in which the negative regulation of conductivity is possible. In other words, this thickness of the n-type AlGaAs layer (1) still allows the negative regulation of conductivity.

Referring again to FIG. 7 (a), when the thickness of the n-type AlGaAs layer (1) is further decreased, no electrons are supplied to the GaAs layer (2), and the electron accumulation (14) does not appear, as shown in FIG. 8 under thermal equilibrium. Therefore, a positive voltage applied to the metal layer (10) causes an electron accumulation (14) in the GaAs layer (2) due to the function of a capacitor constituted with the metal layer (10), the depletion layer (11) and the GaAs layer (2). As a result, the energy band diagram is changed as shown in FIG. 9. This means that a positive regulation of conductivity is possible for this layer configuration.

It has become clear that active semiconductor devices with high electron mobility can be produced by growing an n-type semiconductor layer having a smaller electron affinity on a semiconductor layer having larger electron affinity, before one or more gates of a rectifying or non-conductive material and a source and a drain are placed on the semiconductor layers.

The numerical limitations for the thickness of the n-type AlGaAs layer (1) which were referred to above will be discussed. At first, referring to FIG. 10 which is virtually identical to FIG. 4, each variable is defined below. V_D1 is the height of the potential barrier between the metal layer (10) and the n-type AlGaAs layer (1). In other words, as shown in FIG. 10, V_D1 is the potential difference between the peak in the bottom of the conduction band formed at the boundary with the control terminal and the semiconductor (AlGaAs) layer 1 and the illustrated flat portion of the bottom of the conduction band that forms when the semiconductor layer 1 is sufficiently thick to form the flat portion. As is well known, the height of the potential barrier V_D1 corresponds to the difference between the work function of the control terminal and the electron affinity of the semiconductor layer. The thickness of the depletion layer (11) is depicted by d₁. V_D2 is the height of the energy barrier in the n-type AlGaAs layer (1) at the junction with the GaAs layer (2). In other words, as with V_D1, V_D2 is the potential difference between the peak in the bottom of the conduction band formed at the heterojunction boundary in the semiconductor layer 1 and the illustrated flat portion in the bottom of the conductor band, as shown in FIG. 10. The thickness of the depletion layer (12) is depicted d₂. The thickness of the n-type AlGaAs layer (1) is depicted by d₀. The total thickness d of the two depletion layers (11) and (12) is ##EQU1## wherein, N_D is the impurity concentration of the n-type AlGaAs layer (1),

ε_S is the dielectric constant of the n-type AlGaAs layer (1),

q is the charge of an electron,

k is the Boltzmann constant, and

T is the absolute temperature at which a device works.

(The formulations herein ignore the small energy gap shown in FIG. 10 between the bottom of the conduction band in the source layer and the Fermi level, this gap depending on the impurity type.) The upper limit (d₀) of the thickness range of the n-type AlGaAs layer (1) which allows the negative regulation of conductivity, that is, which allows the condition shown in FIGS. 5 and 6, is

d₀ ≈d₁ +d₂ (2)

In other words, the higher limit (d₀) must be identical to the cumulative thickness of the two depletion layers (11) and (12). The layer configuration which satisfies this thickness limitation allows regulation of the concentration of the electron accumulation (14) with a negative voltage applied to a gate. This conclusion was proved for the layer configuration described above containing a 800-angstrom AlGaAs layer with a donor concentration of 6×10¹7 /cm³. The surface electron concentration N_S of the electron accumulation (14), determined by utilization of the Hall effect, showed a linear change from 8×10¹1 /cm² to 2×10¹1 /cm² for the gate-source voltage variation between 0 V (zero volt) and -3.5 V.

As described earlier, the thickness (d₀) range of the n-doped AlGaAs layer (1) workable as an active device is

0<d₀ ≦d₁ +d₂ (3)

Within this thickness range, however, the function varies depending on specific conditions.

In the case where the energy barrier (V_D1) between the metal layer (10) and the n-type AlGaAs layer (1) is less than the energy barrier (V_D2) between the n-type AlGaAs layer (1) and the GaAs layer (2) due to the difference in electron affinity, namely in the case of V_D1 /V_D2, the electron accumulation (14) is always available in the GaAs layer (2) as shown in FIG. 7 (b), regardless of the thickness of the n-type AlGaAs layer (1). Therefore, regardless of the thickness of the n-doped AlGaAs layer (1), regulation for conductivity is possible for this layer configuration with a negative voltage applied to a gate. As a result, under these conditions, this layer configuration can be utilized as a normally-on mode (depletion mode) FET. Within this thickness range, variation in thickness corresponds to variation in characteristics. Namely, a lesser thickness of the n-type AlGaAs layer (1) causes a lesser electron concentration for the electron accumulation (14). In this case, however, a larger influence of the field effect due to the lesser thickness of the n-type AlGaAs layer (1) causes a better sensitivity.

In the case where the energy barrier (V_D1) between the metal layer (10) and the n-type AlGaAs layer (1) is larger than the energy barrier (V_D2) between the n-type AlGaAs layer (1) and the GaAs layer (2) due to the difference in electron affinity, namely in the case of V_D1 >V_D2, the situation differs depending on whether the thickness (d₀) of the n-type AlGaAs layer (1) is

d₁ <d₀ ≦d₁ +d₂ (4)

or

0<d₀ ≦d₁ (5)

In the case where the inequality (4) is satisfied, the band diagrams shown in FIGS., 5, 6 and 7 (a) are realized. In the case where the inequality (5) is satisfied, the band diagrams shown in FIGS. 8 and 9 are realized. In the former case, since the electron accumulation (14) is available in the GaAs layer (2), regulation for conductivity is possible with a negative voltage applied to a gate. Therefore, a normally-on mode (depletion mode) FET can be produced with this layer configuration. In the latter case, regulation for conductivity is possible with a positive voltage applied to a gate. Therefore, a normally-off mode (enhancement mode) FET can be produced with this layer configuration. In the case of d₀ =d₁, the pinch-off voltage becomes 0 V (zero volts). Within this thickness range, variation in thickness corresponds to variation in characteristics. Namely, a lesser thickness of the n-type AlGaAs layer (1) causes a lesser electron concentration for the electron accumulation (14). In this case, however, a larger influence of the field effect due to the lesser thickness of the n-type AlGaAs layer (1) causes a better sensitivity.

It is needless to emphasize that not only a Schottky barrier gate but also an insulated gate is useful in the present invention.

One example of a production method will be described below for each of the normally-on mode (depletion mode) FET and the normally-off mode (enhancement mode) FET, supposing that Al₀.3 Ga₀.7 As and GaAs are respectively employed for fabrication of an electron source region and a channel region.

FIG. 11 shows a completed normally-on mode (depletion mode) FET in accordance with this invention. The first step is to grow a GaAs layer with the thickness of approximately 3,000 angstroms of a non-conductive or semi-insulator GaAs substrate (20) employing for example an MBE (Molecular Beam Epitaxy) process. Reference numeral (22) depicts the GaAs layer or the channel region. The impurity concentration is freely selected for the channel region, although it is preferable if it is input and the source and drain output terminals along a single heterojunction formed between a channel region of a material having a lesser electron affinity and an electron source region of a material having a larger electron affinity.

Claims

1. An active semiconductor device with high electron mobility, comprising

a source layer of a semiconductor doped with donor impurities,

a channel layer of a semiconductor having a larger electron affinity than the semiconductor of the source layer and forming a heterojunction with said source layer, wherein a channel is formed in said channel layer along said heterojunction,

at least one control terminal formed on a selected one of said source and channel layers layer over said a portion of said heterojunction,

a pair of output terminals selectively formed on said source and channel layers, on opposite sides of said at least one control terminal,

said source layer having sufficiently small thickness, at least under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control electrode,

wherein said output terminals are electrically connected, at least under said at least one control terminal, only by an accumulation of electrons with high mobility in said channel in said channel layer, depending on a control voltage applied to said control terminal.

2. The device of claim 1, said at least one control terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, such that said device is of the normally ON type.

3. The device of claim 1, said at least one control electrode terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, such that said device is of the normally OFF type.

4. The device of claim 3, the difference between said electron affinities of said source and channel layers being less than approximately the height of the potential barrier that would form at the bottom of the conduction band in said source layer at the boundary of said at least one the control electrode terminal, if said source layer were sufficiently thick to have a flat portion in its conduction band.

5. The device of claim 1, wherein said at least one control terminal is formed on said source layer and said source layer has a thickness, under said at least one control terminal, equal to or less than approximately ##EQU10## wherein ε_S is the dielectric constant of said source layer,

N_D is the concentration of said donor impurities in said source layer,

V_D1 is the height of the potential barrier that would form in said source layer at the boundary of said at least one control terminal, if said source layer was sufficiently thick to have a flat portion in its conduction band,

V_D2 is the height of the potential barrier that would form in the conduction band in said source layer adjacent said channel layer, if said source layer was sufficiently thick to have said flat portion, and

k is Boltzmann's constant, q is the electron charge, and

T is absolute temperature.

6. The device of claim 5, said source layer being thicker, under said at least one control electrode terminal, than approximately the first term in the formula of claim 5.

7. The device of claim 5, said source layer having a thickness, under said at least one control terminal, that is equal to or less than approximately the first term in the formula of claim 5.

8. The device of claim 7, wherein V_D1 >V_D2.

9. The device of claim 7, wherein VD₁ <V_D2.

10. The device of claim 1, wherein said at least one control terminal is formed on said channel layer, and said source layer has a thickness, under said at least one control terminal, that is equal to or less than ##EQU11## wherein

ε_SA is the dielectric constant of said source layer,

N_D is the concentration of said donor impurities in said source layer,

V_D is the height of the potential barrier that would form in the conduction band of the source layer adjacent said channel layer, if the source layer was sufficiently thick that the bottom of its conduction band had a flat portion, and

k is the Boltzmann constant, q is the electron charge, and T is the absolute temperature.

11. The device of claim 10, wherein the ratio of the thickness of said channel layer to the thickness of said source layer, under said at least one control terminal, is greater than approximately ##EQU12## wherein

V_S is the height of the potential barrier in the bottom of the conduction band in said channel layer adjacent said at least one control terminal and the Fermi level in said channel,

ΔE_C is the difference in the electron affinities of the source and channel layers,

E_F is the energy difference between the Fermi level and the bottom of the conduction band in the channel layer along said heterojunction, and

ε_SG is the dielectric constant of said channel layer.

12. The device of claim 10, wherein the ratio of the thickness of said channel layer to the thickness of said source layer, under said at least one control terminal, is equal to or less than approximately ##EQU13## wherein

V_S is the height of the potential barrier in the bottom of the conduction band in said channel layer adjacent said at least one control terminal and the Fermi level in said channel,

ΔE_C is the difference in the electron affinities of the source and channel layers,

E_F is the energy difference between the Fermi level and the bottom of the conduction band in the channel layer along said heterojunction, and

ε_SG is the dielectric constant of said channel layer.

13. The device of claim 12, said source and channel layers having thicknesses, under said at least one control terminal, such that said device is of the normally ON type.

14. The device of claim 12, said source and channel layers having thicknesses, at least under said at least one control terminal, such that said device is of the normally OFF

type. 15. The device of any one of claims 1-14 1-9, wherein the non-selected one of said semiconductor layers is grown on a substrate of a substantially non-conductive material.

16. The device of claim 11, 12, 13 or 14 wherein said source layer is formed on a buffer layer of an undoped semiconductor, and said buffer layer is formed on a substrate of a substantially non-conductive

material. 17. The device of any one of claims 1-14 1-9, wherein said source and channel layers, and control and output electrodes, comprise a FET having a substantially linear transfer conductance and amplification characteristic as a result of said output electrodes being connected, under said at least one control electrode, only by said high mobility electrons in said channels. 18. An active semiconductor device as recited in claim 1, wherein:

the source layer is formed of AlGaAs semiconductor material; and

the channel layer is formed of GaAs semiconductor material. 19. An active semiconductor device as recited in claim 1, wherein:

the source layer is formed of AlGaAs semiconductor material; and

the channel layer is formed of Ge semiconductor material.

. An active semiconductor device as recited in claim 1, wherein:

the source layer is formed of GaAs semiconductor material; and

the channel layer is formed of Ge semiconductor material. 21. An active semiconductor device as recited in claim 1, wherein:

the source layer is formed of CdTe semiconductor material; and

the channel layer is formed of InSb semiconductor material. 22. An active semiconductor device as recited in claim 1, wherein:

the source layer is formed of GaSb semiconductor material; and

the channel layer is formed of InAs semiconductor material. 23. An active semiconductor device as recited in claim 1, wherein:

said source layer is formed of an n-doped semiconductor material. 24. An active semiconductor device as recited in claim 23, wherein:

said channel layer is selectively formed of an undoped or an unintentionally doped semiconductor material. 25. An active semiconductor device as recited in claim 23, wherein said channel

layer is undoped. 26. An active semiconductor device as recited in claim 1, further comprising a substrate, said channel layer being formed on said substrate and said source layer being formed on said channel layer, in succession. 27. An active semiconductor device as recited in claim 26, wherein:

said substrate is formed of a semi-insulating material. 28. An active semiconductor device as recited in claim 2 or 6, wherein:

said source layer is limited in lateral extent, in a plane transverse to the thickness thereof, substantially to the corresponding lateral extent of said at least one control terminal; and

said pair of output terminals is formed on said channel layer, on opposite sides of said source layer and said at least one control terminal formed thereon. 29. An active semiconductor device as recited in claim 2 or 6, wherein:

a single control terminal is formed on said source layer;

said source layer is limited in lateral extent, in a plane transverse to the thickness thereof, substantially to the corresponding lateral extent of said control terminal; and

said pair of output terminals is formed on said channel layer, on opposite sides of said source layer and said control terminal formed thereon.

30. An active semiconductor device as recited in claim 3 or 7, wherein:

said source layer, in a plane transverse to the thickness thereof, is substantially coextensive with said channel layer; and

said source layer, in a central portion thereof under said at least one control terminal has said thickness such that said device is of the normally OFF type and the remaining portions of said source layer have a greater thickness, thereby to define a recessed said central portion of said source layer; and

said at least one control terminal is formed on said recessed central portion. 31. An active semiconductor device as recited in claim 30, wherein:

said pair of output terminals is formed on said source layer on said greater thickness portions thereof on opposite sides of said recessed central portion thereof and comprise respective, deeply doped regions of said greater thickness portions of said source layer and the corresponding underlying portions of said channel layer. 32. An active semiconductor device as recited in claim 3 or 7, wherein:

a single control terminal is formed on said source layer;

said source layer, in a plane transverse to the thickness thereof, is substantially coextensive with said channel layer; and

said source layer, in a central portion thereof under said single control terminal, has said thickness such that said device is of the normally OFF type and the remaining portions of said source layer have a greater thickness, thereby to define a recessed, said central portion of said source layer on which said single control terminal is formed.

33. An active semiconductor device as recited in claim 32, wherein:

said pair of output terminals is formed on said source layer on said greater thickness portions thereof on opposite sides of said recessed central portion thereof and comprise respective, deeply doped regions of said greater thickness portions of said source layer and the corresponding underlying portions of said channel layer. 34. An active semiconductor device as recited in claim 1, said at least one control terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control terminal and to afford electron accumulation in said channel in the channel layer for functioning as a normally ON type device. 35. An active semiconductor device as recited in claim 1, a single said control terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control terminal and to afford electron accumulation in said channel in the channel layer for functioning as a normally ON type device. 36. An active semiconductor device as recited in claim 1, said source layer having a recess in a central portion thereof, on which said at least one control terminal is formed, defining a thickness in said central portion under said at least one control terminal which is entirely depleted of majority carriers and prevents the accumulation of electrons in said channel in said channel layer in the absence of a control voltage applied to said control terminal, so as to function as a normally OFF type device.

37. An active semiconductor device as recited in claim 1, said source layer having a recess in a central portion thereof on which a single said control terminal is formed, defining a thickness in said central portion under said at least one control terminal which is entirely depleted of majority carriers and prevents the accumulation of electrons in said channel in said channel layer in the absence of a control voltage applied to said control terminal, so as to function as a normally OFF type device. 38. An active semiconductor device as recited in claim 1, said source layer having a central portion of said sufficiently small thickness and remaining portions of greater than said sufficiently small thickness thereby to define a recessed said central portion, and said at least one control terminal being formed on said recessed central portion of said source layer. 39. An active semiconductor device as recited in claim 38, said source layer being limited in lateral extent, in a direction transverse to the thickness thereof, to the spacing between said pair of output terminals; and

said output terminals being formed on said channel layer. 40. An active semiconductor device as recited in claim 38, said output terminals being formed on said source layer on opposite sides of said recessed central portion and said at least one control terminal

formed thereon. 41. An active semiconductor device with high electron mobility, comprising:

a substrate;

a channel layer formed on said substrate;

a source layer of a semiconductor doped with donor impurities, formed on said channel layer;

said channel layer comprising a semiconductor having a larger electron affinity than the semiconductor of the source layer and forming a heterojunction with said source layer;

at least one control terminal formed on said source layer and over at least a portion of said heterojunction;

a pair of output terminals each, independently, conductivity connected to said heterojunction and respectively disposed on opposite sides of said at least one control terminal, said source layer having sufficiently small thickness, at least under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control electrode; and

said output terminals being electrically connected, at least under said at least one control terminal, only by an accumulation of electrons with high mobility in a channel defined by said heterojunction, depending on a control voltage applied to said control terminal. 42. An active semiconductor device as recited in claim 41, said source layer having a central portion of said sufficiently small thickness and remaining portions of greater than said sufficiently small thickness thereby to define a recessed said central portion, and said at least one control terminal being formed on said recessed central portion of said

source layer. 43. An active semiconductor device as recited in claim 41, said source layer being limited in lateral extent, in a direction transverse to the thickness thereof, to the spacing between said pair of output terminals; and

said output terminals being formed on said channel layer. 44. An active semiconductor device as recited in claim 41, said output terminals being formed on said source layer on opposite sides of said recessed central portion and said at least one control terminal formed thereon. 45. An active semiconductor device as recited in claim 41, 42, 43 or 44, said at least one control terminal being formed on said source layer, and said source layer having a thickness, under said at least one control terminal, so as to be entirely depleted of majority carriers under said at least one control terminal and to afford electron accumulation in said channel in the channel layer for functioning as a normally ON type device. 46. An active semiconductor device as recited in claim 41, 42, 43 or 44, said source layer having a recess in a central portion thereof, on which said at least one control terminal is formed, defining a thickness in said central portion under said at least one control terminal which is entirely depleted of majority carriers and prevents the accumulation of electrons in said channel in said channel layer in the absence of a control voltage applied to said control terminal, so as to function as a normally OFF type device.