A circuit for rotating a multibit binary word in either the right or the left direction includes a scale factor decoder receiving a scale factor word which specifies the magnitude of the rotation and a direction control signal which specifies the direction of rotation and providing a shift control word which is the same as the scale factor word when a right rotation is specified but providing a shift control word which is the complement of the scale factor word when a left rotation is specified. The circuit also includes a plurality of input buffers receiving an input word and providing corresponding input data, and a one-bit rotator receiving the input data and the direction control signal and rotating the input data in the right direction by one position when a left rotation is specified or providing the input data without rotation when a right rotation is specified. In addition, the circuit includes a network receiving data from the one-bit rotator and the shaft control word and rotating the data from the one-bit rotator in only the right direction by a magnitude specified by the shift control word. Furthermore, the circuit includes a plurality of output buffers receiving the data from the network and providing an output word.A data shift/rotate circuit is designed to have the capability of either shifting or rotating data by a number of bit positions prescribed by an input word. The shifting vs. rotating is selected by a binary digital rotate control signal (ROT). The shifting or rotating can be either to the right or to the left, depending upon a binary digital direction control signal (L/R).
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1. A circuit for rotating an N-bit binary word in either a first or a second direction comprising:
control means adapted to receive a plurality of scale factor signals and a direction control signal indicative of a rotation in the second direction, and responsive thereto for providing a plurality of shift control signals which are respectively the complement of the scale factor signals, the control means providing a plurality of shift control signals which are respectively the same as the scale factor signals when the direction control signal is absent; input means adapted to receive an N-bit input word and providing corresponding N-bit input data; one-bit rotate means adapted to receive the input data and the direction control signal and being responsive to the direction control signal for rotating the input data by one position in the first direction, the one-bit rotate means providing the input data without rotation when the direction control signal is absent; unidirectional shift/rotate means adapted to receive data from the one-bit rotate means and the plurality of shift control signals and for rotating the data from the one-bit rotate means in the first direction by a magnitude specified by the shift control signals; and output means adapted to receive data from the unidirectional shift/rotate means for providing an N-bit output word which is the input word rotated according to the scale factor signals and the direction control signal.
2. A shift/rotate circuit for shifting an N-bit binary word in a first direction and for rotating the binary word in either the first or a second direction comprising:
control means adapted to receive a plurality of scale factor signals and a direction control signal indicative of a rotation in the second direction and being responsive thereto for providing a plurality of shift control signals which are respectively the complement of the scale factor signals, the control means for providing shift control signals which are respectively the same as the scale factor signals when the direction control signal is absent; input means adapted to receive an N-bit input word and for providing corresponding N-bit input data; one-bit rotate means adapted to receive the input data and the direction control signal and being responsive to the direction control signal for rotating the input data by one position in the first direction, the one-bit rotate means providing the input data without rotation when the direction control signal is absent; unidirectional shift/rotate means adapted to receive data from the one-bit rotate means, the plurality of shift control signals and a rotate control signal and being responsive to the rotate control signal for rotating the data from the one-bit rotate means in the first direction by a magnitude specified by the shift control signals, the unidirectional shift/rotate means shifting the data from the one-bit rotate means in the first direction by the magnitude specified by the shift control signals; and output means adapted to receive data from the unidirectional shift/rotate means for providing an N-bit output word which is the input word shifted or rotated according to the scale factor, direction control and rotate
control signals. 3. A shift/rotate circuit as recited in
4. A shift-rotate circuit as recited in
N input conductors representing N bit positions including a first and a last bit position along the second direction; N output conductors representing N bit positions including a first and a last bit position along the second direction; means providing a no-rotation control signal when the direction control signal is absent; a no-rotation conductor for transmitting the no-rotation signal control signal; a direction conductor for transmitting the direction control signal; a plurality of first switch means, a respective one coupled between each input conductor and a corresponding output conductor representing a like bit position for transferring data signals on the input conductors to the corresponding output conductors in response to the no-rotation signal; and a plurality of second switch means, a respective one coupled between each input conductor except the one representing the first bit position and an output conductor representing a bit position displaced by one position in the first direction from that represented by the input conductor, and a respective one coupled between the input conductor representing the first bit position and the output conductor representing the last bit position, the second switch means transferring a data signal from the input conductor to the output conductor coupled thereby in response to the direction control signal.
5. A shift/rotate circuit as recited in
N input conductors representing N bit positions including a first and a last bit position along the second direction; N output conductors representing N bit positions including a first and a last bit position along the second direction; means providing a no-shift signal when the respective shift control signal is absent; a no-shift conductor for transmitting the no-shift control signal; a shift conductor for transmitting the respective shift control signal; a rotate conductor for transmitting the rotate control signal; a plurality of third switch means, a respective one coupled between each input conductor and a corresponding output conductor of a like bit position for transferring data signals on the input conductors to the corresponding output conductors in response to the no-shift signal; a plurality of fourth switch means, a respective one coupled between each input conductor except the ones representing those bit positions which are less than the predetermined number of positions from the first bit position and an output conductor representing a bit position displaced by the predetermined number of positions in the first direction from that represented by the input conductor, the fourth switch means transferring a data signal from the input conductor to the output conductor coupled thereby in response to the respective shift control signal; and one or more fifth switch means, a respective one coupled between each input conductor representing a bit position which is less than the predetermined number of positions from the first bit position and an output conductor representing a bit position circularly displaced by the predetermined number of bit positions in the first direction from that represented by the input conductor, the fifth switch means transferring a data signal from the input conductor to the output conductor coupled thereby in response to the rotate control signal.
6. A shift/rotate circuit as recited in
7. A shift/rotate circuit as recited in
8. A shift/rotate circuit as recited in
9. A shift/rotate circuit as recited in
10. A shift/rotate circuit as recited in
p-type. 11. A circuit for rotating a multibit input binary word in either a first or a second direction comprising: (a) control means, adapted to receive a plurality of scale factor signals and to receive a direction control signal, for providing a plurality of shift control signals which are respectively the complement of the scale factor signals when the direction control signal has a first binary value and which are respectively the same as the scale factor signals when the direction control signal has a second binary value; (b) multi-bit-position rotate means, adapted to receive input data that are representative of the multibit input binary word, comprising (1) one-bit-position rotate means, adapted to receive the input data and the direction control signal, for rotating data by one bit position in the first direction when the direction control signal has the first binary value and for providing data without rotation when the direction control signal has the second binary value; and (2) unidirectional rotate means, connected to the one-bit-position rotate means so as to receive data therefrom and connected to the control means so as to receive the plurality of shift control signals therefrom, for rotating data in the first direction by a number of bit positions specified by the shift control signals, whereby output data of the unidirectional rotate means are representative of the input word rotated according to the scale factor signals and the direction control signal. 12. The circuit of claim 11 comprising (a) input means, adapted to receive the multibit input binary word, for providing the input data which are representative of the input word; and (b) output means, adapted to receive the output of the multi-bit-position rotate means, for providing the rotated input word in accordance with the scale factor signal and the direction control signal. 13. The circuit of claim 12 in which the input means comprises a first array of inverters, one for each bit of the multibit input word, for inverting each bit of the input word to produce the input data which are representative of the input word, and in which the output means comprises a second array of inverters, one for each bit of the rotated input word, for inverting each bit of the output of the multi-bit-position rotate means. 14. A shift/rotate circuit for shifting an N-bit input binary word in a first direction and for rotating the binary word in either the first or a second, opposite direction comprising: control means, adapted to receive a plurality of scale factor signals and a direction control signal, for providing a plurality of shift control signals which are respectively the complement of the scale factor signals when the direction control signal has a first binary value and which are respectively the same as the scale factor signals when the direction control signal has a second binary value; one-bit-position rotate means, adapted to receive input data which are representative of the N-bit binary word and to receive the direction control signal, for rotating the input data by one bit position in the first direction when the direction control signal has the first value, and for providing the input data without rotation when the direction control signal has the second value; and unidirectional shift/rotate means, connected to the control means so as to receive the plurality of shift control signals therefrom, connected to the one-bit-position rotate means so as to receive data therefrom, and adapted to receive a rotate control signal, for rotating in the first direction the data from the one-bit-position rotate means by the total number of bit positions specified by the shift control signals when the rotate control signal has a third binary value, and for shifting in the first direction the data from the one-bit-position rotate means by the total number of bit positions specified by the shift control signals when the rotate control signal has a fourth binary value, whereby output of the unidirectional shift/rotate means is representative of the input word shifted or rotated according to the scale factor signals, the direction control signal, and the rotate control signal. 15. The circuit of claim 14 further comprising (a) input means, adapted to receive the input word, for providing the input data which are representative of the input word; and (b) output means, adapted to receive the output of the unidirectional shift/rotate means, for providing the input word rotated or shifted according to the scale factor signals, the rotate control signal, and the direction control signal. 16. A shift/rotate circuit as recited in claim 14 wherein the unidirectional shift/rotate means comprise a plurality of ranked levels including a first and a last level, each ranked level being adapted to receive incoming data, a respective one of the shift control signals, and the rotate control signal, each ranked level being responsive to the rotate control signal and to a respective one of the shift control signals, for rotating or for shifting the incoming data, depending upon the value of the rotate control signal, by a predetermined number of bit positions, depending upon the ranked level, when the respective shift control signal has a binary fifth value and for providing the incoming data without shift or rotation when the respective shift control signal has a binary sixth value, each ranked level except the first being coupled to receive data from the immediately preceding level, the first ranked level being coupled to receive data from the one-bit-position rotate means, whereby the last ranked level provides the output that is representative of the input word shifted or rotated according to the scale factor signals, the rotate control signal, and the direction control signal. 17. The circuit of claim 16 further comprising (a) input means, adapted to receive the input word, for providing the input data which are representative of the input word; and (b) output means, adapted to receive the output of the last ranked level, for providing the input word rotated or shifted according to the scale factor signals, the rotate control signal, and the direction control signal. 18. A shift-rotate circuit as recited in claim 17 wherein the one-bit-position rotate means comprises: N input conductors representing N bit positions including a first and a last bit position; N output conductors representing N bit positions including a first and a last bit position; a plurality of first switch means, a respective one coupled between each input conductor and a corresponding output conductor representing a like bit position for transferring data signals on the input conductors to the corresponding output conductors in response to the second binary value of the direction control signal; and a plurality of second switch means, a respective one coupled between each input conductor except the one representing the first bit position and an output conductor representing a bit position displaced by one position in the first direction from that represented by the input conductor, and a respective one coupled between the input conductor representing the first bit position and the output conductor representing the last bit position, the second switch means transferring a data signal from the input conductor to the output conductor coupled thereby in response to the first binary value of the direction control signal. 19. A shift/rotate circuit as recited in claim 18 wherein each level of the unidirectional shift/rotate means comprises: N input conductors representing N bit positions including a first and a last bit position; N output conductors representing N bit positions including a first and a last bit position; a plurality of third switch means, a respective one coupled between each input conductor and a corresponding output conductor of a like bit position for transferring data signals on the input conductors to the corresponding output conductors in response to the sixth binary value of the respective one of the shift control signal; a plurality of fourth switch means, a respective one coupled between each input conductor except the ones representing those bit positions which are less than a predetermined number of positions from the first bit position and an output conductor representing a bit position displaced by the predetermined number of positions in the first direction from that represented by the input conductor, the fourth switch means transferring a data signal from the input conductor to the output conductor coupled thereby in response to the fifth binary value of the respective one of the shift control signals; and one or more fifth switch means, a respective one coupled between each input conductor representing a bit position which is less than the predetermined number of positions from the first bit position and an output conductor representing a bit position circularly displaced by the predetermined number of bit positions in the first direction from that represented by the input conductor, the fifth switch means transferring a data signal from the input conductor to the output conductor coupled thereby in response to the rotate control signal. |
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has thirty-two input conductors I200 through I231 (not all are shown) representing thirty-two bit positions and thirty-two output conductors O200 through O231 (not all are shown) also representing the thirty-two bit positions. The input conductors of level 1037 are each connected to an output conductor of level 1036 representing a like bit position. Each input conductor of level 1037 is also coupled through the conduction channel of a respective one of a third group of n-channel transistors T500 through T531 (not all are shown) to a corresponding output conductor of the level 1037 representing a like bit position. The gate electrodes of T500 through T531 are all connected to a conductor 4007 carrying the complement of the 21 signal generated by a CMOS inverter 4006 which receives the 21 signal. Each input conductor of level 1037 except the two right-most two I200 and I201 is also coupled through the conduction channel of a respective one of a fourth group of n-channel transistors T602 through T631 (not all are shown) to an output conductor representing a bit position displaced two positions to the right of that represented by the input conductor. The gate electrodes of transistors T602 through T631 are all connected to a conductor 4005 carrying the 21 signal. Input conductors I200 and I201 are coupled respectively through the conduction channels of a fifth group of n-channel transistors T600 and T601 to output conductors O230 and O231. The gate electrodes of transistors T600 and T601 are both connected to a conductor 4008 carrying the ROT signal.
When both the 21 and the ROT signals are each a logic "0" level, transistors T600 through T631 are in the OFF state while transistors T500 through T531 are all permitted to go to the ON state. Under these conditions the data signal on each input conductor of level 1037 is transferred to a corresponding output conductor of level 1037 representing a like bit position.
When the 21 signal is a logic "1" level and the ROT signal is a logic "0" level, transistors T500 through T531, T600 and T601 are all in the OFF state while transistors T602 through T631 are all permitted to go to the ON state. Under these conditions the data signal on each input conductor except the right-most two I200 and I201 is transferred to an output conductor representing a bit position displaced by two positions to the right of that represented by the input conductor. If while the 21 signal is a logic "1" level, the ROT signal is also a logic "1" level, transistors T600 and T601 are permitted to go to the ON state, and the data signals on input conductors I200 and I201 are respectively transferred to output conductors O230 and O231 which represent bit positions circularly displaced by two positions to the right of those represented by input conductors I200 and I201, respectively. In normal operation a logic "1" level ROT signal is not applied when the 21 signal is a logic "0" level.
Referring now to FIG. 5, there is shown a schematic diagram of level 1040 of the shifter/rotator, the precharge network 1041 and the output inverters 1042 through 1073 (not all are shown). For simplicity of the drawing, levels 1038 and 1039 have been omitted from the depiction. The circuit details of levels 1038 and 1039 which are designed to provide shift or rotation in the right direction by four and eight positions, respectively, will be obvious to one skilled in the art of IGFET circuit design from the description of the circuit details of levels 1036, 1037 and 1040 which are designed to provide shift or rotation in the right direction by one, two, and sixteen positions, respectively.
Level 1040 has thirty-two input conductors I300 through I331 (not all are shown) representing thirty-two bit positions and thirty-two output conductors O300 through O331 (not all are shown) also representing the thirty-two bit positions. The input conductors of level 1040 are each connected to an output conductor of level 1039 (not shown) representing a like bit position. Each input conductor of level 1040 is coupled through the conduction channel of a respective one of a third group of n-channel transistors T700 and T731 (not all are shown) to a corresponding output conductor of level 1040 representing a like bit position. The gate electrodes of transistors T700 through T731 are all connected to a conductor 5003 carrying the complement of the 24 signal provided by a CMOS inverter 5002 which receives the 24 signal. Each input conductor except the right-most sixteen I300 through I315 is also coupled through the conduction channel of a respective one of a fourth group of n-channel transistors T816 through T831 (not all are shown) to an output conductor representing a bit position displaced by sixteen positions to the right of that represented by the input conductor. The gate electrodes of transistors T816 through T831 are all connected to a conductor 5001 carrying the 24 signal. The right-most sixteen input conductors I300 through I315 are respectively coupled through the conduction channels of a fifth group of n-channel transistors T800 through T815 (not all shown) to the sixteen left-most output conductors O316 through O331. The gate electrodes of T800 through T815 are all connected to a conductor 5004 carrying the ROT signal.
When the 24 signal and the ROT signal are each a logic "0" level, transistors T800 through T831 are all in the OFF state while transistors T700 through T731 are all permitted to go to the ON state. Under these conditions the data signal on each input conductor of level 1040 is transferred to a corresponding output conductor of level 1040 representing a like bit position.
When the 24 signal is a logic "1" level, and the ROT signal is a logic "0" level, transistors T700 through T731 and T800 through T815 are all in the OFF state while transistors T816 through T831 are all permitted to go to the ON state. Under these conditions the data on each of the input conductors except the right-most sixteen I300 through I315 are transferred to an output conductor representing a bit position displaced sixteen positions to the right of that represented by the input conductor. If while the 24 signal is at a logic "1" level, the ROT signal is also at a logic "1" level, transistors T800 through T815 are permitted to go to the ON state, and the data signals on the sixteen right-most input conductors I300 through I315 are transferred to output conductors O316 through O331, respectively. The bit positions represented by output conductors O316 through O331 are circularly displaced to the right by sixteen positions from those represented by the input conductors I300 through I315, respectively.
Each one of the output conductors O300 through O331 is connected to the input of a respective one of thirty-two output inverters 1042 through 1073 (not all are shown). Each output inverter provides a respective bit of the output word B0 through B31.
The precharge network 1041 comprises thirty-two pairs 1074 through 1105 of p-channel transistors (not all pairs are shown). Each pair includes transistors T3 and T2 both having their conduction channels coupled between a respective one of the output conductors of level 1040 and a conductor 5006 carrying VDD. The gate electrode of transistor T4 is connected to a conductor 5005 carrying the PRECHARGE signal while the gate electrode of T3 is connected to ground. Transistor T3 is designed to provide a relatively large current when driven to the ON state to permit a rapid precharge of the respective output conductor. Therefore, transistor T3 has a relatively large channel width to channel length ratio. On the other hand, transistor T4, which remains in the ON state even when T3 is in the OFF state, is designed to provide a relatively low current which is sufficient to sustain a logic "1" level on the respective output conductor against leakage currents but which is not sufficient to hold the output conductor against a logic "0" data signal. Therefore, transistor T3 has a relatively small channel width to channel length ratio. Transistors T3 and T4 are driven to the ON state by a logic "0" level applied to their respective gate electrodes.
In normal operation, the bits 24,23,22,21 and 20 of the shift control word are all set to a logic "0" level during intervals when the PRECHARGE signal is at a logic "0" level. Therefore, during those intervals, transistors in the third group in each level of the shifter/rotator and in the first group in the one-bit rotator are all permitted to go to the ON state, and all the input and output conductors of each level and the one-bit rotator are precharged to a logic "1" level.
Although the disclosed embodiment of the present invention is implemented in CMOS, a shift/rotate circuit according to the present invention may also be implemented in other integrated circuit technologies such as p-channel metal-oxide-semiconductor (PMOS) technology and n-channel metal-oxide-semiconductor (NMOS) technology with appropriate modifications to the polarities and magnitudes of the supply voltages and logic levels as would be obvious to one skilled in the art of integrated circuit design.
It will be understood by those skilled in the art that the foregoing and other modifications and other alterations may be made to the described embodiment without departing from the spirit and scope of the present invention. For example, the shifter/rotator may be modified to provide only the rotation operation by eliminating the ROT signal and by connecting the conductor for carrying the ROT signal in each level of the shifter/rotator to the conductor carrying the respective bit of the shift control word. In addition, the transistors of the first and second groups in the one-bit rotator and of the third, fourth, and fifth groups in the shifter/rotator which serve as transmission gate switches may be replaced by equivalent switch means as are known or as will be discovered.
Kang, Sung M., Krambeck, Robert H., Kwan, Alfred Y.
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