Auto focus circuit for video camera

Abstract

An auto focus circuit for a video camera comprises an A-D converting circuit (7) for converting to a digital amount a high frequency component absolute value output of a luminance signal in a sampling area for focusing. The A-D converting circuit (7) is connected so that the high frequency component absolute value output of a luminance signal is directly converted to a digital amount. Then, the signal converted to a digital amount is added in an integrating circuit (12) for each field and the signal amount in one field and the signal amount in the coming one field ahead of it or behind it are compared in a comparing circuit (10) so that the output of comparison serves for control of focusing. Thus, addition processing of the high frequency component of the luminance signal, that is, averaging processing is performed digitally in the integrating circuit (12). Accordingly, as compared with the case of analog averaging processing of a signal, the processing operation is stable and as a result the focusing precision is improved.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an improvement of an auto focus circuit adopted in a video camera.

Particularly, the present invention relates to an improvement of an auto focus circuit of a system in which an input video signal is evaluated to control the movement of a focusing ring by a closed loop.

2. Description of the Prior Art

In the prior art concerning an auto focus circuit of a video camera, two methods are known: a method in which the movement of a focusing ring is controlled by an open loop and a method in which the movement of a focusing ring is controlled by a closed loop by evaluating a video signal. The former method has disadvantages the comparison is supplied to a focusing motor control circuit 11.

The focusing motor control circuit 11 rotates in an initialized state causes the focusing motor (not shown) in an initialized state to rotate in a predetermined direction. The rotation in the above stated direction is continued as far long as the output of the second memory 9 is smaller than the output of the first memory 8. On the contrary, if the output of the second memory 9 becomes larger than the output of the first memory 8 and the output level of the comparing circuit 10 is reversed, the focusing motor control circuit 11 reverses the rotating direction of the focusing motor. Thus, by means of the focusing motor, the focusing ring (not shown) is always moved to a position in focus.

FIG. 3 is a block diagram of an auto focus circuit of the second preferred embodiment of the present invention.

Referring to FIG. 3, a luminance signal Y contained in a video signal obtained by recording is supplied to a high-pass filter 4. Through the high-pass filter 4, a high frequency component higher than 100 kHz is separated from the luminance signal. Then, the separated high frequency component is supplied to an absolute value calculating circuit 5. In the absolute value calculating circuit 5, an absolute value of the signal is obtained and the absolute value output is supplied to an envelope detecting circuit 13. In the envelope detecting circuit 13, an envelope of the absolute value output is detected. Then, the detected output is supplied to an analog-to-digital (A-D) converting circuit 7. The A-D converting circuit 7 converts the received analog envelope detection signal to a digital signal during a predetermined period.

On the other hand, the luminance signal Y is also supplied to a synchronizing separation circuit 3. In the synchronizing separation circuit 3, a horizontal synchronizing signal H and a vertical synchronizing signal V are separated from the luminance signal Y. The separated horizontal synchronizing signal H and vertical synchronizing signal V are supplied to a gate control circuit 2. The gate control circuit 2 controls a gate circuit 1 so that the gate circuit 1 is opened only in a period corresponding to a predetermined sampling area in the screen region. More specifically, the sampling area is defined by a range from 1/4 to 3/4 of a dimension of the screen region in the horizontal direction and a range from 1/4 to 3/4 of a dimension of the screen region in the vertical direction and the opening of the gate circuit 1 is controlled so that the signal in the sampling area is extracted. The sampling area is not limited to the area as defined above and may be an arbitrary region in the screen region. Otherwise, the sampling area may be variable by selecting operation. In addition, to the gate circuit 1, a pulse signal of 5 MHz is supplied from a pulse generating circuit 14. In consequence, the pulse signal of 5 MHz is supplied to the A-D converting circuit 7 in a period in which the gate circuit 1 is opened by the gate control circuit 2, and with the timing of the pulse signal, the analog envelope detecting signal is converted to a digital signal of eight bits for example. The pulse signal provided from the gate circuit 1 is supplied as a latch pulse to a latch circuit 12b in an integrating circuit 12 to be described later. The pulse signal from the pulse generating circuit 14 may be applied to the gate control circuit 2 for determining the sampling area.

The digital signal thus converted is integrated for each field in the integrating circuit 12 in the next stage. More specifically, the integrating circuit 12 comprises an addition circuit 12a and a latch circuit 12b. The addition circuit 12a has a closed loop structure in which the digital signal provided from the A-D converting circuit 7 and the digital signal provided from the latch circuit 12b are added and the output of addition is supplied to the latch circuit 12b.

The latch circuit 12b latches the input signal according to the latch pulse supplied from the above stated gate circuit 1. The latch circuit 12b is reset by the vertical synchronizing signal V supplied from the synchronizing separation circuit 3. Thus, the latch circuit 12b integrates the output of the A-D converting circuit 7 by a field cycle.

On A first memory 8 is connected on the output side of the latch circuit 12b, a first memory 8 is connected and a second memory 9 is connected to the first memory 8, a second memory 9 is connected. Both of the memories 8 and 9 are controlled by the vertical synchronizing signal V so that writing operation is performed in the memories 8 and 9. The memories 8 and 9 provide the signals stored at present as far long as new data is not written. These first memory 8 and second memory 9 are formed by D-flip-flops for example.

As described previously, the resetting on the latch circuit 12b and the writting of the first memory 8 and the second memory 9 are controlled in synchronism with the vertical synchronizing signal V. Accordingly, for each field, the content of the latch circuit 12b is written in the first memory 8 and with a delay of one field, the content is written in the second memory 9. Instead of using the vertical synchronizing signal V, a divided vertical synchronizing signal can be used as a control signal. In such a case, for each predetermined period, for example, 1/2 field or 2 fields etc. the content of the latch circuit 12b is written in the first memory 8 and, with a delay of one predetermined period, the content is written in the second memory 9. Then, a comparing circuit 10 receiving the output of the first memory 8 and the output of the second memory 9 compares by a field cycle, the digital converted data in one field (this data being supplied from the second memory 9) and the digital converted data in the field coming one field ahead of behind the above stated field (this data being supplied from the first memory 8) and the output of comparison is supplied to a focusing motor control circuit 11. The focusing motor control circuit 11 controls the focusing motor in the same manner as in the first embodiment and the prior art so that the most suitable focusing operation is performed.

Thus, in both of the first embodiment and the second embodiment, processing of the signal after A-D conversion, that is, addition, writing and other processing of the digital signal are performed with predetermined timing based on the vertical synchronizing signal V separated from the luminance signal Y. However, it is to be noted that such processing of the digital signal can be performed using software, in other words, a microcomputer provided with a program for desired operation.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims

1. An autofocus circuit for a video camera including a focusing motor for focusing, comprising:

a high-pass filter circuit means to which a luminance signal of a video signal is applied so that for extracting a high frequency component higher than a predetermined frequency is extracted from said applied luminance signal,

an absolute value calculating circuit connected to said high-pass filter circuit for obtaining an absolute value of the output of said high-pass filter circuit,

an A-D converting circuit means operatively connected to said absolute value calculating circuit high-pass filter means for converting an analog absolute value output signal provided derived from said absolute value calculating circuit to high-pass filter means into a digital signal,

a calculating circuit means connected to said A-D converting circuit means for adding the converted digital signal with a predetermined period cycle,

a comparing circuit means connected to said calculating circuit means for comparing the output of calculation in one predetermined period and the output of calculation in the predetermined period coming one another predetermined period ahead of said predetermined period, and

a focusing motor control circuit means connected to said comparing circuit means for providing a signal for controlling the rotation of the focusing motor included in said video camera in the clockwise direction or in the counter-clockwise direction based on the output of said comparing circuit means.

2. An auto focus circuit in accordance with claim 1, wherein

said one predetermined period comprises one field.

3. An auto focus circuit in accordance with claim 2, wherein

said A-D converting circuit means converts said applied analog absolute value output signal from said high-pass filter means to a digital signal for each field only in a predetermined sampling period and provides said digital signal as an output.

4. An auto focus circuit in accordance with claim 3, further comprising:

a synchronizing separation circuit to which said luminance signal is applied so that a horizontal synchronizing signal and a vertical synchronizing signal are extracted from said luminance signal, and

a sampling period setting circuit connected between said synchronizing separation circuit and said A-D converting circuit means for setting a sampling period for each field of said video signal based on said horizontal synchronizing signal and said vertical synchronizing signal so that said A-D converting circuit means is enabled only in said sampling period.

5. An auto focus circuit in accordance with claim 4, wherein

the sampling period set by said sampling period setting circuit can be changed by selecting operation.

6. An auto focus circuit in accordance with claim 1, further comprising:

an envelope detecting circuit means connected between said absolute value calculating circuit high-pass filter means and said A-D converting circuit means for detecting and providing as an output an envelope of the output signal of said absolute valve calculating circuit high-pass filter means.

7. An auto focus circuit in accordance with claim 2, wherein

said calculating circuit means comprises:

a latch circuit operating with a cycle of one field for latching an input signal for one field, and

an addition circuit for adding the output from said A-D converting circuit means and the output from said latch circuit so that the signal obtained by said addition is applied to said latch circuit.

8. An auto focus circuit in accordance with claim 2, wherein

said comparing circuit means comprises:

a first memory for writing the output of said calculating circuit means for each field,

a second memory for writing the content written by said first memory with a delay of one field, and

a comparator for comparing the content of said first memory and the content of said second memory so that a high level output or a D-level output is provided according to the magnitude relation of said contents.

9. An auto focus circuit in accordance with claim 8, wherein

said first memory and said second memory are both D-flip-flops. 10. An auto focus circuit in accordance with claim 1, wherein

said another predetermined period comes before said one predetermined period.