Semiconductor device with isolation between MOSFET and control circuit

Abstract

A semiconductor device is provided which has a power insulated-gate MOS field effect transistor and a control semiconductor element formed in a common semiconductor substrate. A first area corresponding to a drain region of low resistance in the power MOS field effect transistor is different in resistivity than a second area corresponding to the control semiconductor element. The electrical characteristics of each element integrated in the devices is substantially equal to the same element in discrete form.

Description

a an N- -type silicon 24 and comprises of high resistance drain area 27 (first area), a drain region having low resistance regions 18, 19 and 21, a P type body 30, N³0 N+ type source region 29, and gate electrode 31. A An NPN transistor 52 used for controlling Power MOS FET 51 is formed within a high resistance N- type area 24a (second area) and comprises an emitter 32, a P type base 33, and a an N+ type collector 34. An N+ type collector 22 serves to lower the collector resistance. An A CMOS transistor 53 is formed within an N- type area 24b (second area) and comprises an N-channel MOS FET, which includes an N+ type drain 35e an, N+ type source 35b, and a gate electrode 36 formed within a P type well 39, and a P-channel MOS FET, which includes a P+ type drain 37a, a P+ type source 37b, and a gate electrode 38 formed within N- type area 24b. Power MOS FET 51, NPN transistor 52, and MOS transistor 53 are electrically isolated by a P type layer 20 and P+ type layers 23 and 26 (element isolation layers). In the first embodiment shown in FIG. 2, high resistance drain area 27 (first area) in Power MOS FET 51 has the resistivity value of about 1 Ω-cm and N-type areas 24a and 24b (second area) corresponding to control transistor elements 52 and 53 has have the resistivity value of 5 to 7 Ω-cm, these values being properly set in the formation of transistor elements.

FIG. 3(a) to FIG. 3(f) are cross-sectional views showing a principal process in manufacturing the aforementioned semiconductor device of the present invention. An N+ type silicon substrate 18 of low resistance is prepared with a highly-concentrated antimony doped therein. A highly-concentrated phosphorus is diffused in a low-resistance drain formation section of a Power MOS FET in a gaseous atmosphere of N₂ and O₂ at 1000° to 1100°C for 30 to 120 minutes to form N+ type region 19 as shown in FIG. 3(a). A P type silicon of 7 to 10 Ω (resistivity) is epitaxially grown on the surface of the resultant structure to form a P type silicon layer 20 (element isolation layer) about 20 or 30 μm in thickness and then thermally diffused in a gaseous atmosphere of N₂ and O₂ at 1100° to 1200° C. for 12 to 13 hours to form an N+ type region 19 as shown in FIG. 3(b). Antimony is diffused in the portion of the resultant structure in a gaseous atmosphere of N₂ at 1100°C to 1200°C for 20 to 120 minutes to form an N+ type region 21, corresponding to a low-resistance drain region in the Power MOS FET as well as a low-resistance area 22 used as a controlling element. A P³0 P+ type impurity (boron) is diffused for 30 minutes in an element isolation area of a formation portion with a gaseous atmosphere of 1000°C to 1100°C to form element isolation a P+ type layer 23, as shown in FIG. 3(c). Then a N- type silicon layer 24 (phosphorus) is epitaxially grown on the resultant structure so as to have a desired resistivity value and thickness, as shown in FIG. 3(d). In the first embodiment of the present invention, an N- type silicon layer 24 (second layer) is formed which has the resistivity value of 5 to 7 Ω-cm and a thickness of 17 to 20 μm, suitable to the formation of an NPN transistor used for controlling a Power MOS FET. Then a phosphorus ion and an impurity concentration of 1×10¹2 to 1×10¹3 cm-2 used to form an N type silicon area 27 are injected into the Power MOS FET formation section at an acceleration voltage of 100 keV. A P+ type impurity (boron) is diffused for four hours into an element isolation area of a formation portion with a gaseous atmosphere of N₂ at 1000° to 1100°C to form an element isolation P+ type layer 26, as shown in FIG. 3(e). Thermal diffusion is achieved in a gaseous atmosphere of N₂ and O₂ at 1100°C to 1200°C for 8 hours, so that element isolation P+ layer 26 reaches an element isolation P+ type layer 23. In this way, island areas 24a, 24b are formed such that they are surrounded with P+ type layers 23 and 26 and P type silicon layer 20. At this time, N type silicon area 27 extends in a depth direction, as shown in FIG. 3(f). Island areas 24a and 24b are formed as second areas corresponding to the control element in the substrate, and N type silicon area 27 is formed as a high resistance drain area (first area) in the Power MOS FET. In this embodiment, the phosphorus concentration and diffusion time are so selected as to be about 1 Ω-cm, a value suitable to the Power MOS FET at V_DSS =60 V. In this way, the Power MOS FET is formed in N type silicon area 27 and corresponding NPN transistor (control) 52 and CMOS transistor 53 are formed in N- type silicon areas 24a and 24b, respectively, as shown in FIG. 2.

In the first embodiment, epitaxial layer 24 which has a resistivity value suitable to the formation of NPN transistor (control) 52, is deposited as shown in FIG. 3(d), noting that second areas 24a, 24b are formed in epitaxial layer 24. Area 27 (first area) of Power MOS FET 51 in epitaxial layer 24 is set to have a proper resistivity value by means of an impurity diffusion method, as shown in FIG. (e) and FIG. (f).

FIG. 4 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. In the first embodiment, N type silicon 27 (first area) reaches low resistance drain region 21 while, in the second embodiment, first area 27 may be of such a type that it does not reach region 21 in which case thermal diffusion is performed in a shorter time than in the first embodiment, as shown in FIG. 4, for example, for 5 hours in a gaseous atmosphere of N₂ and O₂ at 1100° to 1200°C

FIG. 5(a) and FIG. 5(b) are cross-sectional views showing a semiconductor device according to a third embodiment of the present invention. In the third embodiment, phosphorus is doped into a semiconductor structure to form a low resistance drain region 21 in a Power MOS FET and antimony is doped as an impurity in low a resistance collector region 22 in which case, due to a difference in the diffusion coefficient between the phosphorus and antimony, N an type silicon area 27 is made to be more shallow than a second area 24a. In FIG. 5(a), area 27 is of such a type that it reaches low resistance drain region 21 and, in FIG. 5(b), region 27 does not reach drain region 21.

FIG. 6(a) and FIG. 6(b) are cross-sectional views showing a semiconductor device according to a fourth embodiment of the present invention. In the fourth embodiment, an area including a Power MOS FET is etched to a desired depth.

An N type silicon of a desired resistivity value is epitaxially grown onto that etched section to form an N type silicon area 27a, at which time the surface of the resultant structure is planarized.

In FIG. 6(a), region 27a is of such a type that it reaches a drain region 21 of low resistance and, in FIG. 6(b), region 27a does not reach drain region 21.

FIG. 7(a) and FIG. 7(b) show a fifth embodiment of the present invention. Although in the aforementioned embodiments the drain area of low resistance has been explained as having a varying resistivity value, it is also possible to vary the resistivity value of second area 24a in the control element section as the case may be. In FIG. 7(a), a control element formation area (second area) 24a is so formed through impurity diffusion as to be made different in resistivity from a Power MOS FET formation area. In FIG. 7(b), the second area is selectively etched in the semiconductor structure and a layer is epitaxially grown on the corresponding area of the semiconductor structure so as to be made different in resistivity from the Power MOS FET formation area.

FIG. 8(a) to FIG. 8(f) are cross-section views showing a semiconductor device according to a sixth embodiment of the present invention. In connection with the first to fifith embodiments, an explanation has been made of the semiconductor device in which a source current of a Power MOS FET is taken out from a first major surface side (the upper surface side) of the semiconductor substrate and a drain current from a second major surface side (the lower surface side) of the semiconductor substrate.

In the embodiment shown in FIG. 8(a) through FIG. 8(f), source and drain currents of the Power MOS FET are taken from a first major surface side of the semiconductor substrate. In the embodiment shown in FIG. 8(a) through 8(f) similar reference numerals are employed to designate parts or elements corresponding to those shown in the embodiment of FIG. 2. Reference numeral 40 shows an N+ drain region for taking out the drain current of the Power MOS FET. The semiconductor device is of such a type that the drain area (first area) of high resistance is so formed as to be made different in resistivity from control element formation areas 24a, 24b (second area) and that area 27 reaches the drain region of low resistance. FIG. 8(b) shows a modified form of a semiconductor device in which the first area is so formed through impurity diffusion as to be made different in resistivity from areas 24a, 24b and that the first area does not reach drain region 21 of low resistivity. FIG. 8(c) shows a semiconductor device in which, after the etching of the first area, a layer is epitaxially grown on the surface of the resultant semiconductor structure such that it reaches a drain region 21 of low resistance with the former made different in resistivity from the latter. FIG. 8(d) shows a form of semiconductor device in which after the etching of the first area a layer is epitaxially grown on the surface of the resultant structure such that it does not reach the drain region of low resistance. FIG. 8(e) shows a semiconductor device in which a second region is so formed through impurity diffusion as to vary its resistivity value and FIG. 8(f) shows a semiconductor device in which a second area varies its resistivity value by an etching step and epitaxially growing step. Although, in order to make the first and second areas different in resistivity from each other, the N- type area of high resistance having a lower impurity concentration is converted to the N type area of high impurity concentration in the aforementioned embodiments, the N type area may be changed to the N- type area either by varying their resistivity values through the diffusion of an impurity of the opposite conductivity type or by etching the N type area and epitaxially growing an N- type silicon layer of a lower impurity concentration.

FIG. 9 is a cross-sectional view showing a semiconductor device according to a seventh embodiment of the present invention. In the seventh embodiment, after the formation of N type epitaxial layer 24 (see FIG. 3), an impurity (boron) of the other conductivity type is diffused into area 27 (shown in FIG. 2) in a Power MOS FET to form N type area 27 (shown in FIG. 2) an N- type region 40.

The present invention can also be applied to a Power MOS FET in another element isolation structure.

FIG. 10(a) to FIG. 10(c) show a tenth embodiment of the present invention, that is, a device fabricated by a PN isolation method, device fabricated by a self isolation method and device fabricated by a dielectric isolation method, respectively. In FIG. 10(a), numeral 37a denotes P+ type drain, numeral 37b denotes P³0 P+ type source. In FIG. 10(c), numeral 40 denotes dielectric region, and numeral 41 denotes oxide layers.

Claims

1. A semiconductor device comprising:

a power gate-insulated MOS field effect transistor having a drain region and a control circuit element formed on a common semiconductor substrate, said drain region having a high and a low resistance region, said high resistance region overlaying said low resistance region;

a first area including at least a portion of said high resistance region of the drain region of the power gate-insulated MOS field effect transistor, said first area having a predetermined resistivity value; and

a second area including at least a portion of the area in which said control circuit element is formed, said second area being disposed contiguous to said first area, said second area having a resistivity value less than said predetermined resistivity value of the first area.

2. A semiconductor device according to claim 1, wherein said power gate-insulated MOS field effect transistor has a source current taken from a first major surface side of said semiconductor substrate and has a drain current taken from a second major surface side of said semiconductor substrate, the second major surface side being disposed opposite said first major surface side.

3. A semiconductor device according to claim 1, wherein said power gate-insulated MOS field effect transistor has a source current and a drain current taken from a major surface side of said semiconductor substrate.

4. A semiconductor device according to claim 1, wherein said first area is formed by selectively etching at least a portion of the area that includes said power gate-insulated MOS field effect transistor, and epitaxially growing a layer in said etched portion of the area.

5. A semiconductor device according to claim 1, wherein said second area is formed by selectively etching at least a portion of the area occupied by said control circuit element, and epitaxially growing a layer in said etched portion of the area.

6. A semiconductor device according to claim 1, wherein one of said first and second areas is impurity-diffused for providing different resistivity values to the first and second areas.

7. A semiconductor device according to claim 1, wherein said first area is in contact with said low resistance region of said drain region.

8. A semiconductor device according to claim 1, wherein said first area is not in contact with said low resistance region of said drain region.

9. A semiconductor device according to claim 1, wherein the depth defined by a dimension substantially perpendicular to a major surface of the semiconductor substrate of the first area is substantially smaller than the depth of the second area.

10. A semiconductor device according to claim 1, wherein said first area has an impurity concentration gradient extending into the semiconductor substrate from a major surface thereof in a direction perpendicular to said major surface.

11. A semiconductor device comprising:

a power gate-insulated MOS field effect transistor having a drain region and a control circuit element formed on a common semiconductor substrate, said drain region having a high and a low resistance region, said high resistance region overlying said low resistance region;

a first area including at least a portion of said high resistance region of the drain region of the power gate-insulated MOS field effect transistor, said first area having a predetermined resistivity; and

a second area including at least a portion of the area in which said control circuit element is formed, said second area being disposed contiguous to said first area, said second area having a resisitivity different from said predetermined resistivity of the first area. 12. A semiconductor device according to claim 11, wherein said power gate-insulated MOS field effect transistor has a source current taken from a first major surface side of said semiconductor substrate and has a drain current taken from a second major surface side of said semiconductor substrate, the second major surface side being disposed opposite said first major surface side. 13. A semiconductor device according to claim 11, wherein said power gate-insulated MOS field effect transistor has a source current and a drain current taken from a major surface side of said semiconductor substrate. 14. A semiconductor device according to claim 11, wherein said first area is formed by selectively etching at least a portion of the area that includes said power gate-insulated MOS field effect transistor, and epitaxially growing a layer in said etched portion of the area. 15. A semiconductor device according to claim 11, wherein said area is formed by selectively etching at least a portion of the area occupied by said control circuit element, and epitaxially growing a layer in said etched portion of the area. 16. A semiconductor device according to claim 11, wherein one of said first and second areas is impurity diffused for providing different resistivity values to the first and second areas. 17. A semiconductor device according to claim 11, wherein said first area is in contact with said low resistance region of said drain region. 18. A semiconductor device according to claim 1, wherein said first area is not in contact with said low resistance region of said drain region. 19. A semiconductor device according to claim 11, wherein the depth defined by a dimension substantially perpendicular to a major surface of the semiconductor substrate of the first area is substantially smaller than

the depth of the second area. 20. A semiconductor device according to claim 11, wherein said first area has an impurity concentration gradient extending into the semiconductor substrate from a major surface thereof in a direction perpendicular to said major surface.