Image sensor device having plural photoelectric converting elements

Abstract

An image sensor device provided with a linear array of photoelectric converting elements each having a capacitor on a control electrode area of a semiconductor transistor is disclosed. The image sensor device is provided with means for sequentially selecting the photoelectric converting elements, and the potential of the control electrode area of the selected photoelectric converting element is controlled through said capacitor, thereby accumulating the carriers generated by photoexcitation in said control electrode area and reading a voltage generated according to the amount of carrier accumulation or dissipating thus accumulated carriers.

Description

This application is A--AA--A 11B--11B, and FIG. 12 is an equivalent circuit thereof, wherein same components are always represented by same numbers.

In FIG. 11 there is shown an arrangement in rows and columns, but there may naturally be employed a staggered arrangement of pixels in order to improve the resolving power in the horizontal direction.

Said photosensor cell is provided with a structure as explained in the following. As shown in FIGS. 11A and 11B, there are provided, on an n-type silicon substrate 1101;

a passivation layer 1102;

an insulating oxide layer 1103 composed of silicon oxide;

a separating area 1104 composed of an insulating layer or a polysilicon layer for electrically separating the neighboring photosensor cells;

an n^--type area 1105 of a low impurity concentration formed for example by epitaxy;

a p-type area 1106 formed thereon to constitute a base of a bipolar transistor; an n+ -type area 1107 constituting an emitter of said bipolor transistor;

a wiring 1108 composed of a conductive material such as aluminum for signal readout to the exterior;

a capacitor electrode 1109 opposed to the p-type area 1106 across the insulator 1103 for applying pulses to said p-type area 1106 in the floating state;

a wiring 1110 connected to a capacitor electrode 1109;

an n+ -type area 1111 formed on the bottom face of the substrate 1101 for making ohmic contact; and

an electrode 1112 for supplying a collector potential to said bipolar transistor.

In the equivalent circuit shown in FIG. 12, a capacitor C_ox 1113 is composed, in a MOS structure, of the electrode 1109, insulating layer 1103 and p-type area 1106, while a bipolar transistor 1114 is composed of the n+ -type area 1107 functioning as the emitter, p-type area 1106 functioning as the base and n- -type area 1105 and area 1101 functioning as the collector. Also as will be understood from these drawings, the p-type area 1106 is maintained in the float-state.

In the equivalent circuit, the bipolar transistor 1114 is represented by a junction capacity Cbe 1115 of the base and emitter; a p-n junction diode Dbe 1116 between the base and emitter; a junction capacity Cbc 1117 between the base and collector; and a p-n junction diode Dbc 1118 between the base and collector.

In the following the above-explained photosensor cell will be clarified in further detail, in particular relation to other embodiments to be explained later.

The basic function of said photosensor cell is composed, as already explained before, of a charge accumulation step in response to the incident light, a signal readout step and a refreshing step. In the charge accumulation, the emitter is grounded through the wiring 1108, while the collector is positively biased through the wiring 1112. The base is in advance biased inversely to the emitter 1107.

In such state, as shown in FIG. 11, in response to the entry of light 1120 from the top face of the photosensor cell, a pair of electron and hole is generated in the semiconductor. The electrons flow toward the n-type area 1101 because of the positive bias thereof, but the holes are accumulated in the p-type area 1106, whereby the potential thereof gradually changes toward positive side. The potential V_p caused by the accumulation of photo-generated holes in the base is given by V_p =Q/C, wherein Q is the amount of accumulated charge, while C is a summed function capacity of Cbe 1115 and Cbc 1117.

It is to be noted that the potential V_p generated by the incident light remains almost constant even when the photosensor cell size is reduced to achieve a higher resolving power, since the amount of accumulated charge Q decreases with the decrease in the amount of light per cell while the junction capacity decreases proportional to the cell size. This is due to a fact that the photosensor cell of the present invention can have a very large effective light-receiving area, because of the very simple structure as shown in FIG. 11.

In the following there will be explained an operation of reading a voltage generated by the charge accumulated in the p-type area 1106.

In the signal readout step, the emitter and the wiring 1108 are maintained in the floating state, while the collector is maintained at a positive potential Vcc.

In this state the base potential is equal to -Vb+Vp, wherein -Vb is a negative bias potential of the base 1106 prior to light irradiation, and Vp is the accumulated voltage generated by said irradiation. Then a positive voltage Vr for signal reading is applied to the electrode 1109 through the wiring 1110. Said voltage is divided by the oxide layer capacity C_ox 1113, base-emitter junction capacity Cbe 1115 and base-collector junction capacity Cbc 1117, so that the base potential is shifted to: ##EQU1## With a following additional forward bias Vbs: ##EQU2## the base potential is further biased in the forward direction, in comparison with the voltage Vp accumulated by the light irradiation. Consequently the electrons are injected from the emitter to the base, and reach the collector through acceleration by the drift electric field, because of the positive collector potential.

FIG. 13A is a chart showing the relation between the accumulated voltage Vp in case of Vbs=0.6 V and the signal readout voltage.

It will be understood, from said chart, that the accumulated voltage Vp and the signal readout voltage are linearly proportional over a range in excess of 10,000 times, so that a high-speed signal readout is ensured if the readout time, in which the readout voltage Vr is applied to the capacitor electrode 1109, is selected longer than ca. 100 nsec. In the foregoing example, the wiring 1108 has a capacity of 4 pF while the junction capacity Cbe+Cbc is equal to 0.01 pF, with a ratio of ca. 300 times. However the accumulated voltage Vp generated in the p-type area 1106 is not influenced, and an extremely speedy signal readout is rendered possible by the effect of the bias voltage Vbs. This is due to an effective contribution of the amplifying function of the photosensor cells. In comparison with such high output voltage, the fixed pattern noises and random noises resulting from the output capacity are relatively small, so that an extremely high S/N ratio can be obtained.

It was already explained that a linearity over a range of ca. 10,000 times could be obtained with a high-speed signal readout time of ca. 100 nsec when the bias voltage Vbs is selected equal to 0.6 V. FIG. 13B shows this linearity and the relationship between the signal readout time and the bias voltage Vbs.

FIG. 13B allows to know the signal readout time required by the readout voltage to reach a desired percentage of the accumulated voltage, at a given bias voltage Bvs. Consequently the chart shown in FIG. 13B allows to determine the required bias voltage Vbs, once the signal readout time and the linearity required for the overall design of the image sensor device are determined.

Another advantage of the photosensor cell of the present invention is the possibility of nondestructive readout because the probability of recombination of electron and hole in the p-type area 1106 is quite low. This fact indicates the possibility of a new function in case said photosensor cells are constructed as an image sensor device.

The p-type area 1106 can maintain the voltage Vp for an extremely long time, and the maximum holding time is rather limited by a dark current thermally generated in the depletion layer of the junction. However, in said photosensor cell, the depletion layer is present in the n- -type area 1105 with a very low impurity concentration with a high crystallinity, so that few pairs of electrons and holes are thermally generated.

In the following there will be explained a process of dissipating the charge accumulated in the p-type area 1106.

In the above-explained photosensor cell, the charge accumulated in the p-type area 1106 is not dissipated in the signal readout operation as already explained before. For this reason, in order to enter new optical information, the previously accumulated charge has to be dissipated in a refreshing operation. It is at the same time necessary to maintain the p-type area 1106 in the floating state at a determined negative potential.

In said photosensor cell, the refreshing operation is effected, just like the signal readout, by applying a positive voltage to the electrode 1109 through the wiring 1110. At the same time the emitter is grounded through the wiring 1108. The collector is grounded or maintained at a positive potential through the electrode 1112. FIG. 14A shows an equivalent circuit for refreshing operation, wherein the collector is grounded.

If a positive voltage Vrh is applied to the electrode 1109 in this state, a voltage: ##EQU3## obtained by capacitative division through the oxide layer capacity Cox 1113, base-emitter junction capacity Cbe 1115 and base-collector junction capacity Cbc 1117, is instantaneously applied to the base 112 as in the signal readout step. Said voltage forms a forward bias in the base-emitter junction diode Dbe 1116 and the base-collector junction diode Dbc 1118, thus generating currents therein, whereby the base potential is gradually lowered.

FIG. 14B shows the result of calculation of change in the potential of floating base, as an example of time dependence of the base potential, wherein the abscissa indicates the refreshing time or the time after the application of the refreshing voltage Vrh to the electrode 1109, while the ordinate indicates the base potential, indicating various initial base potentials. The initial base potential is the potential of the floating base when the refreshing voltage Vrh is applied, and is determined by Vrh, Cox, Cbe, Cbe and the charge accumulated in the base.

FIG. 14B indicates that the base potential is not determined by the initial potential but shows a linear change in logarithmic scale after the lapse of a determined time.

The p-type area 1106 can be biased to a negative potential in two ways, by applying a positive voltage through the MOS capacitor Cox for a determined period and then removing said voltage. In one method, a negative charge is accumulated by the flow of positively charged holes from the p-type area 1106 to the n-type area 1101 in grounded state.

On the other hand, it is also possible to accumulate a negative charge in the p-type area 1106 by a flow of electrons from the n+ -type area 1107 and the n-type area 1101 to cause recombination with the holes.

The solid-state solid image sensor device employing the above-explained photosensor cells has a complete refreshing mode, in which the base potential of all the photosensor cells is brought to zero (requiring 10 seconds in the example shown in FIG. 14B), and a transient refreshing mode, in which a variable component resulting from the accumulated voltage Vp is dissipated though a certain base potential remains (requiring 10 μsec to 10 sec in the example shown in FIG. 14B).

The complete refreshing mode or the transient refreshing mode is selected according to the purpose of use of the image sensor device.

In the foregoing there has been given an explanation on the basic function of the above-explained photosensor cell consisting of the charge accumulation in response to the incident light, signal readout and refreshing, and the observation of incident light or the readout of optical information is rendered possible through a basic cycle consisting of the above-mentioned steps.

As explained in the foregoing, the photosensor cell explained above is much simpler in structure in comparison with that disclosed in the aforementioned European Patent Application Laid-open No. 0130276, thus providing an ample possibility for a higher resolving power in the future, and retains the advantages of a low noise level, a high output level, a wide dynamic range and a non-destructive signal readout resulting from the amplifying function.

In the following there will be explained solid-state image sensor devices employing the above-explained photosensor cells.

FIG. 15 is a circuit diagram of an embodiment of a solid-state image sensor device, composed of a one-dimensional array of the above-explained photosensor cells.

In FIG. 15, there are provided three photosensor cells 1530 of which collectors 1512 are commonly connected. Capacitor electrodes 1510 of said photosensor cells 1530 are connected to a horizontal line 1531 for supplying readout pulses and refreshing pulses. Said horizontal line 1531 is connected, through a buffer MOS transistor 1532, to a terminal 1533 for supplying refreshing pulses, and the gate of said buffer MOS transistor 1532 is connected to a terminal 1534. Also the horizontal line 1531 is connected, through a buffer MOS transistor 1535, to a terminal 1536 for supplying readout pulses, and the gate of said transistor is connected to a terminal 1537.

Emitters 1508 of the photosensor cells 1530 are respectively connected to vertical lines 1538, 1538', 1538" for signal readout for each column, and said vertical lines are connected, respectively through gate MOS transistors 1539, 1539', 1539", to the input terminal of a P-type CCD register 1540. The gates of said gate MOS transistors 1539, 1539', 1539" are connected to a terminal 1541 for generating pulses for controlling the vertical lines.

The output terminal of the CCD register 1540 is connected to an output signal line 1542, which is grounded through a refreshing transistor 1543, whose gate is connected to a terminal 1544. Said output signal line 1542 is further connected to the gate of a signal amplifying transistor 1545, of which drain is connected to a load resistor 1546 and an output terminal 1547 for releasing the amplified output signals.

The vertical lines 1538, 1538', 1538" are grounded through refreshing MOS transistors 1548, 1548', 1548", of which gates are commonly connected to a terminal 1549.

In the following there will be given an explanation on the function of the above-explained solid-state image sensor device, while making reference to a timing chart shown in FIG. 16.

At the time t1, the terminal 1549 is maintained at an H-level to turn on the MOS transistors 1548, 1548', 1548" whereby the photosensor cells are grounded through the vertical lines 1538, 1538', 1538". An H-level signal is also supplied to the terminal 1534 to turn on the refreshing MOS transistor 1532. In this state, a refreshing pulse supplied to the terminal 1533 is transmitted through the horizontal line 1531 to provide the bases of the photosensor cells with a voltage Vrh, whereby the refreshing operation is initiated to dissipate the accumulated charges according to the complete refreshing mode or the transient refreshing mode.

At a time t2, the bases of the transistors of the photosensor cells are inversely biased with respect to the emitters, thus initiating a succeeding accumulation. In the refreshing period, all other pulses are maintained at an L-level state as will be understood from the drawing.

In the accumulation period, the electrons of the electron-hole pairs generated by light irradiation can be rapidly dissipated into the collector since the substrate, or the collector of transistor, is maintained at a positive potential.

In the accumulation step, the terminal 1549 is maintained at an H-level state as in the refreshing step to maintain the MOS transistors 1548, 1548', 1548" in the conductive state, whereby the emitters of the photosensor cells are grounded through the vertical lines 1538, 1538', 1538". If the base is saturated with holes under a strong light irradiation, or, if the base becomes biased in forward direction with respect to the grounded emitter potential, the holes flow through the vertical lines 1538, 1538', 1538", so that the base potential no longer moves and is clipped in this state. Consequently the blooming phenomenon can be avoided by the grounding of the vertical lines, even though the emitters of vertically neighboring photosensor cells are commonly connected to the vertical lines 1538, 1538', 1538".

Succeeding to the accumulation period, the signal readout period starts from a time t3, when the terminal 1549 is shifted to an L-level state, and terminal 1537 is shifted to an H-level state, thereby turning off the MOS transistors 1548, 1548', 1548" and turning on the MOS transistor 1535.

At a time t4, a readout pulse of a voltage Vr is supplied to the terminal 1536, whereby the signal readout from three photosensor cells connected to the horizontal line 1531 is effected through the MOS transistor 1535.

Then, at a time t5, an H-level signal is supplied to the terminal 1541 to turn on the MOS transistors 1539, 1539', 1539", whereby the output signals of the photosensor cells are simultaneously supplied to the CCD register 1540. Said output signals stored in the CCD register 1540 are transferred in succession, after the completion of the signal readout period, to the output signal line 1542, then amplified by the transistor 1545 and released through the output terminal 1547. After the transfer of each output signal, a charge remains in the output signal lines 1542, due to a wiring capacity. For dissipating said retentive charge, an H-level signal is supplied to the terminal 1544 in synchronization with the transfer timing of the CCD register 1540, so that the output signals are transferred, in separated state, to the transistor 1545.

In the foregoing explanation, there is assumed an application in which the accumulation period and the signal readout period can be clearly separated, for example in a still video system which has been actively developed in recent years. However the present invention is also applicable, with a suitable modification in the timing of pulses shown in FIG. 16, to the fields in which the function during the accumulation period and that during the signal readout period proceed simultaneously, for example in a television camera or a facsimile apparatus.

In the present embodiment, the final amplifier can be made simpler in comparison with the MOS image sensor device since a high output voltage can be obtained by the amplifying function of each photosensor cell.

The MOS transistor employed as the signal amplifier 1545 in the present embodiment can be naturally replaced by other amplifying means such as a bipolar transistor.

Though the present embodiment employs a p-type CCD register as the CCD register 1540, an n-type CCD register may also be employed if the output charge from each photosensor cell is subtracted from a charge accumulated in advance in the register.

As detailedly explained in the foregoing, the image sensor device of the present invention provides a higher output voltage, a higher sensitivity and a lower noise level, thus enabling to achieve a higher resolving power, in comparison with conventional MOS or CCD image sensor devices.

Besides, the image sensor device of the present invention is capable of a high-speed signal readout operation even for an increased number of photosensor cells, thus providing a high-speed operation combined with a high resolving power, since the signals from plural photosensor cells are temporarily retained in holding means and then released sequentially.

Also in a two-dimensional array, the photosensor cells can have a uniform accumulation time, thus ensuring a stable photoelectric converting characteristic, because each photosensor cell can be refreshed immediately after the signal readout operation. Also a high-speed operation is rendered possible because of the absence of idle time after the completion of signal read-out as in the conventional structure.

Furthermore, the image sensor device of the present invention can achieve a higher packing density because a pixel is comprised of a single transistor, and still shows significantly reduced blooming and smear phenomena. It also provides a higher sensitivity and a wider dynamic range.

Also, the amplifying function of the photosensor cells themselves allows to obtain a high signal voltage without relying on the wiring capacity, to achieve a low noise level and facilitates the designing of peripheral circuits.

Also, the transfer of the output signals from the photosensor cells with a CCD register allows to achieve a higher packing density in comparison with the conventional structure involving complex shift registers, and easily achieves a transfer frequency in excess of 100 MHz required in high-speed signal processing.

Also, a high degree of integration can be attained with a high S/N ratio, since the output impedance of the CCD register is maintained low even in an array involving several thousand photosensor cells.

Claims

1. An image sensor device comprising a linear array of photoelectric converting elements each having a semiconductive transistor with a control electrode area and having a capacitor on said control electrode area, and selector means for sequentially selecting said photoelectric converting elements, wherein the potential of the control electrode area of a thus selected photoelectric converting element is controlled through said capacitor of the selected photoelectric converting element, thereby accumulating carriers generated by photoexcitation in said control electrode area and reading a voltage generated according to the amount of said accumulation or dissipating the thus accumulated carriers; said selector means comprising:

a shift register having readout terminals provided corresponding to respective photoelectric converting elements;

first switching means, for refresh, connected to said capacitor of a corresponding photoelectric converting element and to a refresh terminal; and

second switching means, for refresh, connected to said control electrode area and said capacitor of a corresponding photoelectric converting element.

2. An image sensor device comprising a linear array of photoelectric converting elements each having a semiconductive transistor with a control electrode area and having a capacitor on said control electrode area, and selector means for selecting said photoelectric converting elements, wherein the potential of the control electrode area of a thus-selected photoelectric converting element is controlled through said capacitor of the selected photoelectric converting element, thereby accumulating carriers generated by photoexcitation in said control electrode area and reading a voltage generated according to the amount of said accumulation or dissipating the thus-accumulated carriers; said selector means comprising:

a shift register having plural readout and refresh terminal means provided corresponding to respective photoelectric converting elements and each connected to said capacitor of a corresponding photoelectric converting element for supplying to said capacitor first a read signal for reading the voltage out from the corresponding photoelectric converting element, and then a refresh signal for refreshing said corresponding photoelectric converting element. 3. An image sensor device according to claim 2, wherein each said read and refresh terminal means further comprises a read terminal and a refresh terminal both connected to said capacitor of said corresponding photoelectric converting element.

4. An image sensor device according to claim 2, wherein said read and refresh terminal means further comprises a read and refresh terminal connected to said capacitor of said corresponding photoelectric converting element, for supplying both the read signal and the refresh signal thereto; and further comprising additional refresh means connected to both said capacitor and said control electrode area of said photoelectric converting element for applying a predetermined signal thereto for refresh.