Method for fabricating isolation region in semiconductor devices

Abstract

A method for fabricating an isolation region in a semiconductor substrate that produces neither a "bird's beak" nor a "bird's head". A smooth substrate surface is provided, which is preferable for multi-layered wiring. The packing density of devices in a bipolar IC circuit can be increased. A sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching. The inner surface of the isolation groove is coated by an insulating film. Then the groove is buried with polycrystalline semiconductor material. The polycrystalline material which is deposited on the surface of the substrate is etched off. At the same time the polycrystalline material in the groove is also etched to a specific depth from the surface. An insulating film is then deposited so as to again fill the groove. Then the substrate surface is polished or etched to provide a flat surface.

Description

of layers are formed for fabricating semiconductor devices.

The surface of the substrate is coated by a silicon dioxide (SiO₂) film 14 about 1000 Å thick. A silicon nitride (Si₃ N₄) layer 15 about 2000 Å thick is then formed. These films are fabricated by methods such as thermal oxidation and chemical vapor deposition (CVD).

Then, by photolithographic etching, a window corresponding to the groove to be formed at the position 16 for the isolation region is opened in the Si₃ N₄ film 15. Using the remaining Si₃ N₄ film as a mask, a U-shaped groove of about 4 to 5 microns deep and about 2 to 3 microns wide is made by dry etching at the position 16. The dry etching applicable to this process is a reactive ion etching using a mixture of carbon tetrachloride CCl₄) and boron trichloride (BCl₃). By the reactive etching (which is disclosed in U.S. Pat. No. 4,104,086 issued Aug. 1, 1978 to J. A. Bondur and H. G. Pogge) the side walls of the groove are etched vertically to shape a U-shaped groove. The bottom of the groove reaches to the p-type substrate 11 by cutting through both layers 12 and 13.

In an ordinary IC process as shown in FIG. 5, boron ions are implanted by ion implantation technology to form a p+ -region highly doped by a p-type dopant at the bottom of the groove. This region is used as a channel stopper of the device, but it is not related explicitly to the present invention. Accordingly, in the further description and figures the channel stopper is omitted.

In the next step of the process, as shown in FIG. 6, the inner surface of the groove is coated with a SiO₂ film 17 by thermal oxidation, to a thickness of about 2000 to 3000 Å. Then an undoped polycrystalline semiconductor material such as polysilicon is deposited over the surface of the substrate, and the groove is buried thereby.

The polysilicon 18 deposited on the surface of the Si₃ N₄ film 15 is removed by chemical wet etching as shown in FIG. 7. A commonly used etchant such as caustic potash (KOH) or a mixture of nitric acid (NHO₃) and hydrofluoric acid (HF) may be used. By this etching process the upper part of the polysilicon burying the groove is also etched. The depth of etching at the groove is controlled to about 0.5 to 1 micron from the surface of the Si₃ N₄ film 15, although a shallower depth such as 0.2 micron is also possible. This control is not so critical but it is important for preventing a bird's beak and a bird's head from growing.

Next, as shown in FIG. 8, an insulating layer 19 such as a layer of SiO₂ is deposited on the surface of the substrate by a bias sputtering method. By this process the groove is buried again, but this time by SiO₂. Bias sputtering is a preferable method for depositing SiO₂ on the surface of a target which is electrically biased at about a hundred and a few tens of volts. It is an easy method for coating the inner surface of the groove with SiO₂ with a good coverage. The bias sputtering method is disclosed in Japanese Patent Application No. Tokukaisho 55-13904 by Tsuenkawa et al. This bias sputtering process may be replaced by an ordinary CVD method.

Next, as shown in FIG. 9, the SiO₂ film deposited on the surface of the Si₃ N₄ film 15 is removed by etching. A wet etching by hydrofluoric acid or a dry etching using trifluoromethane gas are applicable. These etching methods are effective for the SiO₂ deposited by the aforementioned bias sputtering method. For the SiO₂ deposited by a chemical vapor deposition process, chemical polishing is effective for the same purpose. The Si₃ N₄ is removed with boiling phosphoric acid (H₃ PO₄).

Comparing FIG. 9 with FIG. 3, it will be apparent that an isolation region fabricated by the present invention has neither a bird's beak nor a bird's head. A self-aligned walled based and walled emitter can be applied without any change in the ordinary process. The polysilicon 18 is buried deep in the SiO₂ film 19. Accordingly, there is no need for anxiety that the polysilicon may be exposed by the etching of the above process to cause leakage in an electric circuit of a device.

A smooth surface is provided that is preferable for multilayered wiring. It will be clear that the packing density of devices in an IC can be increased to a greater extent than with conventional isolation grooves.

As has been described in the above explanation, the present invention does not need any new or special process to provide an isolation region. Further, it can be applied to any type of device.

Claims

1. A method for fabricating an isolation region in a semiconductor device formed with a semiconductor substrate having a U-shaped isolation groove, comprising:

coating said isolation groove with a first insulating layer:

filling the coated groove with polycrystalline semiconductor material at least to a first depth below the surface of said substrate; and

depositing a second insulating layer on said polycrystalline semiconductor material so as to at least fill said isolation groove up to said substrate surface.

2. The method of claim 1, comprising, prior to depositing said second insulating layer:

continuing said filling of said coated groove with said polycrystalline semiconductor material to fill said coated groove above said first depth; and

etching said polycrystalline semiconductor material in said coated groove down to said first depth.

3. The method of claim 2, said filling of said coated groove with said polycrystalline semiconductor material also comprising depositing said polycrystalline semiconductor material on said substrate surface, said method comprising continuing said filling of said coated groove with said polycrystalline semiconductor material so as to bury said isolation groove, prior to said etching of said polycrystalline semiconductor material to said first depth.

4. The method of claim 2 or 3, said etching of said polycrystalline semiconductor material

comprising a wet etching process. 5. The method of claim 1, 2 or 3, comprising forming 19, wherein said first depth location is at a distance to be in the range of from 0.2 to 1.0 micron from below the exposed upper surface of

said substrate surface. 6. The method of claim 1, 2 or 3 19, comprising providing said substrate to be of silicon, each said insulating layer to be of silicon dioxide, and said

polycrystalline semiconductor material to be of silicon.

7. The method of claim 1, 2 or 3, wherein the top surface of said second insulating layer provides said substrate surface with an effectively flat surface in the vicinity of the isolation region and the isolation region is provided with a width that is effectively the width of the isolation groove.

8. The method of claim 1, 2 or 3, said depositing of said second insulating layer including coating the surface of said substrate with said second insulating layer, said method further comprising:

continuing said depositing of said second insulating layer so as to bury said coated groove; and

removing said second insulating layer on said substrate surface and from above said substrate surface over said isolation groove.

9. The method of claim 8, comprising providing said substrate to be of silicon, each said insulating layer to be of silicon dioxide, and said polycrystalline semiconductor material to be of silicon.

10. The method of claim 8, said removing of said second insulating layer comprising at least one of etching and polishing.

11. The method of claim 8, wherein the top surface of said second insulating layer provides said substrate surface with an effectively flat surface in the vicinity of the isolation region and the isolation region is provided with a width that is effectively the width of the isolation groove.

12. The method of claim 8, comprising forming said first depth to be in the range

from 0.2 to 1 micron from said substrate surface. 13. The method of claim 12, comprising providing 5, wherein said first defined depth to be is at a distance of at least 0.5 microns micron below the

exposed upper surface of said substrate. 14. The method of claim 8, said method 19, further comprising forming said substrate of a slice of single crystal semiconductor with at least one layer of doped semiconductor as the top on the major surface of the slice and a semiconductor oxide layer superposed on the top doped layer,

forming said isolation groove being deeper than each said doped layer, and

forming the thickness of said layer of semiconductor oxide to be smaller

than said first depth. 15. The method of claim 14, comprising

forming a layer of semiconductor nitride in superposed relationship on said layer of semiconductor oxide, prior to forming said coating of said groove with said first insulating layer on the sidewalls and the bottom wall of said groove, and

removing said layer of semiconductor nitride after said removing of a portion of said second insulating layer.

16. The method of claim 15, comprising providing the thickness of said layer of silicon nitride to be smaller than said first depth.

17. The method of claim 15, wherein the top surface of said second insulating layer provides said substrate surface with an effectively flat surface in the vicinity of the isolation region abd the isolation region is provided with a width that is

effectively the width of the isolation groove. 18. The method of claim 15, comprising providing said substrate and said polycrystalline semiconductor material to be of silicon, each said insulating layer and said layer of semiconductor oxide to be of silicon oxide (SiO₂), and said semiconductor nitride to be of silicon nitride. 19. A method for producing and filling an isolation groove in a semiconductor substrate, the substrate having a major surface and successive, doped and insulating layers formed in superposed relationship on the major surface for forming semiconductor devices therein and defining an upper surface of the substrate substantially parallel to the major surface of said substrate, the isolation groove having substantially parallel interior sidewalls, spaced apart and defining the width of the groove and extending, transversely to the upper surface, through the superposed insulating and doped layers and into the substrate and defining the depth of the groove and an interior bottom wall within the substrate, the depth of the groove being greater than the width thereof, comprising:

(a) forming a mask layer on the upper surface of the semiconductor substrate, the mask layer having a window extending therethrough and exposing a portion of the upper surface of the semiconductor substrate at which an isolation groove is to be formed;

(b) etching the successive, doped and insulating layers and the semiconductor substrate in the respective portions thereof, as exposed in succession through the mask layer during the etching, thereby to form the isolation groove;

(c) thermally oxidizing the sidewalls and the bottom wall of the groove to form a first insulating layer as a coating on each of the sidewalls and the bottom wall;

(e) etching the deposited polysilicon semiconductor material through the window in the mask for removing a portion of the deposited polysilicon semiconductor material from within the groove such that the resulting, exposed upper surface thereof is substantially at the aforesaid, defined depth location;

(f) depositing insulating material on the substrate by a sputtering method or a chemical vapor deposition method, thereby both to fill the groove with a second insulating layer extending from said resulting, exposed upper surface of the deposited polycrystalline semiconductor material and thus from the aforesaid depth location and up to the major surface of the substrate, and also to bury the groove and the second insulating layer with further said insulating material; and

(g) etching said further insulating material while employing the mask layer as an etching stopper thereby to remove a portion of the further insulation material of said second insulating layer sufficient to expose the mask layer, thereby forming a common, flat upper surface of the second insulating layer and the exposed upper surface of the substrate. 20. The method of claim 19, wherein the step of etching of the material of the second insulating layer comprises:

wet or dry etching of the second insulating layer, as filled in the isolation groove by a sputtering method, to provide the common, flat upper surface of the second insulating layer and the exposed upper surface of the substrate. 21. The method of claim 19, wherein the step of etching of the material of the second insulating layer comprises:

chemically polishing the second insulating layer, as filled in the isolation groove by a chemical vapor deposition method, to provide the common, flat upper surface of the second insulating layer and the exposed upper surface of the substrate.