Floating gate memory with improved dielectric

Abstract

The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

Description

820 is then grown to a thickness of e.g., 600 angstroms, which at the same time partially oxidizes the 200 angstrom silicon nitride layer. However, the nitride oxidation is a self-limiting process, and only about 10 angstroms of oxide forms on top of the nitride layer 18. This tends to plug up any pinholes in the thin nitride layer.

The layer of oxide is not only quite thin, but is also not truly separated from the nitride layer. That is, a region of graded oxide/nitride composition will exist instead of a sharp boundary, and for this reason the oxide layer is not shown separately in FIGS. 6a, 6b, 7 and 8. That is, it is more correct to refer to a composite layer than to separate layers.

This is a major source of the advantages of the present invention, in that, not only are the nitride pinholes out of alignment with the underlying oxide pinholes, but also the nitride pinholes themselves tend to be plugged by the reoxidation step.

After performing any transistor threshold adjustments, the second level polysilicon is deposited, doped (e.g. with phosphorous oxychloride) and patterned and etched in the peripheral circuits. A separate patterning step is used for the control gates. Any exposed nitride is also etched at this step.

The source/drain implants are then performed, and the refill oxide is grown.

Because silicon nitride has a higher dielectric constant than silicon dioxide (approximately 7 vs. 4), a layer of silicon nitride is electrically equivalent to a thinner layer of silicon dioxide. For example, in the presently preferred embodiment, a 200 angstrom layer of silicon nitride has the same approximate electrical thickness as 120 angstroms of silicon dioxide, so that the total equivalent thickness of the dielectric layer formed is equivalent to about 350 angstroms of silicon dioxide. This permits the formation of polysilicon capacitors with a specific capacitance in the neighborhood of 0.8 picofarads per square mil.

It should be noted that the uniformity of specific capacitance across the wafer is strongly dependent on the uniformity of the silicon nitride layer. However, low pressure chemical vapor deposition has been found to give excellent uniformity for nitride layers as thin as 100 angstroms.

Although formation of capacitors between two polysilicon levels has been primarily referred to, this is not strictly necessary. For example, the dielectric according to the present invention can easily be formed between a first polysilicon floating gate layer and a polycide (i.e. polysilicon/silicide composite), pure silicide, or metal top layer.

Moreover, it is also possible to form a thin uniform capacitor dielectric according to the present invention over a polycide or pure silicide first layer, although this is not the preferred embodiment of the invention. In this case, the oxide and nitride dielectric layers would both preferably be deposited. With silicide or polycide, as with polysilicon, the surface of the silicide layer will normally be uneven. Thus, the same difficulties caused by physical excursion exists with silicide or polycide as exists with polysilicon. Moreover, in silicide and polycide as in polysilicon, a significant fraction of dopant impurities will normally be included in the material, and these impurities which are uncontrolled with also affect the oxidation rate of the first plate material in an uncontrolled manner. Most silicides are susceptible to partial oxidation (niusance oxidation) during the oxidizing condition which are used to form the second gate oxide, and therefore the present invention is useful to avoid growth of an uncontrolled thickness of silicon and metal oxides over a silicide bottom layer.

The process flow of the presently preferred embodiment will now be described in somewhat greater detail. This process flow fabricates an EPROM design for 21 volt operation. However, this device scales to other voltages, as will be discussed below. Moreover, the present invention is also directly applicable to EEPROM fabrication, as will be discussed below.

On a silicon substrate 10, 350 angstroms of an initial oxide 15 and 1000 angstroms of an initial nitride 16 are formed. A first resist level 12 is then patterned to define most areas 14, in which active devices are to be formed. The initial nitride layer 16 is then etched to remove the nitride from the most regions 14. regions not covered by first resist level 12. At this point a channel stop implant is also performed, e.g. 1.7×10¹3 per square centimeter of boron at an energy of 100 keV. This concentration of boron will form the channel stops 18. This results in the structure shown in FIG. 1.

Next, the resist level 12 is stripped. The channel stop implant 18 is in yield, the field oxidation is performed to provide a field oxide 20 which is approximately 1.3 microns thick. This produces the device structure shown in FIG. 2.

The initial nitride 16 and the initial oxide 15 are then stripped. Preferably a dummy gate oxide is grown at this point in the most regions to a thickness of approximately that of the gas oxide which will follow, or 600 angstroms in this embodiment. This dummy gate oxide is sacrificial, and is immediately stripped. The gate oxide 22 is then grown, e.g. to a thickness of 600 angstroms. The threshold voltage implants are then performed. Note that threshold voltages for three kinds of transistors must be defined. In the presently preferred embodiment, boron is first implanted, as a dose, of, e.g., 2.5×10¹1 per centimeter squared at 35 keV, to define the threshold for the floating gate transistors and for the "natural" (enhancement-mode) devices. This is a blanket implant which is applied overall. Next, a resist layer 24 is patterned, and a phosphorus implant is used to define threshold voltages of the P depletion transistors, e.g. at a dose of 1.15×10¹2 per square centimeter and an energy of 150 keV. This step is shown in FIG. 3.

The resist layer 24 is then stripped, and the first polysilicon layer 26 (referred to as "polysilicon 1") is deposited and POCl₃ doped. The inner level oxide 28 and the interlevel nitride 30 are then formed or deposited, as extensively described above. A resist level 32 is then patterned to define the desired configuration of the polysilicon 1 level, and the nitride 30, the oxide 28, and the polysilicon 26 are anisotropically etched in accordance with the resist level 32. This results in the structure shown in FIG. 4. The resist level 32 is then stripped, and a further resist level 34 is then applied to pattern a further implant to set the voltages of enhancement transistors. For example, a boron B implant of 3×10¹1 at 35 keV is preferably used. This results in the structure shown in FIG. 5. This resist level is then stripped. The first gate oxide 22 is then stripped away wherever it is exposed, and a second gate oxide 36 is then grown. As noted above, this same second gate oxidation step will also grow a small amount of oxide in the top portion of the inner level nitride layer 30. A second polysilicon level 38 is then deposited and doped, and a layer 40 of molybdenum silicide is also deposited overall. A mask layer 42 is now used to pattern the silicided second polysilicon level 38, 40 in the periphery. However, it should be noted that the second polycide 38, 40 is not patterned at this time in the array. The second polycide layer 38, 40 is then etched, resulting in a structure as shown in FIG. 6a.

The resist level 42 is now stripped, and the silicided second polysilicon level 38,40 is patterned in the array. Anisotropic etches are now performed, according to a further resist layer 44, to cut through the silicide layer and second polysilicon layers 40,38, the interlevel oxynitride stack 28,30, and the first polysilicon level 26. That is, a stack etch is preferably used, to produce a structure as shown in FIG. 6b.

The resist level 44 is then stripped, as is any remaining portion of the second gate oxide 36, 7and arsenic as shown in FIG. 7. Arsenic is then implanted, preferably at a dose of 1×10¹6 per centimeter squared at 50 keV, to form source/drain regions 46. This process step is shown in FIG. 7 8.

An implant anneal step is then performed, and a refill oxide 48 is then grown. Preferably this is a thermal oxide, since its purpose is to provide very good isolation of the floating gate portions of the first polysilicon 26. In particular, this refill oxide layer 48 serves to isolate the impurities used to obtain a low reflow temperature in a multilevel oxide 50 from the floating gates. A multilevel oxide is then applied, which results in the structure as shown in FIG. 8. Processing continues with contact etching and metallization steps, to interconnect the devices thus formed to form a functional complete integrated circuit chip, but these steps are entirely conventional and well known to those skilled in the art.

The present invention has been described with reference to a 600 angstrom gate oxide process for a 21 volt operating voltage, but this thickness is readily scalable. For example, the thicknesses of the first and second gate oxides can both be scaled down to 400 angstroms with interlevel dielectric thicknesses as given to produce a 15 volt part. Scaling to other voltages in straightforward.

The present invention is also applicable to EEPROM parts. In EEPROMS, a separate very thin tunnel oxide is typically separately patterned underneath the first polysilicon level. For example, in a 21 volt part with 600 angstrom gate oxides, a 150 angstrom tunnel oxide can be used underneath the first polysilicon floating gate portions, to provide an area where tunneling is easy.

As will also be obvious to those skilled in the art, the present invention can be applied in a wide variety of other floating gate process, wherever close capacitative coupling of an amorphous silicon-containing floating gate to an overlying control gate is desired.

The present invention advantageously provides a method for fabricating capacitors having high specific capacitance in a standard MOS process.

The present invention advantageously provides a thin polysilicon-to-polysilicon dielectric having a very low density of pinholes.

The present invention advantageously provides a method for growth of a second gate oxide without simultaneously growing a thick oxide over first polysilicon.

The present invention advantageously provides a method for growing a second gate oxide without increasing the thickness of a dielectric over a first polysilicon level.

The present invention advantangeously provides a method for forming polysilicon-to-polysilicon capacitors with highly uniform specific capacitance across the wafer.

The present invention advantageously provides a method for fabricating high voltage MOS integrated circuits, in which the thickness of the dielectric between the first and second polysilicon levels can be selected to be equal to or less than the thickness of the second gate oxide.

As will be obvious to those skilled in the art, the present invention provides a process innovation having very wide applicability, and can be practiced in the context of a very wide variety of integrated circuit processes, and with a very wide variety of modifications and variations. The scope of the claimed invention is therefore not limited except as specified in the accompanying claims.

Claims

1. A floating gate memory cell device comprising:

(a) a silicon substrate;

(b) a plurality of polysilicon insulated floating gates overlying a first gate insulating layer on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate;

(c) at least one other transistor gate overlying a second gate insulating layer on said silicon substrate;

(c) (d) a plurality of polysilicon control gates over respective ones of said floating gates;

(d) (e) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates;

(e) (f) a plurality of source and drain regions respectively separated by respective ones of said channel regions; and

(f) (g) means for applying a write voltage to a selected one of said control gates,;

(g) (h) said voltage being about 15 volts when said dielectric is about 400 angstroms, said voltage varying therefrom proportionally with the thickness of said dielectric when the thickness of said second gate insulating layer is about 400 angstroms, 21 volts when the thickness of said second gate insulating layer is about 600 angstroms, said voltage varying therefrom proportionally with the thickness of said second gate insulating layer.

2. The device of claim 1 further comprising means for applying a read voltage between a selected one of said sources and said respective corresponding drain.

3. A floating gate memory cell, comprising:

(a) a silicon substrate;

(b) a plurality of polysilicon insulated floating gates on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate;

(c) a plurality of polysilicon control gates over respective ones of said floating gates;

(d) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates;

(e) a plurality of source and drain regions respectively separated by respective ones of said channel regions; and

(f) means for applying a write voltage to a selected one of said control gates,

(g) said voltage being about 21 volts when said dielectric is about 600 angstroms, said voltage varying therefrom proportionally with the thickness of said dielectric.

4. The device of claim 3 further comprising means for applying a read voltage between a selected one of

said sources and said respective corresponding drain. 5. The device of claim 1, wherein the thickness of said first insulating layer is about the thickness of said second insulating layer. 6. The device of claim 1, wherein said plurality of polysilicon insulated floating gates is formed from a first layer of polysilicon and said at least one other transistor gate and said polysilicon control gates are formed from a second layer of polysilicon. 7. A floating gate memory device, comprising:

(a) a silicon substrate;

(b) a plurality of polysilicon insulated floating gates overlying a first insulating layer on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate;

at least one other transistor gate overlying a second insulating layer on said silicon substrate,

(c) a plurality of polysilicon control gates over respective ones of said floating gates;

(d) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates, said composite dielectric being thinner than said second insulating layer;

a plurality of source and drain regions respectively separated by respective ones of said channel regions;

and means for applying a write voltage to a selected one of said control gates and means for applying a voltage of a magnitude of about said write

voltage to said at least one other transistor gate. 8. The device of claim 7, wherein the thickness of said first insulating layer is about the thickness of said second insulating layer. 9. The device of claim 7 further comprising means for applying a read voltage between a selected one of said sources and said respective corresponding drain. 10. The device of claim 7, wherein said plurality of polysilicon floating gates is formed from a first layer of polysilicon and said at least one other transistor gate and said polysilicon control gates are formed from a second layer of polysilicon.