TTL/CMOS compatible input buffer with Schmitt trigger

Abstract

A TTL/CMOS compatible input buffer circuit comprises a schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the schmitt trigger. The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.

Description

CROSS-REFERENCE TO COPENDING PATENT APPLICATION

Copending U.S. patent application Ser. No. 788,344, filed Sept. 19, 1985 on behalf of H. C. Hsieh and assigned to the same assignee, off on. The DC characteristic of the Schmitt trigger is then determined by transistors M3 and M4 that provide a higher trigger point than the inverter comprising transistors M1, M2 and M3.

In operation of the input buffer, a power down (PD) control signal is applied to transistor P4 of the reference voltage generator 20. P4 is coupled to a voltage supply V_cc and to ground potential through series resistors R1 and R2. Resistor R1 has a resistance value greater than that of R2, in this implementation, being in the ratio of 5R:2R, by way of example. The resistance values are selected so that the reference voltage at node T1A is at the midpoint of the range of TTL values, taht that is at 1.4 Volts approximately. When transistor P4 is on, the reference voltage on node T1A is substantially equal to the desired trigger point of the Schmitt trigger 10, which is the selected value between the low level TTL signal (0.8 volts) and the high level TTL signal (2.0 Volts).

The voltage at node T1A is applied to the inverting input lead 26 of operational amplifier 25. Capacitor C1 which is connected between T1A and ground smooths any glitches that may be caused by power supply perturbations. The noninverting input lead 27 of the op amp 25 is connected to the ouptut output node T2A of the reference input buffer stage 11A of the reference voltage generator. The reference input buffer stage 11A comprises a P-channel transistor P2, an N-channel transistor N2, an N-channel transistor N3, and an N-channel transistor N4. The configuration of the reference input buffer stage 11A is substantially equivalent to that of the Schmitt trigger 10, except that the node T2A is shorted to the gates of P2, N2 and N3. The ratios of the sizes of the transistors P2, N2, N3 and N4 are substantially the same as the ratios of sizes of transistors M1, M2, M3 and M4, respectively. The output signal of the operational amplifier 25 controls the gate of a P-channel transistor P3, which is a relatively large transistor. The transistor P3 acts as a true voltage source and limits excursions of the voltage at node T3A. P3 supplies transient current for all input buffers in the system, which are similar to the Schmitt trigger input buffer 29, and is connected to the output lead 21 of the reference voltage generator 20. A capacitor C2, which is a large capacitor having a capacitance value of 50 picoFarads, by way of example, is connected to output lead 21 of the reference voltage generator 20 and serves to stabilize the reference voltage.

The Schmitt trigger input buffer 29 includes an output stage comprising an inverter formed with a P-channel transistor MR M5 and N-channel transistor M6. The transistor M5 is a native P-channel transistor having a threshold voltage of about -1.6 Volts±0.2 Volts, so that the inverter formed by the M5 and M6 transistors does not consume DC power when V_REF has a value greater than or equal to 3.5 volts approximately.

Since the voltage on the gates of transistors P2, N2 and N3 is the same as the voltage on node T2A connected to the drains of transistors P2 and N2, the trigger point of the reference input buffer is in effect the voltage at node T2A, which is connected to the noninverting lead 27 at the input of op amp 25. The output signal from the op amp 25 is fed to the gate of P3 to establish a reference voltage at node T3A so that the voltage at the node T2A approaches the desired level of about 1.4 volts.

Since the ratios of the sizes of the transistors of the Schmitt trigger 10 are the same as the ratios of the sizes of the transistors of the reference input buffer stage 11A, and since the node T3A is connected to node T1 of the Schmitt trigger, the trigger point of the Schmitt trigger is the same as the trigger point of the reference input buffer, which is at the desired approximate 1.4 volt level.

FIG. 2 illustrates two waveforms, representing the reference voltage V_REF, and the trigger voltage V_TRIG with slow input transistions and a noisy reference voltage that produces a indeterminate output signal. A feature of the invention is that the Schmitt trigger input buffer with its hysteresis characteristic overcomes the effect of the slow input transistions. The hysteresis of the Schmitt trigger, which is controlled by the transistor sizes, causes a change in the threshold level of the trigger. The Schmitt trigger is characterized by two trigger points which are higher and lower than the desired 1.4 volt trigger level respectively. The trigger points are switched in response to the rising and falling edges of the input signal V_IN. By virtue of the hysteresis of the Schmitt trigger, a significant improvement is realized in noise immunity for noise on the reference voltage and for noise on the input signal.

FIGS. 3a and 3b show the transfer curves for a normal inverter and a Schmitt trigger respectively, illustrating the hysteresis characteristic of the Schmitt trigger.

FIG. 4 represents a computer simulation obtained by simulating the operation of the Schmitt trigger input buffer in a noisy reference voltage environment. The input buffer of this invention affords better noise immunity and improves the tolerance to the noise level of the reference voltage, thereby increasing the reliability of the input buffer even when the input signal has a very slow transition time.

Claims

1. A TTL/CMOS compatible input buffer network comprising:

a reference voltage generator for providing a reference voltage at a coupling electrical lead;

a schmitt trigger input buffer coupled to said electrical lead;

said reference voltage generator comprising a reference input buffer stage having a first p-channel enhancement transistor, and first, second and third n-channel enhancement transistors;

an operational amplifier having a noninverting input terminal, an inverting input terminal, and an output lead;

a large p-channel enhancement transistor having gate, source and drain electrodes, the gate electrode of said large p-channel transistor being coupled to the output lead of said operational amplifier, and the drain electrode of said large p-channel transistor being coupled to said coupling electrical lead and to said p-channel transistor of said reference input buffer stage;

said operational amplifier, large p-channel transistor, and first p-channel transistor forming a negative feedback loop;

means for applying a fixed reference voltage to said inverting terminal of said operational amplifier;

means for connecting said noninverting terminal of said operational amplifier to the gate electrodes of said transistors of said reference input buffer stage;

said schmitt trigger input buffer comprising a schmitt trigger having a first p-channel enhancement transistor and first, second and third n-channel enhancement transistors; and an output stage having a native p-channel enhancement transistor and a fourth n-channel enhancement transistor, the gates of said native p-channel transistor and fourth n-channel transistor being connected to a node between said first p-channel enhancement transistor and said first n-channel enhancement transistor of said schmitt trigger.

2. A TTL/CMOS compatible input buffer network as in claim 1, wherein the configuration, ratios and electrical characteristics of said p-channel and n-channel transistors of said schmitt trigger are matched and substantially equivalent to the configuration, ratios and electrical characteristics of said p-channel and n-channel transistors respectively of said reference input buffer stage; and

wherein said reference input buffer stage includes an electrical shorting connection for connecting a node between said first p-channel and said first n-channel enhancement transistors to the gate electrodes of said first p-channel and said first, second and third n-channel enhancement transistors.

3. A TTL/CMOS compatible input buffer network as in claim 1 including in which said means for applying a fixed reference voltage to said inverting terminal of said operational amplifier comprises;

first and second resistors connected in series and to a voltage source; and means for connecting said inverting input terminal of said operational amplifier to a node between said resistors.

4. A TTL/CMOS compatible input buffer network as in claim 1 including a large capacitor connected to said coupling electrical lead for damping noise on said reference voltage.

5. A TTL/CMOS compatible input buffer network comprising:

a schmitt trigger circuit having a higher trigger point to rising input signals and a lower trigger point to falling input signals, and having an input line for receiving an input signal, an output line for providing an output signal, a ground terminal for being connected to a ground voltage, and a reference voltage lead which receives a reference voltage, said schmitt trigger circuit comprising a plurality of transistors connected to form a schmitt trigger;

a reference stage having transistors corresponding to each of said transistors of said schmitt trigger circuit and having input and output lines, a ground terminal, and a reference voltage lead corresponding to those of said schmitt trigger circuit, said transistors of said reference stage having length to width ratios substantially the same as corresponding transistors of said schmitt trigger circuit, said transistors of said reference stage being connected to each other as in said schmitt trigger circuit, and additionally said input and output lines of said reference stage being shorted together to supply a reference stage output voltage which is between said trigger points of said schmitt trigger circuit; and

a reference voltage establishing circuit which receives a selected voltage and said reference stage output voltage, and generates said reference voltage such that said reference voltage such that said reference stage output voltage is equal to said selected voltage.

6. A TTL/CMOS compatible input buffer network as in claim 5 in which said reference voltage establishing circuit comprises:

a large transistor, large enough to supply transient current for all input buffers in a system, said large transistor having a first current carrying terminal connected to a supply voltage and a second current carrying terminal for supplying said reference voltage, and a control terminal; and

an operational amplifier which:

in a TTL mode receives said selected voltage and said reference stage output voltage and provides an output signal to said control terminal of said large transistor, which generates said reference voltage, and

in a CMOS mode is disabled, whereby said large transistor is fully on and provides said supply voltage as said reference voltage;

said TTL/CMOS compatible input buffer network further comprising means for switching between said TTL mode and said CMOS mode.

7. A TTL/CMOS compatible input buffer network as in claim 5 in which said reference voltage establishing circuit comprises:

a large transistor having one current carrying terminal connected to a supply voltage and a second current carrying terminal for providing said reference voltage; and

an operational amplifier which receives said selected voltage on one input terminal, said reference stage output voltage on another input terminal and which provides on an output terminal a control signal for controlling said large transistor.