Conversion device for doubling/dividing the rate of a serial bit stream

Abstract

A device for doubling or dividing by 2 the flow rate of series bits comprising a succession of first one-bit registers (R4-R0) actuated at a frequency f; a second register (R) actuated at a frequency 2f; an input terminal (IN) connected to the input of the first (R4) of the first registers and, through a first gate (T5), to an internal line (L) connected to the input of the second register; first multiplexers (M4-M1) connected to the input of each second (R3) to last (R0) of the first registers for selecting either the output of the preceding register, or the internal line, or still the output of the second register; a second multiplexer (M), which selects either the output of the last (R0) of the first registers, or the output of the second register, or filling bits; second transfer gates (T4-T0) between the output of each first register and the internal line; and means for controlling the various gates and multiplexers.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a device transforming each word of a flow of series bitsstill, transfer gates, and one-cell registers.

On the other hand, the operation of the system has been explained by indicating the sequence of the control signals which have to be applied to transfer gates and multiplexers. The implementation of a logic circuit implementing these functions and supplying these successive control signals will be simple for those skilled in the art, who will be capable of pre-storing the control sequences to be applied to the various components in a memory or a programmable logic array, in a way known per se.

Among the advantages of the invention, it can be noted that the described device exhibits the advantage to be operable either as a divider or as a doubler, according to its control mode and that it is further mode. It is also simple to implement,since it is fully modular as a function of the number of data bits.

Calculation shows that if the number of data to be doubled is equal to N, the number of registers has to be equal to 2+N/2) if N is even and to 2+[(N-1)/2]if N is odd.

Claims

1. A device for doubling or dividing by 2 the rate of serial bits in a serial bit stream, comprising:

a succession of first one-bit registers (R4-R0) actuated at a frequency f,

a second register (R) actuated at a frequency 2f,

an input terminal (IN) connected to the input of the first (R4) among said first registers and, through a first gate (T5), to an internal line (L) connected to the input of said second register,

first multiplexers (M4-M1) respectively connected to the input of each (R3-R0) of said first registers for selecting either the output of the preceding register, or said internal line, or the output of said second register,

a second multiplexer (M), the output of which corresponds to the device output and which selects either the output of the last (R0) among said first registers, or the output of the second register, or filling bits,

second transfer gates (T4-T0) between the output of each first register and said internal line, and

means for controlling the various gates and multiplexers.

2. A device according to claim 1, connected as a doubler, wherein:

said first gate (T5) is inhibited and the input is constantly applied to the first among said first register (R4) of said first registers,

each first multiplexer (M4-M1) is designed to constantly connect the output of each first register to the following first register,

said second multiplexer (M) is controlled for alternatively supplying a succession of filling bits during the first half period of a word transmission duration, then the succession of outputs of said second register (R), and

each second transfer gate (T4-T0) is actuated so that the last (T0) among said second gates is first rendered conductive once, the following gates among said second gates rendered conductive twice, successively, and the last among said second gates reduced conductive once.

3. A device according to claim 1, connected as a divider, wherein:

said first gate (T5) is enabled for constantly connecting the input terminal (IN) to the input of said second register (R),

the second gates (T4-T0) are inhibited,

the output of the last (R0) among the first registers is constantly connected through said second multiplexer (M) to the output terminal (OUT),

said first multiplexers (M4-M1) are sequentially controlled for sending either of their inputs, in a predetermined order, to each first register (R3-R0). 4. A device according to claim 1, wherein each said gate is a 3-state buffer. 5. A device according to claim 1, for doubling the rate of 8-bit strings of data, comprising 6

of said first and second registers. 6. A device according to claim 1, for doubling the rate of N-bit strings of data where N is a predetermined even number, comprising 2+N/2 of said first and second registers. 7. A device according to claim 1, for doubling the rate of N-bit strings of data where N is a predetermined odd number, comprising 2+(N-1)/2 of said first and second registers. 8. A circuit for selectably doubling or halving the rate of an incoming bit stream, comprising:

a shift register comprising multiple stages connected to be operated at a first clock rate, and each having an input and an output; said stages of said shift register being operatively connected in series, with each pair of successive stages having a respective intermediate multiplexer interposed therebetween;

a plurality of gates, each connected to receive the output of a respective one of said stages, and to selectably drive said output onto a common line, said common line also being selectably connectable to receive the incoming bit stream,

an additional register connected to be operated at a multiple of said first clock rate, and connected to receive said common line as input, and to provide a corresponding output; and

an output multiplexer, connected to provide an output which is selected from among: said output of said additional register, a last one of said stages, and a constant value;

said intermediate multiplexers each being connected to receive as inputs said common line, said output of said additional register, and the output

of one of said stages. 9. The circuit of claim 8, for doubling the rate of 8-bit strings of data, comprising 5 of said stages. 10. The circuit of claim 8, for doubling the rate of N-bit strings of data where N is a predetermined even number, comprising 1+N/2 of said stages. 11. The circuit of claim 8 for doubling the rate of N-bit strings of data where N is a predetermined odd number, comprising 1+(N-1)/2 of said stages. 12. The circuit of claim 8, wherein each said transfer gate is a 3-state buffer.

13. A method for using a single circuit for selectably doubling or halving the bit rate of an incoming bit stream, comprising the steps of:

for doubling the bit rate:

connecting the incoming signal to a first stage of a shift register in which each intermediate stage is preceded and followed by a respective intermediate multiplexer.

operating said imtermediate multiplexers to connect all of said stages in series, and

during one half period of a word transmission duration, operating a plurality of transfer gates, which are each connected to receive the output of a respective one of said stages, to provide successive values, through a common line and an additional register which operates at twice said bit rate, to an output multiplexer, and operating said output multiplexer to provide said successive values as output, and

during the other half period of a word transmission duration, operating said output multiplexer to provide fill bits as output; and

for halving the bit rate:

connecting the incoming signal to said common line while inhibiting said transfer gates, and operating each said intermediate multiplexers to transfer into a respective one of said stages, in a predetermined order, either

bits of said incoming signal, from said common line or from said additional register, or

the output from a preceding one of said stages; and

operating said output multiplexer to provide said successive outputs from a

last one of said stages as output. 14. The method of claim 13 for doubling the rate if 8-bit strings of data, using 5 of said stages. 15. The method of claim 13, for doubling the rate of N-bit strings of data where N is a predetermined even number, using 1+N/2 of said stages. 16. The method of claim 13, for doubling the rate of N-bit strings of data where N is a predetermined odd number, using 1+(N-1)/2 of said stages. 17. The method of claim 13, wherein each said transfer gate is a 3-state buffer.